CN106411311B

CN106411311B - Output circuit

Info

Publication number: CN106411311B
Application number: CN201510461108.5A
Authority: CN
Inventors: 洪俊雄; 张坤龙; 陈耕晖; 罗思觉; 邱子庭
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2015-07-31
Filing date: 2015-07-31
Publication date: 2019-10-01
Anticipated expiration: 2035-07-31
Also published as: CN106411311A

Abstract

The invention discloses a kind of output circuits, comprising: an output switch, comprising a grid, a drain electrode and a trap pole, the drain electrode of output switch is coupled to one exterior I/O bus；One trap control circuit is coupled to the trap pole of output switch with a trap pole, and the greater of a first voltage and a second voltage is not less than with the trap voltage for maintaining the output to switch；One gate control circuit, it is coupled to the grid and the drain electrode of output switch, and it is coupled to the exterior I/O bus, the gate control circuit can end output switch, and to avoid electric current to flow through output switch from exterior I/O bus in following situations: an operation voltage of the output circuit is not applied to output switch；And the bus voltage from an external device (ED) occurs from the exterior I/O bus.

Description

Output circuit

Technical field

The invention relates to a kind of output buffers for integrated semiconductor circuit device, and in particular to A kind of output buffer avoiding current reflux when device is powered down.

Background technique

Output buffer is usually to be implemented in semiconductor product circuit, e.g. memory circuit and logic circuit, with Signal is transmitted and is amplified to the input buffer circuit of another device.Chip used herein is alternatively referred to as the integrated electricity of semiconductor Road.Chip can share exterior I/O bus, can pass through the corresponding input and output for being coupled to I/O bus through thus I/O bus chip Buffer circuit and mutually communicate.

Fig. 1 is painted the block diagram of legacy system 100, and wherein chip A 102 and chip B 104 share exterior I/O bus.Core Piece A 102 and chip B 104 separately include output buffer 106 and 108, and separately include input buffer circuit 110 and 112.The output buffer 106 of chip A 102 includes pMOS transistor 114 and nMOS transistor 116.PMOS transistor 114 Comprising drawing high (Pull-Up, PU) grid 118, drain electrode 120, source electrode 122 and trap pole 123.Trap pole 123 is coupled to source electrode 122, Source electrode 122 receives voltage VDD.NMOS transistor 116 includes to drag down (Pull-Down, PD) grid 124, drain electrode 126 and source electrode 128.The drain electrode 126 of nMOS transistor 116 is coupled to the source electrode 120 of pMOS transistor 114.The input of chip A 102 buffers Circuit 110 includes pMOS transistor 130 and nMOS transistor 132.PMOS transistor 130 includes grid 134, drain electrode 136, source electrode 138 with trap pole 139.Trap pole 139 is coupled to source electrode 138, and source electrode 138 is coupled to receive voltage VDD.NMOS transistor 132 Include grid 140, drain electrode 142 and source electrode 148.The drain electrode 142 of nMOS transistor 132 is coupled to the leakage of pMOS transistor 130 Pole 136.

The output buffer 108 of chip B 104 includes pMOS transistor 150 and nMOS transistor 152.PMOS transistor Include PU grid 154, drain electrode 156, source electrode 158 and trap pole 159.Trap pole 159 is coupled to source electrode 158, and source electrode 158 receives voltage VDD.NMOS transistor 152 includes that PD grid 160, drain electrode 162 and source electrode 164, source electrode 164 are coupled to pMOS transistor 150 Drain electrode 156.The input buffer circuit 112 of chip B 104 includes pMOS transistor 166 and nMOS transistor 168.PMOS crystal Pipe 166 includes pole grid 170, drain electrode 172, source electrode 174 and trap pole 175.Trap pole 175 is coupled to source electrode 174, and source electrode 174 receives Voltage VDD.NMOS transistor 168 includes grid 176, drain electrode 178 and source electrode 180.The drain electrode 178 of nMOS transistor 168 is by coupling It is connected to the drain electrode 172 of pMOS transistor 166.

182 coupling chip A 102 and chip B 104 of exterior I/O bus.For chip A 102, exterior I/O bus 182 Be coupled to the drain electrode 120 of pMOS transistor 114, the drain electrode 126 of nMOS transistor 116, pMOS transistor 130 grid 134 With the grid 140 of nMOS transistor 132.For chip B 104, exterior I/O bus 182 is coupled to pMOS transistor 150 Drain electrode 156, the drain electrode 162 of nMOS transistor 152, the grid 170 of pMOS transistor 166 and nMOS transistor 168 grid 176.Through coupling exterior I/O bus 182 between chip A 102 and chip B 104, the data signals from chip A 102 It can transmit to chip B 104.In more detail, the output buffer 106 of chip A 102 transmits data traffic via I/O bus 182 Number to chip B 104 input buffer circuit 112.Similarly, data signals can be sent to chip A 102 from chip B 104.

Summary of the invention

According to the first aspect of the invention, a kind of output circuit is proposed, comprising: an output switch includes a grid, a leakage The drain electrode of pole and a trap pole, output switch is coupled to one exterior I/O bus；One trap control circuit has trap pole coupling The trap pole switched to the output, with maintain the output to switch a trap voltage not less than a first voltage and a second voltage The greater；And a gate control circuit, it is coupled to the grid and the drain electrode of output switch, and be coupled to the exterior I/O bus, The gate control circuit is operable to end output switch, to avoid there is electric current to flow through from exterior I/O bus in following situations Output switch: an operation voltage of the output circuit is not applied to output switch；And one from an external device (ED) is total Line voltage occurs from the exterior I/O bus.

According to the second aspect of the invention, propose a kind of output circuit, comprising: an output switch, operate when Yu Qidong with A data signals to one exterior I/O bus is supplied, output switch includes a grid, a drain electrode and a trap pole；One trap control electricity Road is coupled to the trap pole of output switch with a trap pole, is not less than one first with the trap voltage for maintaining the output to switch The greater of voltage and a second voltage, wherein the first voltage is that an operation voltage of the output circuit subtracts D1；This second Voltage is that the exterior I/O bus bus voltage subtracts D2；And D1 and D2 are respectively positive or zero；One input switch, is coupled to The grid of output switch；One grid control circuit is coupled to the grid and the drain electrode, the exterior I/O of output switch Bus and the input switch；One bias generator is coupled to a grid of the input switch, to maintain a bias to be greater than the output The sum of the operation voltage and a threshold voltage of the input switch of circuit；And a voltage discharge circuit, it is coupled to the bias The grid of generator, the trap control circuit and the input switch, with the operation voltage of the output circuit reduce when, to this The bias caused by bias generator discharges.

According to the third aspect of the invention we, propose a kind of output circuit, comprising: an output switch, operate when Yu Qidong with A data signals to one exterior I/O bus is supplied, output switch includes a grid, a source/drain and a trap pole；The control of one trap Circuit is coupled to the trap pole of output switch with a trap pole, with maintain the output to switch a trap voltage not less than one the The greater of one voltage and a second voltage, wherein the first voltage is that an operation voltage of the output circuit subtracts D1；This Two voltages are that the exterior I/O bus bus voltage subtracts D2；And D1 and D2 are respectively positive or zero；One input switch, coupling Between source/drain and the exterior I/O bus of output switch, and operate with disconnected from the I/O bus and output switch Open (disconnect)；One bias generator is coupled to a grid of the input switch, to maintain a bias to be greater than output electricity The sum of the operation voltage and a threshold voltage of the input switch on road；And a voltage discharge circuit, it is coupled to bias production The grid of raw device, the trap control circuit and the input switch, it is inclined to this with when the operation voltage of the output circuit reduces The bias caused by pressure generator discharges.

More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates institute Accompanying drawings are described in detail below:

Detailed description of the invention

Institute's accompanying drawings merge referring to being part of specification, and are painted embodiment according to the present invention, and in explanation Appearance, which is shared on, illustrates the principle of the present invention.

Fig. 1 is painted the block diagram that multiple chips share the legacy system of a common exterior I/O bus.

Fig. 2A is painted the configuration diagram of the output buffer according to exemplary embodiment of the present invention.

Fig. 2 B is painted another framework of the output buffer realized with VIO mode according to exemplary embodiment of the present invention Schematic diagram.

Fig. 3 is painted the exemplary circuit diagram of first embodiment.

Fig. 4 A- Fig. 4 C is painted the circuit diagram of the trap control element according to exemplary embodiment of the present invention.

Fig. 5 A- Fig. 5 B is painted another configuration diagram of the trap control element according to exemplary embodiment of the present invention.

Fig. 6 is painted the circuit diagram of the framework according to exemplary embodiment of the present invention.

Fig. 7 is painted the circuit diagram of the framework according to exemplary embodiment of the present invention.

[symbol description]

100: system

102: chip A

104: chip B

106,108,200,300,600,700: output buffer

110,112: input buffer circuit

114,130,150,166,202,302,320,322,402,439,440,602,608,620,640,702,730: PMOS transistor

116,132,152,168,318,404,422,424,606,638,706,728:nMOS transistor

118、124、134、140、154、160、170、176、208、308、319、324、332、406、414、426、432、 442,450,614,624,630,642,648,712,720,732,738: grid

120、126、136、142、156、162、172、178、210、310、321、326、334、408、416、428、434、 444,452,616,626,632,644,650,714,722,734,740: drain electrode

122、128、138、148、158、164、174、180、212、312、323、328、336、410、418、430、436、 446,454,618,628,634,646,652,716,724,736,742: source electrode

123,139,159,175,214,313,330,338,412,420,438,448,456,636,654,718,744: Trap pole

182,215,622,726: exterior I/O bus

204,304: gate control circuit

206,306,400A, 400B, 400C, 500A, 500B, 500C, 604,704: trap control circuit

216: level shift circuit

225: internal circuit

610,708: bias generator

612,710: voltage discharge circuit

Vout, VDD, VIO: voltage

Data: data signals

Specific embodiment

It will elaborate referring to the embodiment of the present invention, these, which implement example, will cooperate schema to explain.Being described below will Referring to institute's accompanying drawings, identical or similar element is to represent identical or similar element other than another predetermined justice in schema.Below The implementation presented in the description of exemplary embodiment does not represent all implementations of the present invention, and only represents and want according to appended right The System and method for example seeking the related fields of the invention of range and realizing.

In exemplary embodiment, a kind of output buffer is provided, includes output switch, gate control circuit and trap control Circuit.Output buffer is to be coupled to exterior I/O bus via output switch.

In more detail, in exemplary embodiment, when circuitaoperating voltage is not applied to output switch, output buffering Circuit avoids electric current from flowing through output switch from exterior I/O bus.Output buffer is so that total from exterior I/O bus Line voltage is coupled to trap control circuit and gate control circuit.

Fig. 2A is painted the configuration diagram of the output buffer 200 according to exemplary embodiment of the present invention.Output buffering Circuit 200 includes output switch e.g. pMOS transistor 202, gate control circuit 204 and trap control circuit 206.Gate control electricity Road 204 is coupled to internal circuit 225 to receive data.PMOS transistor 202 include grid 208, drain electrode 210, source electrode 212 and Trap pole 214.Drain electrode 210 is coupled to gate control circuit 204.Drain electrode 210 is more to be coupled to exterior I/O bus 215.I/O bus 215 have bus voltage.Source electrode 212 receives circuitaoperating voltage VDD (also that is, builtin voltage 225 and output buffer 200 Operation voltage).The grid 208 of pMOS transistor 202 is coupled to gate control circuit 204.Trap control circuit 206 is coupled to The trap pole 214 of pMOS transistor 202.

Fig. 2 B is painted another configuration diagram of the output buffer 220 according to exemplary embodiment of the present invention.Output The element of buffer circuit 220 is the same as the element of output buffer 200 and indicates identical reference number, and element illustrates not It repeats again.The source electrode 212 of output buffer 220 receives voltage VIO.Voltage VIO is the operation electricity of output buffer 220 Pressure.Voltage VIO may differ from internal circuit operation voltage VDD.Source electrode 212 is coupled to gate control circuit 204 and level shift Circuit 216.Level shift circuit 216 receive level be internal circuit operate voltage VDD a data signals, and by level from VDD changes to VIO, therefore VIO provides this data signals to exterior I/O bus 215.By in a manner of, internal circuit operates voltage VDD It is to be isolated with output buffer operation voltage VIO.In one embodiment, level shift circuit 216 reduces the voltage of data signals, by To reduce the energy consumption of exterior I/O bus 215 in VDD > VIO.

There is the framework of the similar output buffer in Fig. 2A in relation to Fig. 3-Fig. 7 the embodiment described circuit, wherein only There is internal circuit operation voltage VDD to be provided to the pMOS transistor 202, gate control circuit 204 and trap of output buffer 200 Control circuit 206.However, tool usually intellectual should know related Fig. 3-Fig. 7 the embodiment described circuit with similar in Fig. 2 B Framework, internal circuit operation voltage VDD is to be shifted first by level shift circuit 216 and become VIO, and VIO is (non-in tool VDD the pMOS transistor 202, gate control circuit 204 and trap control circuit 206 of output buffer 220) are provided to.When having Close Fig. 3-Fig. 7 the embodiment described circuit have it is similar when the framework of Fig. 2 B, when device is powered down (that is, circuit close Close pattern), VDD and VIO are also closing.

Exterior I/O bus 215 driving source is to dynamically change.Sometimes exterior I/O bus 215 is by pMOS transistor 202 output is driven.Sometimes exterior I/O bus 215 is that the output institute of exterior I/O bus 215 chip is coupled to by other Driving.Sometimes exterior I/O bus 215 is not driven, that is, exterior I/O bus 215 is suspension joint.No matter exterior I/O bus 215 Driving source why, always have the voltage of a limited voltages level in external I/O bus 215, e.g. no-voltage. Therefore, the voltage appeared in exterior I/O bus 215 is known as " bus voltage ".

Referring again to Fig. 2A, when chip power is closed, output buffer 200 is to avoid electric current from exterior I/O bus 215 are back in chip.The drain electrode 210 of pMOS transistor 202 is coupled to exterior I/O bus 215, total to provide exterior I/O The bus voltage of line 215 to pMOS transistor 202 drain electrode 210.Exterior I/O bus 215 is more to be coupled to gate control circuit 204.Gate control circuit 204 corresponds to exterior I/O bus 215 bus voltage and operates.The exemplary frame of gate control circuit 204 Structure is as described below.It is coupled to the trap control circuit 206 of the trap pole 214 of pMOS transistor 202, is the electricity maintained on trap pole 214 The greater of a first voltage and a second voltage is pressed and is not less than, to avoid the leakage current in pMOS transistor 202.First electricity Pressure is that internal circuit operation voltage VDD subtracts D1, and wherein D1 is positive or zero.Second voltage is that exterior I/O bus 215 is total Line voltage subtracts D2, and D2 is respectively positive or zero.D1 and D2 can be equal or different.In this framework, pMOS transistor 202 is in core It can be turned fully off when (VDD=0) and chip are turned on power supply (VDD=1.8V) when piece power supply is closed.Therefore, cut-off pMOS is brilliant Body pipe 202 and maintenance trap voltage can avoid current reflux.

B referring to figure 2., output buffer 220 are configured to avoid electric current total from exterior I/O when chip power is closed Line 215 is back in chip, and is configured using the circuitaoperating voltage VDD of conversion chip as exterior I/O bus 215 voltage. The drain electrode 210 of pMOS transistor 202 is coupled to exterior I/O bus 215, to provide exterior I/O bus 215 bus voltage extremely The drain electrode 210 of pMOS transistor 202.Exterior I/O bus 215 is coupled to gate control circuit 204.Gate control circuit 204 is corresponding It is operated in exterior I/O bus 215 bus voltage.It is coupled to the trap control circuit 206 of the trap pole 214 of pMOS transistor 202, It is to maintain the voltage on trap pole 214 and the greater not less than a second voltage and a tertiary voltage, to avoid pMOS transistor Leakage current in 202.Second voltage is that exterior I/O bus 215 bus voltage subtracts D2, and D2 is respectively positive or zero.Third Voltage is that the operation voltage VIO of output buffer 220 subtracts D3, and wherein D3 is positive or zero.D2 and D3 can be equal or not Together.Furthermore the level shift circuit 216 of output buffer 220 reduces the voltage of data signals VDD to the I/O voltage of VIO, Use reduction exterior I/O bus 215 voltage.In this way, output buffer 220 is powered down in mode in chip keeps away Exempt from exterior I/O bus 215 current reflux, and isolation internal circuit operation voltage VDD and output are slow in opening electric source modes Punching operation voltage VIO.

Fig. 3 is painted the exemplary circuit diagram of the output buffer 300 of previous embodiment.Output buffer 300 is defeated The exemplary implementation of buffer circuit 200 out.Referring to figure 3., output buffer 300 includes that (e.g. pMOS is brilliant for output switch Body pipe MP 302), gate control circuit 304 and trap control circuit 306, be respectively corresponding to output buffer 200 (Fig. 2A) PMOS transistor 202, gate control circuit 204 and trap control circuit 206.PMOS transistor MP 302 include draw high (Pull-Up, PU) grid 308, drain electrode 310, source electrode 312 and trap pole 313.Drain electrode 310 is coupled to exterior I/O bus 314, exterior I/O bus 314 have bus voltage Vout.PU grid 308, drain electrode 310, source electrode 312 and the trap pole 313 of pMOS transistor MP 302 is distinguished It corresponds to the grid 208 of pMOS transistor 202 (Fig. 2A), drain electrode 210, source electrode 212 and trap pole 214.Source electrode 312 is coupled to connect Receive VDD.Gate control circuit 304 is coupled to the PU grid 308 of pMOS transistor 302.Gate control circuit 304 include input switch with It avoids in current reflux to chip, such as is coupled to the nMOS transistor MN1 of the PU grid 308 of pMOS transistor MP 302 318, the first pMOS transistor MP1 320 and the 2nd pMOS transistor MP2 322.NMOS transistor MN1 318 includes grid 319, drain electrode 321 and source electrode 323.Grid 319 is coupled to receive VDD.Drain electrode 321 is coupled to receive data signals 0 or 1. First pMOS transistor MP1 320 includes grid 324, drain electrode 326, source electrode 328 and trap pole 330.Grid 324 is coupled to receive Bus voltage Vout.Drain electrode 326 is coupled to the PU grid 308 and nMOS transistor MN1's 318 of pMOS transistor MP 302 Source electrode 323.The source electrode 328 of first pMOS transistor MP1 320 is coupled to receive voltage VDD.2nd pMOS transistor 322 packet Containing grid 332, drain electrode 334, source electrode 336 and trap pole 338.Grid 332 is coupled to receive VDD.Drain electrode 334 is coupled to pMOS The source of the PU grid 308 of transistor MP 302, the drain electrode 326 of the first pMOS transistor MP1 320 and nMOS transistor MN1 318 Pole 323.The source electrode 336 of 2nd pMOS transistor MP2 322 is coupled to receive bus voltage Vout.First pMOS transistor The trap pole 330 and 338 of MP1 320 and the 2nd pMOS transistor MP2 322 are coupled together.Trap control circuit 306 is coupled to The trap pole 313 of pMOS transistor MP 302.The trap pole 330 and 338 of first pMOS transistor MP1 and the 2nd pMOS transistor MP2 It is also coupled to trap control circuit 306.In some embodiments, the trap pole 313 of pMOS transistor 302, the first pMOS transistor MP1 320 and the 2nd pMOS transistor MP2 322 trap pole 330 and 338, may be coupled to different trap control circuits respectively.Trap control The exemplary framework of circuit 306 is as described below.

As shown in Figure 2 A and 2 B, trap control circuit 206 is coupled to the electricity of the trap pole 214 of control pMOS transistor 202 Pressure.In Fig. 3, trap control circuit is coupled to control the trap pole 313,330 and 338 of pMOS transistor 302,320,322 respectively Voltage.Fig. 4 A- Fig. 4 C is painted the circuit diagram of the trap control circuit 400A-400C according to exemplary embodiment of the present invention.Scheming In 4A- Fig. 4 C, each exemplary trap control circuit is arranged to control trap pole tension, so that the pMOS that trap control circuit is coupled is brilliant Body pipe can effectively be ended machine in due course.In order to effectively end each pMOS transistor, when the grid of pMOS transistor receives When voltage VDD, trap voltage should be not less than drain electrode and the maximum value of the voltage on source electrode.If trap voltage is less than on drain electrode and source electrode The maximum value of voltage, there may be leakage currents for pMOS transistor.

It include the first pMOS transistor 402 and the 2nd pMOS crystal of coupled in series referring to Fig. 4 A, trap control circuit 400A Pipe 404.First pMOS transistor 402 includes grid 406, drain electrode 408, source electrode 410 and trap pole 412.2nd pMOS transistor 404 Include grid 414, drain electrode 416, source electrode 418 and trap pole 420.The grid 406 of first pMOS transistor 402 is coupled to receive always Line voltage Vout.The drain electrode 408 of first pMOS transistor 402 is coupled to the drain electrode 416 of the 2nd pMOS transistor 404.Source electrode 410 are coupled to receive VDD.The trap pole 412 of first pMOS transistor 402 is coupled to 404 trap pole of the 2nd pMOS transistor 420, and it is coupled to drain electrode 408 and 416.The grid 414 of 2nd pMOS transistor 404 is coupled to receive VDD, and source electrode 418 It is coupled to receive Vout.

For convenience of explanation, when VDD is high, VDD is provided as circuitaoperating voltage (such as 1.8V or 3.0V).Work as VDD When being low, VDD is provided as 0V.Similarly, when Vout is high, Vout is provided as VDD or VIO, respectively represents circuit behaviour Make voltage or such as the voltage after reducing as provided by level shift circuit 216.When Vout is low, Vout is provided as 0V.

During the operation of trap control circuit 400A, when VDD and Vout is high, the voltage on trap pole 412 and 420 is VDD-Vdiode, wherein Vdiode be each pMOS transistor 402,404 source electrode and drain electrode formed in PN junction electric conduction Pressure.When Vout is low and VDD is high, the voltage on trap pole 412 and 420 is VDD.When Vout is high and VDD is low, trap pole Voltage on 412 and 420 is Vout.When Vout and VDD are all low, for suspension joint, this is electric for the voltage on trap pole 412 and 420 It is high for pressing for low Vout and low VDD.With this framework, as VDD ≠ Vout, trap control circuit is coupled PMOS transistor (such as pMOS transistor 202,302,320,322) is not in leakage current, therefore can be completely switched off.Work as VDD= When Vout, trap voltage is VDD-Vdiode, this voltage is enough to inhibit leakage current.

B referring to figure 4., trap control circuit 400B include the first nMOS transistor 422 and the 2nd nMOS crystalline substance of coupled in series Body pipe 424.First nMOS transistor 422 includes grid 426, drain electrode 428 and source electrode 430.Second nMOS transistor 424 includes grid Pole 432, drain electrode 434 and source electrode 436.Grid 426 and 432 is to be respectively coupled to drain electrode 428 and 434.Source electrode 430 and 436 is by coupling It is connected together and is coupled to trap pole 438.The drain electrode 428 of first nMOS transistor 422 is coupled to receive VDD, and the 2nd nMOS is brilliant The drain electrode 434 of body pipe 424 is coupled to receive Vout.

During the operation of trap control circuit 400B, when VDD and Vout is high, the voltage on trap pole 438 is equal to following The maximum of two voltages: VDD subtracts the threshold voltage vt 422 (i.e. VDD-Vt422) of the first nMOS transistor 422 and VDD is subtracted The threshold voltage vt 424 (i.e. VDD-Vt424) of second nMOS transistor 424.Across the first nMOS transistor 422 or the 2nd nMOS The voltage drop Vtn of transistor 424 is generated when electric current flows through the first nMOS transistor 422 or the second nMOS transistor 424, and Lead to trap voltage VDD-Vtn.When Vout is low and VDD is high, the voltage on source electrode 430 and 436 is VDD-Vt422.When Vout is high and VDD when being low, and the voltage on source electrode 430 and 436 is VDD-Vt424.When Vout and VDD are all low, source electrode For suspension joint, this voltage is higher than low Vout and low VDD to voltage on 430 and 436.With this framework, work as VDD=Vout, trap The pMOS transistor (such as pMOS transistor 202,302,320,322) that control circuit is coupled is not in leakage current, therefore can It is completely switched off.As VDD ≠ Vout, trap voltage is VDD-Vtn, this voltage is enough to inhibit leakage current.

C referring to figure 4., trap control circuit 400C include the first pMOS transistor 439 and the 2nd pMOS crystalline substance of coupled in series Body pipe 440.First pMOS transistor 439 includes grid 442, drain electrode 444, source electrode 446 and trap pole 448.2nd pMOS transistor 440 include grid 450, drain electrode 452, source electrode 454 and trap pole 456.The drain electrode 444 of first pMOS transistor 439 is coupled to The drain electrode 452 of two pMOS transistors 440.The coupling of grid 442 and 450 of first pMOS transistor 439 and the 2nd pMOS transistor 440 Be connected to each other, be coupled to drain electrode and 444 and 452 and be coupled to trap pole 448 and 456.446 quilt of source electrode of first pMOS transistor 439 To receive VDD, the source electrode 454 of the 2nd pMOS transistor 440 is coupled to receive Vout for coupling.

During the operation of trap control circuit 400C, when VDD and Vout is high, drain electrode 428 is with the voltage on 434 The higher person of VDD-Vtp or VDD-Vdiode.Electric current flow through the first pMOS transistor 439 or the 2nd pMOS transistor 440 it When, trap voltage is VDD-Vtp, and generates the voltage drop for being equal to the first pMOS transistor 439 and the 2nd pMOS transistor 440 Vtp.When Vout is low and VDD is high, drain electrode 444 and 454 on voltage for VDD-Vtp or VDD-Vdiode the higher person. When Vout is high and VDD is low, voltage on source electrode 444 and 454 for VDD-Vtp or VDD-Vdioe the higher person.Work as Vout When with VDD being all low, for suspension joint, this voltage is for low Vout and low VDD for the voltage on source electrode 444 and 454 It is high.With this framework, work as VDD=Vout, pMOS transistor that trap control circuit is coupled (such as pMOS transistor 202,302, It 320,322) is not in leakage current, therefore can be completely switched off.As VDD ≠ Vout, trap voltage is VDD-Vtp or VDD- Vdiode, this voltage are enough to inhibit leakage current.

Fig. 5 A- Fig. 5 B is painted multiple alternative architectures of the trap control circuit 206 or 306 according to exemplary embodiment of the present invention Schematic diagram.Fig. 5 A and Fig. 5 B are painted multiple trap control circuits 400A, 400B combined in parallel and 400C.These trap controls of configured in parallel Circuit 400A, 400B and 400C (Fig. 4 A- Fig. 4 C) processed allow the control trap voltage in VDD=Vout and VDD ≠ Vout.Fig. 5 A mark Trap control circuit 500A is formed by coupled in parallel trap control circuit 400A and 400B.The leakage of first nMOS transistor 422 Pole 428 is coupled to the source electrode 410 of the first pMOS transistor 402.The drain electrode 434 of second nMOS transistor 424 is coupled to The source electrode 418 of two pMOS transistors 524.The source electrode 430 of first nMOS transistor 422 is coupled to the second nMOS transistor 424 Source electrode 436, source electrode 436 is coupled to drain electrode 408 and trap pole 412 and the 2nd pMOS transistor 404 of the first pMOS transistor 402 Drain electrode 416 and trap pole 420.

Fig. 5 B is painted trap control circuit 500B and is formed by trap control circuit 400A, 400B and 400C of coupled in parallel. The drain electrode 428 of first nMOS transistor 422 is coupled to the source electrode 410 of the first pMOS transistor 402.Second nMOS transistor 424 drain electrode 434 is coupled to the source electrode 418 of the 2nd pMOS transistor 404.The source electrode 430 of first nMOS transistor 422 is by coupling It is connected to the source electrode 436 of the second nMOS transistor 424, source electrode 436 is coupled to drain electrode 408 and the trap pole of the first pMOS transistor 402 412 and the 2nd pMOS transistor 404 drain electrode 416 and trap pole 420.The grid 422 and the 2nd pMOS of first pMOS transistor 439 The grid 450 of transistor 440 be respectively coupled the trap pole 448 of the first pMOS transistor 439 and the 2nd pMOS transistor 440 with 456 and drain electrode 444 and 452, the source electrode 436 of the source electrode 430 of the first nMOS transistor 422 and the second nMOS transistor 424 is by coupling It is connected to drain electrode 408 and 416 and the trap pole 412 and 420 of the first pMOS transistor 402 and the 2nd pMOS transistor 404.First pMOS The source electrode 446 of transistor 439 is coupled to the drain electrode 428 of the first nMOS transistor 422 and the source electrode of the first pMOS transistor 402 410.The source electrode 454 of 2nd pMOS transistor 402 is coupled to drain electrode 434 and the 2nd pMOS crystalline substance of the second nMOS transistor 424 The source electrode 418 of body pipe 404.

Referring once again to Fig. 3, in exemplary embodiment, output buffer 300 is configuration to close in chip power When avoid electric current from flowing back in chip.A variety of different operation examples of output buffer 300 are in lower consideration.In first example In, circuitaoperating voltage VDD is 1.8V, and data signals (Data) are 1.8V, and the voltage Vout in I/O bus 314 is 1.8V.? In this example, when the bus voltage Vout in exterior I/O bus 314 is 1.8V, trap control circuit 306 maintains the voltage of 1.8V It is brilliant in the trap pole 313 of pMOS transistor MP 302 and the first pMOS transistor MP1 320 and the 2nd pMOS of gate control circuit 304 The other trap pole 330 and 338 body pipe MP2 322.First pMOS transistor MP1 320 and the 2nd pMOS transistor MP2 322 are All end, so that the VDD being respectively provided on source electrode 328 and 336 and Vout can not all be respectively applied to drain electrode 326 and 334.Cause This, VDD and Vout on source electrode 328 and 336 can not all be applied to PU grid 308.Conversely, grid PU 308 receives data traffic Number VDD subtracts the threshold voltage vt n, VDD-Vtn of nMOS transistor MN1 318.Since VDD-Vtn is less than circuitaoperating voltage The greater of VDD and Vout, therefore pMOS transistor MP 302 may have leakage current.However, this leakage current is terminated with the time.Such as This, pMOS transistor MP 302 can be ended.

In second example, circuitaoperating voltage VDD is 1.8V, and data signals (Data) are 1.8V, in I/O bus 314 Voltage Vout be 0V.In this example, when the bus voltage Vout in exterior I/O bus 314 is 0V, the first pMOS crystal Pipe MP1 320 is connected because the voltage on grid 324 is 0V, so that PU grid 308, which receives, comes from the first pMOS transistor MP1 The voltage VDD of 320 source electrode 328.2nd pMOS transistor MP2 322 is off, so that the Vout on source electrode 336 can not be sent To source electrode 334, therefore will not be received by the PU grid 308 of pMOS transistor MP 302.Therefore, passing through nMOS transistor MN1 After 318, the voltage value of data signals VDD can reduce the threshold voltage vt n of nMOS transistor 318, and become VDD-Vtn, however It can be then charged to VDD, because VDD is received from the source electrode 328 of the first pMOS transistor MP1 320.When pMOS crystalline substance When the PU grid 308 of body pipe 302 receives VDD, pMOS transistor 302 is off.

In third example, circuitaoperating voltage VDD is 1.8V, and data signals (Data) are 0V, in I/O bus 314 Voltage Vout is to increase to 1.8V from 0V.In this example, when the voltage in I/O bus 314 is 0V, it is applied to pMOS crystal Voltage on the PU grid 308 of pipe MP 302 is 0V.2nd pMOS transistor MP2 322 is to be ended.First pMOS transistor MP1 320 is turned on when being initially at Vout equal to 0V.In this way, the voltage on the source electrode 328 of the first pMOS transistor MP1 320 The 0V of VDD and the received data signals of nMOS transistor MN1 318, are " conflicts ".However, nMOS transistor MN1 318 is compared, The size of pMOS transistor MP1 320 is smaller and has lesser driving current, it is ensured that the 308 received voltage of institute of PU grid is next From the data signals 0V of nMOS transistor MN1 318.After Vout increases to 1.8V, the first pMOS transistor MP1 320 cut-off, And the voltage of 0V is received by PU grid 308, so that pMOS transistor MP 302 be connected.The source electrode of pMOS transistor MP 302 VDD on 312 is then applied to exterior I/O bus 314.

Therefore, in the exemplary embodiment of Fig. 3, when VDD is 1.8V and data signals are 1.8V, pMOS transistor MP 302 are off.When VDD is 1.8V and data signals are 0V, pMOS transistor MP 302 is conducting.In this way, when chip starts When (VDD 1.8V), high data signals end pMOS transistor MP 302, and avoid current reflux.Trap control circuit 306 is tieed up Holding can inhibit the trap of leakage current to control, and allow to end these pMOS transistors.

In fourth example, circuitaoperating voltage VDD is 0V, and the voltage Vout in I/O bus 314 is 1.8V.In this example In son, when bus voltage Vout is 1.8V, trap pole 313 receives the 1.8V of the Vout from trap control circuit 306.Gate control electricity The respective trap pole 330 and 338 of first and second pMOS transistor 320 and 322 on road 304 also receives the 1.8V of Vout.First PMOS transistor 320MP1 is off, because its grid 324 receives the 1.8V of Vout.2nd pMOS transistor 322MP2 is conducting, Because its grid 332 receives the VDD of 0V, the 2nd pMOS transistor 322MP2 is greater than MP1 and provides higher driving force, such as MP1 With the width length ratio bigger than MP2.Therefore, the 1.8V of the Vout of the source electrode 336 from pMOS transistor 322 is applied to pMOS The PU grid 308 of transistor MP 302.The 1.8V of Vout on PU grid 308 ends pMOS transistor MP 302, therefore keeps away Exempt from electric current and flows into output buffer 300 from exterior I/O bus 314.

In fifth example, circuitaoperating voltage VDD is 0V, and the voltage Vout in I/O bus 314 is 0V.In this example In, when bus voltage is 0V, VDD is equal to 0V.Apply Vout the pMOS transistor of 0V to the first MP1 320 grid 324 and The grid 332 of the pMOS transistor of 0V to the 2nd MP2 322 of VDD, and two transistor is connected.2nd pMOS transistor MP2 322 It is sufficiently large and allows the voltage on PU grid 308 that can change with (track) Vout.PU grid 308, which receives, comes from source electrode 328 VDD and Vout from source electrode 336.In this instance, the PU grid 308 of pMOS transistor MP 302, drain electrode 310 and source electrode 312 be to be in 0V.Trap pole 313 be suspension joint and be higher than 0V.Therefore, pMOS transistor MP 302 is off, and is avoided in pMOS There is leakage current flow in transistor MP 302.Furthermore nMOS transistor MN1 318 avoids the electric current when chip power is closed from returning Stream, because nMOS transistor MN1 318 will be ended when VDD is low.

Therefore, in the exemplary embodiment of Fig. 3, when VDD is 0V and Vout is 1.8V, pMOS transistor MP 302 is Cut-off.Similarly, when VDD is 0V and Vout is 0V, pMOS transistor MP 302 is off.By this method, work as chip power When closing, trap control circuit 306 maintains trap voltage to inhibit leakage current, and allows to end these pMOS transistors.

In an exemplary embodiment, shown in Fig. 6, output buffer 600 is configuration to allow data signals Data to send Up to output switch 602 and there is no voltage drop.Referring to Fig. 6, output buffer 600 includes output switch e.g. pMOS transistor MP 602, trap control circuit 604 and input switch are, for example, that nMOS transistor MN1 606, gate control circuit are, for example, pMOS crystalline substance Body pipe MP2 608, bias generator 610 and voltage discharge circuit 612.PMOS transistor MP 602 includes PU grid 614, drain electrode 616, source electrode 618 and trap pole 620.The drain electrode 616 of pMOS transistor MP 602 is coupled to exterior I/O bus 622.618 coupling of source electrode It is connected to circuitaoperating voltage VDD.Trap control circuit 604 is coupled to the trap pole 620 of pMOS transistor MP 602.Trap control circuit 604 can either as described in Fig. 4 A- Fig. 4 C and Fig. 5 A and Fig. 5 B formula and be configured.

NMOS transistor MN1 606 is coupled to the PU grid 614 of pMOS transistor MP 602.NMOS transistor MN1 606 include grid 624, drain electrode 626 and source electrode 628.PMOS transistor MP2 608 includes grid 630, drain electrode 632, source electrode 634 And trap pole 636.The drain electrode 632 of pMOS transistor MP2 608 is coupled to the PU grid 614 of pMOS transistor MP 602, and coupling It is connected to the source electrode 628 of nMOS transistor MNI 606.Source electrode 634 is coupled to receive Vout.The trap of pMOS transistor MP2 608 Pole 636 is coupled to trap control circuit 604.In some embodiments, the trap pole 636 of pMOS transistor MP2 608 and pMOS are brilliant The trap pole 620 of body pipe 602 is coupled to different trap control circuits.

Voltage discharge circuit 612 includes the nMOS transistor 638 and pMOS transistor 640 of coupled in series.NMOS transistor 638 include grid 642, drain electrode 644 and source electrode 646.Grid 642 is coupled to exterior I/O bus 622 and receives Vout.PMOS is brilliant Body pipe 640 includes grid 648, drain electrode 650, source electrode 652 and trap pole 654.Grid 648 and drain electrode 650 are coupled to receive circuit Operate voltage VDD.Voltage discharge circuit 612 is coupled to bias generator 610 and the grid 624 of nMOS transistor MN1 606. Trap pole 620, the trap pole 636 of pMOS transistor MP2 608 and the trap pole 654 of pMOS transistor 640 of pMOS transistor MP 602 It is coupled to trap control circuit 604.In some embodiments, the trap pole 620 of pMOS transistor MP 602, pMOS transistor MP2 608 trap pole 636 and the trap pole 654 of pMOS transistor 640 are coupled to different control circuits.

In exemplary embodiment, output buffer 600 (Fig. 6) avoids when chip power is closed current reflux to core Among piece.Fig. 6 is please referred to, when chip power is closed, VDD 0V.When the bus voltage Vout in exterior I/O bus 622 is When 1.8V, Vout is applied to the drain electrode 616 of pMOS transistor 602, and is coupled to the source electrode 634 of pMOS transistor MP2 608. VDD on the grid of pMOS transistor MP2 608 is 0V, so that pMOS transistor MP2 608 is connected, and on source electrode 634 Vout is applied to the PU grid 614 of pMOS transistor 602.It is applied to the Vout cut-off pMOS transistor MP of PU grid 614 602.Therefore, it may not flow into external buffer circuit from exterior I/O bus 622 electric current.Similarly, when exterior I/O bus 622 On bus voltage Vout be low (such as 0V) and chip power when closing, VDD is equal to 0V.Apply the 0V of VDD to grid 630 and PMOS transistor MP2 608 is connected, so that the voltage on the source electrode 634 of pMOS transistor MP2 608 is applied in pMOS crystal On the PU grid 614 of pipe MP 602.In this instance, on the grid 614 of pMOS transistor MP 602, drain electrode 616 and source electrode 618 Voltage is equal to 0V.Trap pole 620 is suspension joint.Since the voltage on trap pole 620 (suspension joint) is connect from trap control circuit 604 It receives, and is higher than drain electrode 616 and the voltage on source electrode 618, so leakage current is avoided to flow through pMOS transistor 602.Therefore, electric current is not Output buffer 600 can be flowed into from exterior I/O bus 622.Furthermore VDD be 0V when, nMOS transistor MN1 606 be by Cut-off, therefore nMOS transistor MN1 606 avoids having electric current to flow back into chip when chip power is closed.On the other hand, work as VDD When for 1.8V, the bias Vbias that bias generator 610 is supplied is greater than the sum of VDD and the threshold voltage vt n of nMOS transistor 606. This allows full width data signals (VDD) by nMOS transistor without having voltage drop.Voltage discharge circuit 612 includes series connection coupling The nMOS transistor 638 and pMOS transistor 640 connect is to there is voltage drop because chip is powered down in bias generator 610 When, it discharges voltage.

In an exemplary embodiment, as shown in fig. 7, output buffer 700 is to be configured to avoid from exterior I/O The electric current of bus flows into chip.Fig. 7 is please referred to, output buffer 700 includes output switch e.g. pMOS transistor MP 702, trap control circuit 704, input switch are, for example, nMOS transistor MN2 706, bias generator 708 and voltage discharge circuit 710.PMOS transistor MP 702 includes PU grid 712, drain electrode 714, source electrode 716 and trap pole 718.Source electrode 716 is coupled to receive Circuitaoperating voltage VDD.Trap control circuit 704 is coupled to trap pole 718.Trap control circuit 704 can such as Fig. 4 A- Fig. 4 C and Fig. 5 A and Formula either described in Fig. 5 B and be configured.NMOS transistor MN2 706 includes grid 720, drain electrode 722 and source electrode 724.nMOS Transistor MN2 706 is coupled between the drain electrode 714 and exterior I/O bus 726 of pMOS transistor MP 702.Bias generator 708 are coupled to the grid 720 of nMOS transistor MN2 706.Voltage discharge circuit 710 includes the nMOS transistor of coupled in series 728 and pMOS transistor 730.NMOS transistor 728 includes grid 732, drain electrode 734 and source electrode 736.Grid 732 is coupled to outer Portion's I/O bus 726.PMOS transistor 730 includes grid 738, drain electrode 740, source electrode 742 and trap pole 744.Grid 738 and source electrode 742 receive VDD.The trap pole 744 of pMOS transistor 730 and the trap pole 718 of pMOS transistor 702 are coupled to trap control circuit 704.Trap control circuit 704 can either as described in Fig. 4 A- Fig. 4 C and Fig. 5 A and Fig. 5 B formula and be configured.Voltage discharge circuit 710 are coupled to the grid 720 of bias generator 708 and nMOS transistor 706.

In an exemplary embodiment, output buffer 700 is to be configured to avoid closing Shi You electricity in chip power Stream flows into chip.Fig. 7 is please referred to, when chip power is closed, VDD is 0V.Trap control circuit 704 avoids these nMOS crystal Leakage current in pipe, and allow to end pMOS transistor 702,730.When the bus voltage Vout in exterior I/O bus 726 is When 1.8V, bus voltage Vout is applied to the source electrode 724 of nMOS transistor MN2 706.When chip power is closed, bias is produced Raw device 708 is to be ended.Therefore, the voltage on the grid 720 of nMOS transistor MN2 706 is 0V, therefore nMOS transistor 706MN2 is off.Therefore, it may not flow into output buffer from exterior I/O bus 726 electric current.When exterior I/O bus Voltage on 726 is 0V and chip power when closing, and nMOS transistor MN2 706 is to be ended.Therefore, electric current will not be from outside I/O bus 726 flows into output buffer 700.When chip is turned on power supply (VDD is 1.8V), what bias generator 708 was supplied Bias Vbias is greater than the sum of VDD and the thresholds voltage Vtn of nMOS transistor 706.This allows complete from exterior I/O bus 726 Width voltage is by nMOS transistor MN2 706 without having voltage drop.Voltage discharge circuit 710 includes the nMOS of coupled in series brilliant Body pipe 728 and pMOS transistor 730 with bias generator 708 because chip is powered down there is voltage drop when, to voltage It discharges.

The embodiment of the present invention is for having usually intellectual, referring to implementation content of the present invention disclosed herein, When can think and other embodiments.This application be intended to cover any related rule and it is made for the present invention make a variation, using and Adapt to, and include away from the present invention be but in known skill known to or usual example.Specification and example are only used for example Property explanation, protection scope of the present invention is subject to be defined depending on appended claims range.

Although however, it is not to limit the invention in conclusion the present invention has been disclosed as a preferred embodiment.This hair Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when various changes can be made With retouching.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims range.

Claims

1. a kind of output circuit, comprising:

One output switch, comprising a grid, a drain electrode and a trap pole, it is total that the drain electrode of output switch is coupled to one exterior I/O Line；

One trap control circuit, has a first transistor, a second transistor and a trap pole, which is coupled to output switch The trap pole, the greater with the trap voltage that maintains the output to switch not less than a first voltage and a second voltage；And

One gate control circuit, is coupled to the grid and the drain electrode of output switch, and is coupled to the exterior I/O bus, the grid Control circuit is operable to end output switch, to avoid electric current to flow through the output from exterior I/O bus in following situations Switch:

One operation voltage of the output circuit is not applied to output switch；And

A bus voltage from an external device (ED) occurs from the exterior I/O bus.

2. output circuit according to claim 1, wherein output switch is to be configured to one data signals of supply extremely should Exterior I/O bus；

The first voltage is that an operation voltage of the output circuit subtracts D1；

The second voltage is that the exterior I/O bus bus voltage subtracts D2；

Wherein D1 and D2 is respectively positive or zero.

3. output circuit according to claim 1, in the trap control circuit,

The first transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain, one second Source/drain is to receive operation voltage and the trap pole of the output circuit；And

The second transistor coupled in series the first transistor, the second transistor have a grid to receive the output circuit Operation voltage, one first source/drain are coupled to first source/drain of the first transistor, one second source/drain to receive this Exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole and this first and the second transistor These first source/drains, using the trap pole as the trap control circuit.

4. output circuit according to claim 1, in the trap control circuit,

The first transistor there is a grid with receive operation voltage, one first source/drain and one second source of the output circuit/ Drain electrode is coupled to the grid of the first transistor；

The second transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain is coupled to this The source/drain of the first transistor and one second source/drain are coupled to the grid of the second transistor；And

The trap pole of the trap control circuit be coupled to this first and the second transistor these first source/drains, using as this The trap pole of trap control circuit.

5. output circuit according to claim 1, in the trap control circuit,

The first transistor has a grid, one first source/drain, one second source/drain to receive the operation of the output circuit Voltage and a trap pole；And

The second transistor have a grid be coupled to the first transistor the grid and the first transistor first source/ Drain electrode, one first source/drain are coupled to the first drain electrode, one second source/drain of the first transistor to receive the exterior I/O The bus voltage of bus and a trap pole be coupled to the first transistor the trap pole, this first and the second transistor these One source/drain and this first and the second transistor these grids, using the trap pole as the trap control circuit.

6. a kind of output circuit, comprising:

One output switch, when Yu Qidong, are operable for answering a data signals to one exterior I/O bus, and the exterior I/O bus has One bus voltage, output switch include a grid, a drain electrode and a trap pole；

One trap control circuit is coupled to the trap pole of output switch with a trap pole, with the trap electricity for maintaining the output to switch The greater of pressure not less than a first voltage and a second voltage；

One input switch is coupled to the grid of output switch；

One grid control circuit, the grid and the drain electrode, the exterior I/O bus and the input for being coupled to output switch are opened It closes；

One bias generator is coupled to a grid of the input switch, to maintain a bias to be greater than an operation of the output circuit The sum of voltage and a threshold voltage of the input switch；And

One voltage discharge circuit is coupled to the grid of the bias generator, the trap control circuit and the input switch, at this When the operation voltage of output circuit reduces, discharge the bias caused by the bias generator.

7. output circuit according to claim 6, wherein the first voltage is that an operation voltage of the output circuit subtracts D1；

The second voltage is that the exterior I/O bus bus voltage subtracts D2；

Wherein D1 and D2 is respectively positive or zero.

8. output circuit according to claim 6, wherein the trap control circuit includes:

One the first transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain, one second Source/drain is to receive operation voltage and the trap pole of the output circuit；And

One second transistor, the coupled in series the first transistor, the second transistor have a grid to receive the output circuit Operation voltage, one first source/drain be coupled to first source/drain of the first transistor, one second source/drain to receive The exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole and this first and second crystal These first source/drains of pipe, using the trap pole as the trap control circuit.

9. output circuit according to claim 6, wherein the trap control circuit includes:

One the first transistor receives operation voltage, one first source/drain and one second of the output circuit with a grid Source/drain is coupled to the grid of the first transistor；

One second transistor has a grid to receive the exterior I/O bus bus voltage, one first source/drain is coupled to The source/drain of the first transistor and one second source/drain are coupled to the grid of the second transistor；And

One trap pole, be coupled to this first and the second transistor these first source/drains, using the trap as the trap control circuit Pole.

10. output circuit according to claim 6, wherein the trap control circuit includes:

One the first transistor receives the operation of the output circuit with a grid, one first source/drain, one second source/drain Voltage and a trap pole；And

One second transistor, with a grid be coupled to the first transistor the grid and the first transistor this first Source/drain, one first source/drain are coupled to first source/drain of the first transistor, one second source/drain to receive this Exterior I/O bus bus voltage and a trap pole be coupled to the external transistor the trap pole, this first and the second transistor These first source/drains and this first and the second transistor these grids, using the trap pole as the trap control circuit.

11. a kind of output circuit, comprising:

One output switch, when Yu Qidong, are operable for answering a data signals to one exterior I/O bus, and the exterior I/O bus has One bus voltage, output switch include a grid, a source/drain and a trap pole；

One input switch is coupled between source/drain and the exterior I/O bus of output switch, and operation is with from the I/O Bus and output switch disconnect；

12. output circuit according to claim 11, wherein the first voltage is that an operation voltage of the output circuit subtracts Remove D1；

The second voltage is that the exterior I/O bus bus voltage subtracts D2；

Wherein D1 and D2 is respectively positive or zero.

13. output circuit according to claim 11, wherein the trap control circuit includes:

14. output circuit according to claim 11, wherein the trap control circuit includes:

15. output circuit according to claim 11, wherein the trap control circuit includes:

One second transistor, with a grid be coupled to the first transistor the grid and the first transistor this first Source/drain, one first source/drain are coupled to first source/drain of the first transistor, one second source/drain to receive this Exterior I/O bus bus voltage and a trap pole be coupled to the first transistor the trap pole, this first and the second transistor These first source/drains and this first and the second transistor these grids, using the trap pole as the trap control circuit.