CN1921008A

CN1921008A - Memory control system and memory control circuit

Info

Publication number: CN1921008A
Application number: CN 200610121863
Authority: CN
Inventors: 桑原惠一
Original assignee: NEC Corp
Current assignee: NEC Electronics Corp; NEC Corp
Priority date: 2005-08-26
Filing date: 2006-08-25
Publication date: 2007-02-28
Anticipated expiration: 2026-08-25
Also published as: CN1921008B; JP4383495B2; JP2008299879A

Abstract

A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit for selecting a signal line of the address bus and outputting a signal of the signal line corresponding to the refresh request of the SDRAM control circuit to the SDRAM.

Description

Memory control system and memorizer control circuit

Technical field

The present invention relates to a kind of memory control system and a kind of memorizer control circuit, relate in particular to a kind of memorizer control circuit with a plurality of external memory storages.

Background technology

Have external memory storage for example the system of SDRAM (Synchronous Dynamic Random Access Memory) and flash memory or SDRAM and SRAM (static RAM) be known.Usually in this system, memory bus is shared among these external memory storages.

In the DRAM device, the SDRAM device is different from EDO (growth data output) DRAM device.In the SDRAM device, by make up each control signal for example/RAS (row address strobe) signal ,/CAS (column address strobe) signal and/WE (allowing to write) signal or the like can import various command.

A SDRAM device has a plurality of memory banks usually.In SDRAM, each memory bank is independent accessible.In this SDRAM device, when carrying out refresh operation, all memory banks all must precharge and this SDRAM device must be in idle condition.

In order to carry out refresh operation swimmingly, there is number order, that is, and so-called " auto-precharge read (or writing) orders ".For example, when when carrying out read access, after each visit, accessed memory bank is carried out precharge, and this SDRAM device becoming idle condition by " read command of auto-precharge ".Under the situation of the read access of carrying out auto-precharge, the SDRAM device is in idle condition after each visit.Therefore, when the request refresh operation, can carry out refresh operation immediately.Similar with the read access of auto-precharge, carry out write access by " write order of auto-precharge ".

But (or writing) visit of reading of auto-precharge all has precharge operation and memory bank activation manipulation in each visit.These operations (precharge operation and memory bank activation manipulation) have postponed the access speed of SDRAM device.Therefore, there is number order, that is, and so-called " auto-precharge read (or writing) do not order ".According to auto-precharge not read (or writing) visit, can improve the access speed of SDRAM device.

In the read access of auto-precharge not, after each visit, accessed memory bank does not carry out precharge.If (writing) visit of reading next time is that read (the writing) of the memory bank identical with the memory bank of reading the last time to be visited when (writing) visits visited, then execution is read (writing) visit next time and is not carried out memory bank and activate.If (writing) visit of reading next time is not that read (the writing) of the memory bank identical with the memory bank of reading the last time to be visited when (writing) visits visited, then activates memory bank, and carry out read access next time corresponding to read access next time.In this case, even (writing) visit of reading next time is not that read (the writing) of the memory bank identical with the memory bank of reading the last time to be visited when (writing) visits visited, can not carry out precharge to the memory bank of reading for the last time to be visited when (writing) visits yet.

When request does not have the SDRAM device of auto-precharge to carry out refresh operation to visiting, cause the SDRAM device not to be in idle condition owing to not carrying out the auto-precharge visit, so all memory banks must be by precharge.Can carry out the precharge of all memory banks according to one of them order.In order to carry out the precharge of all memory banks, not only by control end for example/RAS end and/the CAS end, but also bring in this order of input by the address.

In having the system of a plurality of external memory storages, the device of access external memory comprises memorizer control circuit.This memorizer control circuit control is to the visit of these external memory storages.In this system, generated request of access, to the request of access of SDRAM with to the refresh requests of SDRAM from the system LSI that comprised CPU to SRAM or flash memory.Irrelevant with the request of access from CPU to the storer, with the refresh requests of constant interval generation to SDRAM.As mentioned above, be used for all memory banks are carried out precharge order because this refresh requests has comprised, so this refresh requests has comprised the signal that is input to certain address end by address bus.Therefore,, then at first finish visit, refresh SDRAM then SRAM if the request of access of SRAM is conflicted with the refresh requests to SDRAM.And, during the refresh cycle of SDRAM, the request of access of another external memory storage is lain on the table.

But, have been found that and follow the method that after the visit of finishing SRAM, refreshes SDRAM, during the refresh cycle, can not utilize address bus and data bus (bus hereinafter referred to as).Therefore, it has reduced the service efficiency of bus and the transfer efficiency of system.

Correlation technique is disclosed in the open text of Japanese Unexamined Patent Application 11-7763 number.In the open text of Japanese Unexamined Patent Application 11-7763 number, during being conducted interviews, the device except DRAM carries out refresh operation.But the open text of Japanese Unexamined Patent Application only discloses traditional DRAM technology for 11-7763 number, and does not disclose the refresh operation of SDRAM.

Summary of the invention

According to an aspect of the present invention, provide a kind of memory control system, it comprises first memory, is used for by address bus and data bus visit CPU; SDRAM is used for by address bus and data bus visit CPU; The SDRAM control circuit is used for refresh requests is outputed to SDRAM; And selecting arrangement, be used for selecting the signal wire of address bus, and will output to SDRAM with the signal of the corresponding signal wire of refresh requests of described SDRAM control circuit.

According to another aspect of the present invention, a kind of memorizer control circuit is provided, its be used for by first memory and SDRAM shared bus visit first memory and SDRAM, this memorizer control circuit comprises: memorizer control circuit is used to produce the control signal of first memory; The SDRAM control circuit is used to produce the control signal of SDRAM; And selecting arrangement, be used for selecting the signal wire of this bus, and selected signal with the corresponding signal wire of being exported by described SDRAM control circuit of refresh requests is outputed to SDRAM.

The present invention can improve the service efficiency of bus.

Description of drawings

Can know according to following description in conjunction with the accompanying drawings and understand above and other objects of the present invention, advantage and feature, wherein

Fig. 1 shows the synoptic diagram according to the structure of the memory control system of the embodiment of the invention;

Fig. 2 A shows synoptic diagram according to the operation of the memory control system of the embodiment of the invention to 2C;

Embodiment

With reference to schematic specific embodiment the present invention is described at this.One skilled in the art will recognize that and use instruction of the present invention can realize many optional embodiment, and the present invention is not limited to be used for each embodiment of task of explanation institute example.

Below, be described in detail with reference to the attached drawings memory control system according to the embodiment of the invention.Fig. 1 shows the synoptic diagram of the memory control system of this embodiment.The memory control system of present embodiment comprise system LSI 10, external memory storage 20 (flash memory/SRAM20) hereinafter referred to as, it can be for example SRAM or flash memory, and external memory storage 30 (SDRAM30 hereinafter referred to as), this external memory storage is SDRAM.This system LSI 10 by by each external memory storage shared memory bus be connected to

external memory storage

20 and 30.

As shown in Figure 1, system LSI 10 comprises CPU11, arbiter 12, flash memory/SRAM control circuit 13, SDRAM control circuit 14,

selector switch

15,16 and 17.In the memory control system of present embodiment, arbiter 12, flash memory/SRAM control circuit 13, SDRAM control circuit 14,

selector switch

15,16 and 17 are corresponding to memorizer control circuit.

CPU11 is according to the externally flash memory device or the program stored work of the interior institute of other memory storages of storer 20.CPU11 is from flash memory/SRAM20 and SRAM30 read data, or data are write flash memory/SRAM20 and SRAM30.Arbiter 12 is arbiters, if request of access for flash memory/SRAM20, then this arbiter sends the request of access from CPU11.If request of access is for SDRAM30, then arbiter 12 sends to SDRAM control circuit 14 with request of access.

Flash memory/SRAM control circuit 13 responds from the request of access of CPU11 and generates address signal, data-signal and the control signal etc. that are used for flash memory or SRAM.Then, flash memory/SRAM control circuit 13 outputs to address bus AB1 with address signal, and data-signal is outputed to data bus DB1, and control signal is outputed to control signal wire C1.

SDRAM control circuit 14 responds from the request of access of CPU11 and generates address signal, data-signal and the control signal etc. that are used for SDRAM.Then, SDRAM control circuit 14 outputs to address bus AB2 with address signal, and data-signal is outputed to data bus DB2, and control signal is outputed to control signal wire C2.SDRAM control circuit 14 inside comprise refresh counter 18.For example, this refresh counter 18 generates the refresh requests that is used for SDRAM30 according to the count value of reference clock with constant interval (for example, per 15 microseconds).

Address bus AB1 and AB2 from flash memory/SRAM control circuit 13 and SDRAM control circuit 14 are connected to selector switch 15.Selector switch 15 selects one of them address bus to be connected to flash memory/SRAM20 or SDRAM30.Data bus DB1 and DB2 from flash memory/SRAM control circuit 13 and SDRAM control circuit 14 are connected to selector switch 16.Selector switch 16 selects one of them address bus to be connected to flash memory/SRAM20 or SDRAM30.With

selector switch

15 and 16 and the bus that couples together of flash memory/SRAM20 or SDRAM30 by shared as external memory bus.

Address bus AB2 from SDRAM control circuit 14 is connected to selector switch 17.Signal wire among the address bus AB2 that 17 pairs of selector switchs are made up of a plurality of signal wire is selected, to be connected to SDRAM30.Control signal wire C1 from flash memory/SRAM control circuit 13 is connected to flash memory/SRAM20, and is connected to SDRAM30 from the control signal wire C2 of SDRAM control circuit 14.

The refresh operation of following brief explanation SDRAM30.SDRAM30 can with comprised/RAS (row address strobe) signal ,/CAS (column address strobe) signal ,/WE (allowing to write) signal and/CS (sheet choosing) control signal of signal and the order that input signal makes up be input on appointment pin among the SDRAM etc.If imported this order, then SDRAM30 is according to this command-execution operation.

The SDRAM30 of present embodiment is the SDRAM that can carry out burst access.Burst access is the characteristic visit of SDRAM.In burst access, be to same word line if selected word line and next visit by the order that only receives column address and be used for read/write, then exist a kind of visit to shorten the required time of row address that obtains.In SDRAM control circuit 14, generate the order of carrying out aforesaid operations.In this SDRAM,, data line is not carried out precharge, and the current potential of data line is based on and the corresponding data of selected word line for each read/write operation.Therefore, in order to refresh the SDRAM that can carry out burst access, all memory banks of SDRAM must be by precharge once.In the SDRAM30 of present embodiment, all memory banks of SDRAM30 are carried out precharge by input command when refreshing.By the signal and the control signal of the specific pin that address bus comprised, all memory banks are carried out precharge order to the SDRAM30 of present embodiment input.And inner self-refresh order that refreshes and the control signal that is used for SDRAM30 carried out of SDRAM30 imported in combination.

Therefore, even SDRAM30 is not connected with any data bus or address bus, SDRAM30 also can be refreshed.Selector switch 17 in the present embodiment is selected for the necessary signal wire of input refresh command (all memory bank precharge), in order to be connected to the appointment pin of SDRAM.

Usually, there are various types of SDRAM.Therefore, be used to import signal wire (specific pin) that all memory banks are carried out precharge order according to the type of SDRAM and different.In the present embodiment, the selector switch 17 of system LSI can be connected to all kinds of SDRAM.

As mentioned above, to be used for the precharge order of all memory banks PALL is input to the SDRAM30 of present embodiment, so that when refresh operation with SDRAM in the voltage level of all data lines adjust on a certain voltage level, and the order SELF that will be used to start self refresh operation is input to the SDRAM30 of present embodiment.Import these two orders and can carry out refresh operation.The signal wire that optionally address bus AB2 is connected to SDRAM is the signal wire that is used to import these two orders.

Below describe the operation of the memory control system of structure in the above described manner in detail.

Fig. 2 A to 2C show the request of access from CPU11 to the external memory storage according to present embodiment, the synoptic diagram of the operation of the refresh requests that generated by refresh counter 18 and memory control system.

At first,, suppose that the request of access from CPU11 is for external memory storage 20, and do not generate refresh requests (referring to Fig. 2 A to 2B) this moment at the time t0 place of Fig. 2 A to 2C.Arbiter 12 is according to the request of access from CPU11, and data that will be obtained from CPU11 and address output to flash memory/SRAM control circuit 13.Flash memory/SRAM control circuit 13 is according to request of access calculated address signal, data-signal and control signal etc. from CPU11.Then, flash memory/SRAM control circuit 13 outputs to address bus AB1 with address signal, and data-signal is outputed to data bus DB1 and control signal is outputed to control signal wire

C1.Selector switch

15 and 16 determines by reference example such as arbiter 12 this request of access will to which storer, so that make one's options.In the present embodiment, for flash memory/SRAM20, so

selector switch

15 and 16 selects address bus AB1 and data bus DB1 to be connected to flash memory/SRAM20 in time t0 place request of access.Therefore, the address and the data-signal that are generated in flash memory/SRAM control circuit 13 are imported into flash memory/SRAM20, and this makes flash memory/SRAM20 successfully set up the visit with CPU11.

Then, at the time t1 place of Fig. 2 A in the 2C, generate request of access to external memory storage from CPU11.At time t2 place, refresh counter 18 generates refresh requests based on its count value.Below describe these operations in detail.At time t1 place, the same with time t0,

selector switch

15 and 16 optionally is connected to flash memory/SRAM20 with AB1 and DB1, thereby has set up the visit between CPU11 and the flash memory/SRAM20.At time t2 place, if generated refresh requests (referring to Fig. 2 B) to SDRAM30 in CPU11 visit flash memory/SRAM20, then SDRAM control circuit 14 generates and refreshes the required order of SDRAM30.Particularly, SDRAM control circuit 14 generates mentioned order PALL and SELF successively, so that these orders are outputed to SDRAM30.At this moment, selector switch 17 optionally will be connected to SDRAM30 corresponding to the signal wire of the pin of importing refresh command.Therefore, being input to SDRAM30 with having made up the order that control signal is used to carry out refresh operation, described control signal comprises/RAS ,/CAS ,/WE ,/CS signal and to the input signal of specifying pin.

In the present embodiment, for example, if generate refresh requests at the t2 place, then SDRAM control circuit 14 outputs to control signal wire C2 with control signal, wherein said control signal has/CS=L ,/RAS=L ,/CAS=H and/combination of WE=L.For address bus corresponding to the appointment pin (AP hereinafter referred to as) of input command, SDRAM control circuit 14 output AP=H and export above-mentioned PALL order.As a result, by control signal wire C2 with by selector switch 17 selected signal wires, the PALL order is imported into SDRAM30 (external memory storage), so that carry out the precharge operation of all memory banks.Then, SDRAM control circuit 14 generates the control signal corresponding to order SELF successively, this control signal made up/CS=L ,/RAS=L ,/CAS=L and/WE=H.Being used for indicating the order SELF that starts self-refresh, do not need to specify AP corresponding to the appointment pin of input command, this is because it does not need to be adjusted especially.In response to order SELF, SDRAM starts self refresh operation.Input command PALL and SELF can make SDRAM30 begin to carry out refresh operation.During the refresh operation based on the refresh requests at t2 place,

selector switch

15 and 16 is based on select output bus from flash memory/SRAM control circuit 13AB 1 and DB1 to be connected to flash memory/SRAM20 from the request of access of CPU11.Therefore, can between flash memory/SRAM20 and CPU11, successfully carry out visit.

Then, at the time t3 place of Fig. 2 A, suppose request of access from CPU11 for SDRAM 30, and do not generate any refresh requests (participating in Fig. 2 A and 2B) this moment to 2C.Arbiter 12 will output to SDRAM control circuit 14 from data and the address that CPU obtains based on the request of access from CPU11.SDRAM control circuit 14 is according to request of access calculated address signal, data-signal and control signal etc. from CPU11.Then, SDRAM control circuit 14 outputs to address bus AB2 with address signal, and data-signal is outputed to data bus DB2 and control signal is outputed to control signal wire

C2.Selector switch

15 and 16 determines by reference example such as arbiter 12 which storer is this request of access be at, so that make one's options.In the present embodiment, request of access is for SDRAM, and therefore,

selector switch

15 and 16 selects address bus AB2 and data bus DB2 to be connected to external memory storage 30.Therefore, the address and the data-signal that are generated in SDRAM control circuit 14 are imported into external memory storage 30, and this makes external memory storage 30 successfully set up the visit with CPU.At this moment, connected the address bus that is used to import mentioned order PALL, in order to the signal of I/O SDRAM in normal running by selector switch 17.

At the time t4 place of Fig. 2 A to 2C, if generated refresh requests by refresh counter 18 when CPU11 conducts interviews to SDRAM30 according to the request of access from CPU11, then SDRAM control circuit 14 can not generate above-mentioned refresh command.This can realize by ignore this refresh requests when 12 pairs of SDRAM control circuits 14 of arbiter are selected.This has prevented to interrupt refresh operation during just at access sdram 30 at CPU11.Optionally, for example, when SDRAM30 was in Access status, this refresh requests can be used as a mark and be retained in the SDRAM control circuit 14, so that start this refresh requests when arbiter 12 is no longer selected the SDRAM control circuit.Fig. 2 A shows the synoptic diagram of this state to 2C.

As top detailed description, according to present embodiment, even when CPU is visiting the external memory storage 20 of flash memory/SRAM for example, also can refresh SDRAM30.Therefore, even under the situation of two types external memory storage shared address bus and data bus, also can use these buses effectively.And therefore the address bus that optionally is connected to SDRAM only need or not another to be used for the address bus of SDRAM corresponding to the pin of input refresh command.

Obviously the invention is not restricted to the foregoing description, and under the situation that does not break away from protection scope of the present invention and spirit, can modify and change.

Claims

1. memory control system comprises:

First memory is used for by address bus and data bus visit CPU;

SDRAM is used for visiting this CPU by address bus and data bus;

The SDRAM control circuit is used for refresh requests is outputed to this SDRAM; And

Selecting arrangement is used for the signal wire of address bus is selected, and will output to SDRAM with the signal of the corresponding described signal wire of described refresh requests of this SDRAM control circuit.

2. memory control system as claimed in claim 1, wherein said order corresponding to refresh requests are the precharge command to all memory banks of SDRAM.

3. memory control system as claimed in claim 1 is wherein according to the data of described address bus with determined the address of described SDRAM by the signal that described selecting arrangement is exported.

4. memory control system as claimed in claim 2 is wherein according to the data of described address bus with determined the address of described SDRAM by the signal that described selecting arrangement is exported.

5. one kind is used for comprising by visited the memorizer control circuit of described first memory and described SDRAM by first memory and the shared bus of SDRAM:

Memorizer control circuit is used to produce the control signal of described first memory;

The SDRAM control circuit is used to produce the control signal of described SDRAM; With

Selecting arrangement is used for the signal wire of this bus is selected, and will output to this SDRAM with the signal of the corresponding selected signal wire of being exported by described SDRAM control circuit of refresh requests.

6. memorizer control circuit as claimed in claim 5 also comprises:

Output terminal is used for the signal with the corresponding selected signal wire of described refresh requests is outputed to described SDRAM.

7. memorizer control circuit as claimed in claim 5, wherein said refresh requests comprises the precharge command to all memory banks of SDRAM.

8. memorizer control circuit as claimed in claim 6, wherein said refresh requests comprises the precharge command to all memory banks of SDRAM.