JP2003091453A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller capable of preventing deterioration of performance by executing processing prior to self-refresh transition and during no access in a fixed period. SOLUTION: As for DDR-SDRAM 1, 2, and 3, a DQS being a signal necessary for data control, data bus MDQ, and signal necessary for access control are connected to a memory control part 10. With respect to a memory system for executing the reading/writing of data by using the DDR-SDRAM as storage means, PDL whose delay is adjustable according to access from a CPU is mounted on this memory controller so that the DQS being a data strobe signal can be delayed. With respect to the memory system, a prescribed specific value is written in a specific address, and the values read in the same address are compared while the value of the PDL is changed. Thus, a readable region can be recognized. Thus, read data can be latched in a valid region by setting the optimal delay time in the PDL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, and more particularly to a memory control device configured as a semiconductor integrated circuit for controlling a memory.

[0002]

2. Description of the Related Art Conventionally, memory control devices are generally D
It is configured using a DR-SDRAM. This DDR-S
At the time of reading, the DRAM takes in the read data by the data latch signal DQS output in synchronization with CLK.
DQS must be delayed in the memory controller so that it can be latched in the valid area of the read data. It is a known technique to register the delay time in the CPU and use PDL (Programmable Delay) for delaying DQS based on the value.

Further, when the environment such as temperature and humidity changes with time, the load capacity of data and DQS fluctuates, and at the delay time preset in PDL (Programmable Deley), the data of delayed DQS is changed. It may be out of the valid area and the correct value may not be latched. In addition, when the main body is not operated in order to save energy, it is now widely and commonly performed to shift the memory system to the self-refresh mode.

Prior invention example 1 similar in technical field to the present invention
As an example, there is a "memory subsystem" in Japanese Patent Laid-Open No. 11-25029. The first invention of the prior application aims at delaying the clock of the data input circuit and smoothly fetching the data. Further, a technique is disclosed in which DQS is delayed in order to smoothly capture data and the delay can be made variable by register setting.

[0005]

However, in the above-mentioned prior art, the optimum delay time is set by estimating the load capacity of the DQS and setting a value according to the load capacity. The load capacity fluctuates accordingly. For this reason, the preset delay time deviates from the effective area of the delayed DQS data, and a correct value cannot be latched.

Further, when the environment such as temperature and humidity changes with time, the load capacity of data and DQS fluctuates, and at the delay time preset in PDL (Programmable Deley), the data of delayed DQS is changed. It may be out of the effective area and the correct value may not be latched.

It is an object of the present invention to provide a memory control device which is implemented before a self-refresh transition and when there is no access for a certain period of time to avoid performance degradation.

[0008]

In order to achieve the above object, the invention according to claim 1 is a memory control device in a memory system for reading and writing data from and to a DDR-SDRAM, which is a data strobe signal. DQS
In order to delay the delay, a PDL (Programmable Display) with adjustable delay by access from the CPU is installed,
It is possible to read by writing a predetermined value to a specific address in the memory system, reading to the above address while changing the value of PDL, and comparing the predetermined value written at the address with the read value. It is characterized by recognizing the range.

According to a second aspect of the invention, in the first aspect of the invention, the readable range is recognized before the self-refreshing of the memory system.

A third aspect of the invention is characterized in that, in the first aspect of the invention, when the memory is not accessed for a predetermined time, the readable range is recognized.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a memory control device according to the present invention will be described in detail with reference to the accompanying drawings.
Referring to FIGS. 1 to 4, there is shown one embodiment of the memory control device of the present invention. Hereinafter, specific description will be given based on embodiments of the present invention.

FIG. 1 is a connection diagram of a memory control unit and a memory system according to the present invention. As shown in FIG. 1, DDR-
The SDRAMs 1, 2, and 3 are connected to the memory control unit 10 in order to exchange DQS, which is a signal required for data control, and signals required for the data bus MDQ and access control.

FIG. 2 shows the configuration of an equivalent circuit of PDL and a data latch circuit. Since the DDR-SDRAM emits DQS and DQM in synchronization with the clock, the DQS is delayed within the readable range of the DQM in the memory control unit 10 and the DQ falls or rises.
Latch M. The delay time of DQS can be selected by register setting for PDL.

FIG. 3 is a control flowchart showing a first operation example of the present invention. First, this control is started when shifting to the energy saving mode (step S1). DDR-
The specific data B is written to the specific address A of the SDRAM (step S2).

Next, the value of the address A is read at 10 degree intervals and compared with the data B to recognize the readable range in 10 degree units (step S3).

At the vicinity of Min or Max in the readable range recognized in step S3, the value of address A is read at 5 degree intervals and compared with data B, and 5de
Recognize the readable range in gree units (step S
4).

In the vicinity of Min or Max in the readable range recognized in step S4, the value of address A is read at 1 degree intervals and compared with data B, and 1de
Recognize the readable range in gree units (step S
5).

After setting the intermediate value of the data valid area (readable range) recognized in step S5 to PDL (step S6), self-refreshing is performed on the memory system (step S7).

FIG. 4 is a control flowchart showing a second operation example of the present invention. First, if memory access is not performed from the memory control device for a certain period, the CPU is notified of this by an interrupt or the like (step S11).
This flowchart is started when there is no memory access for a certain period.

The specific data B is written to the specific address A of DDR-SDRA (step S12).

Next, the value of the address A is read at 10 degree intervals and compared with the data B to recognize the readable range in 10 degree units (step S13).

The value of address A is read at an interval of 5 degrees with respect to the vicinity of Min or Max in the readable range recognized in step S13, and the value is compared with data B.
The readable range in units of degree is recognized (step S14).

In the vicinity of Min or Max in the readable range recognized in step S14, the value of address A is read at 1 degree intervals and compared with data B.
The readable range in units of degree is recognized (step S15).

The intermediate value of the data valid area (readable range) recognized in step S15 is set in PDL (step S16).

In the first operation example of the present invention, even if the data or the load capacity of the DQS changes due to changes in the environment such as the effect temperature and humidity over time, the optimum delay time is changed every energy saving mode transition. Recognize. This allows
If the optimum delay time is set to PDL, read data can be latched in the effective area. Further, since the load for recognizing the optimum delay time is applied before shifting to the energy saving mode, there is no performance deterioration during operation.

Also, in the second operation example of the present invention, it is most suitable when there is no access for a certain period even if the environment such as the effect temperature and humidity changes with time and the load capacity of data and DQS changes. Recognize the delay time. As a result, if the optimum delay time is set to PDL (Programmable Deley),
Read data can be latched in the valid area.
Also, since the load for recognizing the optimum delay time is applied when there is no memory access, there is no performance degradation during operation.

[0027]

As is apparent from the above description, according to the first aspect of the present invention, a predetermined value is written to a specific address in the memory system, the PDL value is changed and read to the same address. Compare each value.
By this, the readable range is recognized.

The optimum delay time to be set in the PDL can be recognized depending on whether or not the correct value can be read by performing read access to the previously written address while changing the value of the PDL. Therefore, if the optimum delay time is set to PDL, the read data can be latched in the effective area.

According to the invention of claim 2, in the invention of claim 1, the readable range is recognized before the transition to self-refresh, and the optimum delay time is recognized each time. As a result, the optimum delay time is set to PDL (Progra
(mmable Deley), read data can be latched in the effective area, and since recognition processing is performed before the transition to self-refresh, the main unit is not operating, preventing performance degradation during operation. be able to.

According to the invention of claim 3, in the invention of claim 1, the readable range is recognized when there is no memory access for a certain period, and the optimum delay time is recognized each time. As a result, the optimum delay time is set to PDL.
If set to, read data can be latched in the effective area, and since recognition processing is executed when there is no memory access, the main unit is not operating, preventing performance degradation during operation. be able to.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a memory control unit and a DDR according to an embodiment of the present invention.
FIG. 6 is a configuration diagram showing a connection state with an SDRAM.

FIG. 2 is a configuration diagram of a PDL equivalent circuit and a data latch circuit.

FIG. 3 is a control flowchart showing a first operation example of the present invention.

FIG. 4 is a control flowchart showing a second operation example of the present invention.

[Explanation of symbols]

1, 2, 3 DDR-SDRAM 10 Memory controller

Claims (3)

[Claims] 1. A memory controller in a memory system for reading / writing data from / to DDR-SDRAM, wherein DQS, which is a data strobe signal, is delayed.
PDL with adjustable delay by access from CPU
(Programmable Display) is mounted, a predetermined value is written to a specific address for the memory system, the PDL value is changed and read to the address, and the predetermined value written to the address is read. A memory control device characterized by recognizing a readable range by comparing with a value. 2. The memory control device according to claim 1, wherein recognition of the readable range is executed before transition to self-refresh of the memory system. 3. The memory control device according to claim 1, wherein when the memory is not accessed for a predetermined time, the readable range is recognized.