CN1917576A - Fractional order differential filter for digital image - Google Patents

Abstract

The apparatus is designed for use in enhancing the complex texture details of digital image in real-time. It comprises a memory module, a phase-locking/shift circuit, a fractional order differential mask convolution circuit and a maximum value comparator. In the fractional order differential mask convolution circuit, the operation rules of 8 dedicated algorithm circuits use fractional order differential mask convolution scheme to achieve the spatial filter of digital image fractional order differential coefficient. The invention can be used in HDTV, biomedicine image, bank paper, satellite remote sensing, and creature characteristic graph.

Description

The fractional order differential filter of digital picture

Affiliated field

The fractional order differential filter of digital picture proposed by the invention is a kind of signal processing circuit device of real-time enhancing digital picture complex texture minutia.The order of the fractional order differential that the present invention relates to is not traditional integer rank, but non-integral order, engineering is generally got mark or reasonable decimal in using.See Fig. 1, the fractional order differential filter of this digital picture is to adopt digital video frequency flow line storage group 18, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20 to constitute with cascade system with maximum comparator 21.The operation rule of 8 specific algorithm unit circuit 1～8 in its fractional order differential mask convolution circuit 20 is airspace filters that the scheme of employing fractional order differential mask convolution realizes the digital image fractional order differential.The fractional order differential filter circuit structure of digital picture proposed by the invention is simple, operation rule is simple and clear, the grain details reinforced effects is good, the real-time height is specially adapted to the complex texture minutia of HD digital TV, biomedical image, bank money, satellite remote sensing images and biometric image etc. is strengthened such application scenario in real time.The invention belongs to applied mathematics, Digital Image Processing and digital circuit cross discipline

Technical field.

Background technology

In recent years, along with HD digital TV of future generation improving constantly to image definition and real-time requirement; Along with biomedical image (for example, cell image, X-ray sheet, breast molybdenum target sheet, CT image, MR image, PET image, ultrasonoscopy etc.) is handled improving constantly of definition and real-time requirement to later image; Along with bank money intelligent identifying system improving constantly to the requirement of bill complex texture minutia pretreatment quality; Along with satellite remote sensing images to the enhancing degree of its complicated geographical grain details feature and improving constantly to the little target identification Capability Requirement that has only several pixels; Along with biological characteristic intelligent identifying systems such as fingerprint, iris, palmmprint to improving constantly that complex biological textural characteristics pretreatment quality requires, these all an urgent demand the scheme that a kind of structure strengthens the filter of digital picture complex texture minutia is efficiently and in real time proposed.

At present, from the relational angle between the image pixel, image texture minutia analytical plan is divided into four classes: the 1st class: the statistical analysis scheme.This scheme mainly is based on the distribution and the correlation of the gray value of image pixel, selects different statistics that the statistical nature that reflects these relations in the texture image is extracted.Those do not have the structural images of obvious systematicness in the only main suitable image of this scheme.The statistical analysis scheme has the co-occurrence matrix scheme, and (gray level co-occurrence matrix is GLCM) with long distance of swimming scheme (run lengthmatrix, RLM) two kinds; The 2nd class: structural analysis scheme.This scheme is at first regarded texture as by many texture primitives and is formed according to certain location rule, divides two step process then: the first step: extract texture primitive; Second step: inference texture primitive position rule, therefrom obtain architectural feature.This scheme is mainly handled texture image with mathematical morphology, only is suitable for processing rule and periodic texture; The 3rd class: based on model scheme.This scheme thinks that there are certain correlation in a pixel and its neighborhood territory pixel.This scheme characterizes texture image with model coefficient, thereby its key is at first will choose optimal model to the structure analysis of texture image, secondly is how to estimate these model coefficients.This scheme is divided into four kinds of autoregression models, markov random file model, Gibbs random field models, fractal model usually.It is big that this class scheme exists amount of calculation, and natural texture is difficult to shortcoming with single model tormulation; The 4th class: frequency spectrum scheme.This scheme can only be finished the frequency decomposition to image, thereby the information that obtains is not very abundant.This scheme has Fourier transform method, power spectrum method, Gabor converter technique, Wavelet Transform etc.Wavelet Transform is divided into gold turriform Wavelet Transform and tree-like Wavelet Transform (wavelet packet method) substantially.Because the complexity of texture image has obtained certain effect with the integrated use of various traditional texture analytical technology in recent years.In fact this integrated use is equivalent to the information fusion of multiple traditional texture analytical plan result, but this has just greatly consumed computational resource, has reduced treatment effeciency, can not satisfy the real-time requirement of calculating.

Nearly three over 100 years, and fractional calculus had become an important branch already in the mathematical analysis field, but it is also rarely known by the people for most of engineering circle scholars.Among how fractional calculus being applied to the modern signal analysis and handling, among the processing of picture signal, at home and abroad all be a new branch of science branch that is worth research particularly.In digital picture, the gray value in the neighborhood between pixel and the pixel has very strong correlation, and this correlation normally shows with the grain details feature of complexity.The complex texture minutia that can utilize fractional order differential to handle to strengthen in the digital picture? the present patent application people is to fractional calculus should be used as deeply and systematic research in the modern signal analysis and in handling, it studies show that: the various fractional order differentials definition of signal all should be satisfied following 3 character: I, is maximum by unusual saltus step place of correspondence gradually go to zero (outside the Riemann-Liouville definite division) in the fractional order differential value of flat sections (zone that the gradation of image value is constant).And the arbitrary integer rank differential of flat sections must be zero.This is a fractional order differential with respect to one of remarkable difference of integer rank differential; II, the fractional order differential value non-zero at the starting point place on gray scale ladder or slope has played the effect of strengthening high-frequency information; III is along the fractional order differential value non-zero on slope, also non-constant.And be constant along the integer rank differential value on slope.Therefore, to one-dimensional signal carry out fractional order differential handle can non-linear reinforcement signal intermediate frequency and high frequency composition, again can be to a certain extent the low frequency of non-linear stick signal and direct current composition as best one can.The classical receptive field model of Rodieck Gaussian difference is even symmetry center one a peripheral antagonism formula.The Sobel operator based on the single order differential of classics in the conventional digital image processing, and based on the Laplace operator of second-order differential, and even, in fact all be that the Rodieck receptive field model is carried out bionical realization on mathematics based on the sombrero operator of wavelet transformation.One-dimensional signal is done fractional order differential handle as can be known, different with traditional classical integer rank differential, the fractional order differential value of direct current and low frequency signal is generally non-vanishing.In like manner, the two dimensional image signal is carried out fractional order differential can keep low frequency contour feature in the image smoothing zone as far as possible, the relatively large high frequency edge feature of gray value transition amplitude in simultaneously again can non-linear enhancing image, and the relative little high frequency grain details feature of gray value transition amplitude in can also non-linear enhancing image with frequency change.The antagonistic properties of image fractional order differential meets the side inhibition principle of biological vision, is asymmetric Rodieck receptive field.

Summary of the invention

The objective of the invention is to construct a kind of digital picture filter, it can disposablely finish, real-time, easy, can try one's best low frequency contour feature in the encumbrance word image smooth region effectively, the relatively large high frequency edge feature of gray value transition amplitude in simultaneously again can non-linear enhancing digital picture, and the relative little high frequency grain details feature of gray value transition amplitude in can also non-linear enhancing digital picture with frequency change.Applicant of the present invention furtherd investigate with fractional order differential strengthen the digital image texture minutia basic principle and and operation rule, on this basis at this core content of signal processing circuit device of how to construct the digital image fractional order differential filter, input characteristics according to the character of digital image fractional order differential and Digital Image Processing, digital circuit, serial digital video code stream, new departure of a kind of signal processing circuit device of real-time enhancing digital picture complex texture minutia has been proposed, i.e. the fractional order differential filter of digital picture.See Fig. 1, the fractional order differential filter of this digital picture is to adopt digital video frequency flow line storage group 18, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20 to constitute with cascade system with maximum comparator 21.The operation rule of 8 specific algorithm unit circuit 1～8 in its fractional order differential mask convolution circuit 20 is airspace filters that the scheme of employing fractional order differential mask convolution realizes the digital image fractional order differential.

Before specifying content of the present invention, be necessary used symbol connotation of this specification and span thereof are carried out 3 explanations: the 1st point, continue to use and be accustomed to using x (different with the transverse axis coordinate in the traditional images processing with the general mathematical notation of Euclidean space with the longitudinal axis of y coordinate difference presentation video pixel, its custom is represented transverse axis and ordinate of orthogonal axes respectively with x and y coordinate), with S (x, y) denotation coordination (x, y) gray value of the pixel on or rgb value; When x and y get the continuous analogue value, S (x, y) expression analog image; When x and y got discrete digital value, (it was a picture element matrix to S for x, y) expression digital picture (x and y represent row-coordinate and row coordinate respectively); The 2nd point has clear and definite axial symmetry center in order to make fractional order differential mask (it is the square formation of a n * n), and the size number n of fractional order differential mask is an odd number; The minimum value of n is 3, the maximum occurrences of n less than the size number of the digital picture of pending fractional order differential (if (x y) is the picture element matrix of L * H to the digital picture S of pending fractional order differential, and when L=H, its size number is L; When L ≠ H, its size number is the minimum value among L and the H); The 3rd point, in practical engineering application, digital picture S (the x of pending processing, y) (it is the picture element matrix of a L * H, L represents S (x, y) line number, H represents S (x, y) columns, promptly every row has H pixel, and x gets the integer between 0～(L-1), y gets the integer between 0～(H-1)) the gray value of the capable pixel of L or rgb value generally be not parallel input (input simultaneously of each row of the gray value of the capable pixel of L or rgb value), but serial input (gray value of the capable pixel of L or rgb value one-row pixels connect the one-row pixels input, and the gray value or the rgb value of H pixel of every row input form the serial digital video code stream) image processing apparatus; According to the input characteristics of serial digital video code stream, use S _x(k) (subscript x represents each frame of digital image S (x to the pixel in the expression serial digital video code stream, y) be to form the serial digital video code stream in the mode that one-row pixels connects one-row pixels input, (x is y) from its nethermost delegation (L is capable) beginning input from bottom to up, k remarked pixel S for S _x(k) the pixel sequence number in the serial digital video code stream, k begins counting from L * H-1, subtracts one by pixel input k value, until being zero); If S _x(k) coordinate before the corresponding serial input (x, y) the pixel S on (x, y), S then _x(coordinate before the corresponding serial input of k ± mH ± b) (the pixel S on the x ± m, y ± b) (x ± m, y ± b).

See Fig. 1, the fractional order differential filter of digital picture of the present invention is to be formed with 21 cascades of maximum comparator by digital video frequency flow line storage group 18, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20; Serial digital video code stream S _x(k) after port one 7 input, be divided into three the tunnel: after the first via is handled through line storage group 18, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20 in proper order, respectively at port 9～16 output pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 directions of fractional order differential mask lower-right diagonal position line, after handling through maximum comparator 21, the maximum in port 22 these 8 approximations of output is as pixel S again _xThe v rank fractional order differential value approximation S of (k+ (n-1) (H+1)) _x ^(v)(k+ (n-1) (H+1)); The second the tunnel triggers sequential control circuit produces corresponding timing control signal; Third Road with the output feed-in of line storage group 18 phase-locked/shift circuit group 19 generates the pel array of (2n-1) * (2n-1).Wherein, the order v of the fractional order differential mask convolution circuit 20 in the fractional order differential filter of this digital picture can get mark or reasonable fractional value (because the computational length of digital circuit is limited between 0～1, when v is unreasonable decimal, can approximate approximate reasonable decimal), different requirements according to engineering precision, order v is divided into three types floating data, the calculated data type of its algorithm unit circuit 1～8 also is divided into corresponding three types: the 1st type: single (accounts for 4 byte of memorys, computational length 32bit, 6～7 of significant digits, evaluation scope 10 ^-37～10 ³⁸); The 2nd type: double (accounts for 8 byte of memorys, computational length 64bit, 15～16 of significant digits, evaluation scope 10 ^-307～10 ³⁰⁸); The 3rd type: long double (accounts for 16 byte of memorys, computational length 128bit, 18～19 of significant digits, evaluation scope 10 ^-4931～10 ⁴⁹³²).The fractional order differential filter of the digital picture that the present invention proposes, be to construct like this: it includes following forming circuit parts:

See Fig. 1, line storage group 18 is made of sequential control circuit, read/write address generator and two-port RAM group; Sequential control circuit produces the timing control signal of control corresponding read/write address generator, two-port RAM group, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20 and 21 operations of maximum comparator under the triggering of the row of input digit video flowing, a useful signal; The read/write address generator produces the read/write address of two-port RAM under the effect of timing control signal, and is responsible for handling read/write address initialization and rotating problem; Line storage group 18 is according to the input characteristics of serial digital video code stream, utilize current input pixel, different in kind according to the digital picture of handling, line storage group 18 is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, this line storage group 18 adopts 2n-2 line storage to finish obtaining of the capable vedio data of 2n-1; The 2nd kind of structure: when handling digital color image, line storage group 18 and line storage group electronic circuit parallel processing identical by 3 constitutes; Wherein the circuit structure and the parameter of each line storage group electronic circuit and above-mentioned line storage group 18 when handling gray level image are identical; R, G, a B3 component value of the parallel respectively storage digital color image of these 3 line storage group electronic circuits; Line storage group 18 adopts 6n-6 line storage altogether, and wherein each line storage group electronic circuit adopts 2n-2 line storage to finish obtaining of 2n-1 line number word video color image respective component value.

See Fig. 1, phase-locked/shift circuit group 19 is according to the input characteristics of serial digital video code stream, utilize current input pixel, different in kind according to the digital picture of handling, phase-locked/shift circuit group 19 is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, this phase-locked/shift circuit group 19 adopts 3n altogether ²-3n d type flip flop produces required (2n-1) * (2n-1) pel array of calculating gray level image fractional order differential by gray level image being carried out a time-delay; (2n-1) * (2n-1) the 1st of pel array the row adopts 2n-2 d type flip flop, and the 2nd row adopts 2n-3 d type flip flop, all is to subtract n d type flip flop of the capable employing of one, the n-1 line by line until the capable every row of n-1 adopts the number of d type flip flop; (2n-1) * (2n-1) 2n-2 d type flip flop of the capable employing of the n of pel array; (2n-1) * (2n-1) n d type flip flop of the capable employing of the n+1 of pel array, n+1 d type flip flop of the capable employing of n+2 all is to add 2n-2 d type flip flop of the capable employing of one, the 2n-1 line by line until the capable every row of 2n-1 adopts the number of d type flip flop; The 2nd kind of structure: when handling digital color image, this phase-locked/shift circuit group 19 and phase-locked/shift circuit group electronic circuit parallel processing identical by 3 constitutes; Wherein the circuit structure and the parameter of each phase-locked/shift circuit group electronic circuit and above-mentioned phase-locked/shift circuit group 19 when handling gray level image are identical; These 3 phase-locked/shift circuit group electronic circuits produce calculating digital color image fractional order differential required R, G, (2n-1) * (2n-1) pel array of a B3 component value respectively by digital color image being carried out a time-delay; This phase-locked/shift circuit group 19 adopts 9n altogether ²-9n d type flip flop.

See Fig. 1, fractional order differential mask convolution circuit 20 is to realize the circuit block of the fractional order differential most critical of digital picture in all forming circuit parts of fractional order differential filter of digital picture of the present invention, also is the core content that the present invention proposes fractional order differential filter new departure of this digital picture.For the circuit that clearly demonstrates fractional order differential mask convolution circuit 20 constitutes, be necessary that elder generation carries out following brief description to the operation rule of fractional order differential mask convolution circuit 20:

Because what digital circuit or digital filter were handled is digital quantity, its value is limited; The maximum variable quantity of picture signal gray scale is limited; The beeline that the digital picture grey scale change takes place can only be between two adjacent pixels, so two-dimensional digital image s (x, y) duration on x or y change in coordinate axis direction (size number of image array) may be that unit measures with the pixel only, (x, y) branches such as minimum on x or y change in coordinate axis direction may be h=1 only to s at interval.If the duration of one-dimensional signal s (t) is t ∈ [a, t], the signal duration [a, t] is carried out five equilibrium by branches such as unit interval h=1, its five equilibrium umber is $n={\left[\frac{t-a}{h}\right]}^{h=1}=[t-a].$ Can derive the backward difference approximate expression that one-dimensional signal s (t) fractional calculus Gr ü mwald-Letnikov defines with waiting Gr ü mwald-Letnikov definition (the Gr ü mwald-Letnikov definition of fractional calculus is the classics definition from research continuous function integer order derivative, expands the exponent number of calculus to non-integral order by the integer rank and derives) of branch umber n substitution fractional calculus: $\frac{d^{v}s\left(t\right)}{{\mathrm{dt}}^v}\≈s\left(t\right)+(-v)s(t-1)+\frac{(-v)(-v+1)}{2}s(t-2)+\frac{(-v)(-v+1)(-v+2)}{6}s(t-3)+\mathrm{\Λ}+\frac{\mathrm{\Γ}(-v+1)}{n!\mathrm{\Γ}(-v+n+1)}s(t-n)+\mathrm{\Λ}$ Wherein, v is the order (can get any real number) of fractional order differential.Order v can get mark or reasonable fractional value (because the computational length of digital circuit is limited, when v is unreasonable decimal, can approximate approximate reasonable decimal) among the present invention between 0～1; $\mathrm{\Γ}\left(\mathrm{\α}\right)=\underset{0}{\overset{\∞}{\∫}}{e}^{-x}{x}^{\mathrm{\α}-1}\mathrm{dx}=(\mathrm{\α}-1)!$ Expression Gamma function.The present invention's definition

S (x, y) the backward difference approximate expression of fractional order partial differential is respectively on x and y reference axis negative direction:

$\frac{{\∂}^{v}s(x,y)}{{\∂x}^v}\≈s(x,y)+(-v)s(x-1,y)+\frac{(-v)(-v+1)}{2}s(x-2,y)+\frac{(-v)(-v+1)(-v+2)}{6}s(x-3,y)+\mathrm{\Λ}+\frac{\mathrm{\Γ}(-v+1)}{n!\mathrm{\Γ}(-v+n+1)}s(x-n,y)+\mathrm{\Λ}$

$\frac{{\∂}^{v}s(x,y)}{{\∂y}^v}\≈s(x,y)+(-v)s(x,y-1)+\frac{(-v)(-v+1)}{2}s(x,y-2)+\frac{(-v)(-v+1)(-v+2)}{6}s(x,y-3)+\mathrm{\Λ}+\frac{\mathrm{\Γ}(-v+1)}{n!\mathrm{\Γ}(-v+n+1)}s(x,y-n)+\mathrm{\Λ}$

The preceding n item that the present invention chooses in above-mentioned two difference approximate expressions and respectively as s (x, y) approximation of fractional order partial differential on x and y reference axis negative direction:

$\frac{{\∂}^{v}s(x,y)}{{\∂x}^v}\≈s(x,y)+(-v)s(x-1,y)+\frac{(-v)(-v+1)}{2}s(x-2,y)+\frac{(-v)(-v+1)(-v+2)}{6}s(x-3,y)+\mathrm{\Λ}+\frac{\mathrm{\Γ}(-v+1)}{(n-1)!\mathrm{\Γ}(-v+n)}s(x-n+1,y),$

$\frac{{\∂}^{v}s(x,y)}{{\∂y}^v}\≈s(x,y)+(-v)s(x,y-1)+\frac{(-v)(-v+1)}{2}s(x,y-2)+\frac{(-v)(-v+1)(-v+2)}{6}s(x,y-3)+\mathrm{\Λ}+\frac{\mathrm{\Γ}(-v+1)}{(n-1)!\mathrm{\Γ}(-v+n)}s(x,y-n+1).$

As seen, (x, y) coefficient value of each the corresponding sum term in the approximation of fractional order partial differential (n item with) all is identical to s on x and y reference axis negative direction.The coefficient value that has only the first term sum term in this n zero coefficient values is constant " 1 ", and other n-1 zero coefficient values all is the function of fractional order differential order v.This n zero coefficient values is respectively in order:

Can prove that this n zero coefficient values sum is not equal to zero, this is one of image fractional order differential and the remarkable difference on characteristic of image integer rank differential.Digital picture s of the present invention (x, fractional order gradient y) (fractional order derivative) defines by one 2 dimensional vector: ${\&dtri;}^{v}s=\left[\begin{array}{c}{G}_x^v\\ G_y^v\end{array}\right]=\left[\begin{array}{c}\frac{{\&PartialD;}^{v}s}{{\&PartialD;x}^v}\\ \frac{{\&PartialD;}^{v}s}{{\&PartialD;y}^v}\end{array}\right];$ The mould value defined of fractional order gradient vector is: $\left|{\&dtri;}^{v}s\right|={[G_x^{{\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="A20061002170200371.png,A20061002170200381.png"\; state="\{\{state\}\}">v</figure-callout>}}^2}+G_y^{v^2}]}^{\frac{1}{2}}.$ Easy for computing, usually will

(promptly

With

In maximum) as the approximation of the mould value of fractional order gradient vector.In addition, because in digital picture, the gray value in the neighborhood between pixel and the pixel has very big correlation.See Fig. 1, in order to strengthen the anti-image rotatory of fractional order differential mask convolution circuit 20, be necessary to calculate respectively pixel s (x, y) approximation of the v rank fractional order partial differential (the inclined to one side gradient of fractional order) on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 directions of fractional order differential mask lower-right diagonal position line, and then ask the mould value of this 8 dimension fractional order gradient column vector.Easy for computing, (x, y) maximum in the mould value of the approximation of the v rank fractional order partial differential on these 8 directions is as s (x, the approximation of v rank fractional order differential y) with s in the present invention.

See Fig. 2, in complete zero square formation of n * n along on the central symmetry axis of x reference axis negative direction, with 1 ,-v,

This n zero coefficient values sequential replacement falls the null value on the relevant position in complete zero square formation of n * n, thereby the fractional order differential mask that constructs on the x axle negative direction (is used W _x ^-Expression).See Fig. 5, along on the central symmetry axis of y reference axis negative direction, use in complete zero square formation of n * n

This n zero coefficient values sequential replacement falls the null value on the relevant position in complete zero square formation of n * n, thereby the fractional order differential mask that constructs on the y axle negative direction (is used W _y ^-Expression).In addition, the fractional order differential mask on the x axle positive direction (is used W _x ⁺Fig. 4 is seen in expression), the fractional order differential mask on the y axle positive direction (uses W _y ⁺Fig. 6 is seen in expression), the fractional order differential mask on the diagonal of fractional order differential mask lower-left (uses W _{The diagonal angle, lower-left}Fig. 7 is seen in expression), the fractional order differential mask on the upper right diagonal of fractional order differential mask (uses W _{Upper right diagonal angle}Fig. 8 is seen in expression), the fractional order differential mask on the upper left diagonal of fractional order differential mask (uses W _{Upper left diagonal angle}Fig. 9 is seen in expression), the fractional order differential mask on the fractional order differential mask lower-right diagonal position line direction (uses W _{Lower-right diagonal position}Figure 10 is seen in expression) and W _x ^-And W _y ^-Aufbauprinciple and method similar, repeat no more here.

The operation rule of fractional order differential mask convolution circuit 20 is airspace filters that the scheme of employing fractional order differential mask convolution realizes the digital image fractional order differential.It is fit to the realization to the hardware handles circuit of data image signal.At the different in kind of digital picture, fractional order differential mask convolution circuit 20 at the operation rule of gray level image and digital color image is respectively:

A. fractional order differential mask convolution circuit 20 is at the operation rule of gray level image.The operation rule of fractional order differential mask convolution circuit 20 on x axle negative direction as shown in Figure 3, its operation rule on other 6 directions is similar with operation rule on x axle negative direction.Fractional order differential mask convolution circuit 20 at the step of the operation rule of gray level image is: in the 1st step, the digital video signal of serial input is imported fractional order differential mask (W on 8 directions respectively _x ^-, W _x ⁺, W _y ^-, W _y ⁺, W _{The diagonal angle, lower-left}, W _{Upper right diagonal angle}, W _{Upper left diagonal angle}And W _{Lower-right diagonal position}); The coordinate at unique constant coefficient value " 1 " place in the fractional order differential mask on these 8 directions (x, y) and the pixel s of pending fractional order differential (x, (x y) must keep overlapping coordinate position y); The 2nd step, the coefficient value on the fractional order differential mask on these 8 directions is multiplied each other with the gray value of the corresponding pixel of importing respectively, general's all product term additions (being weighted sum) separately obtain the weighted sum value on these 8 directions respectively then; The 3rd step because gray value value between 0～255 of digital picture, so need to the weighted sum value on these 8 directions carry out respectively amplitude limit (when the weighted sum value less than 0 the time, get 0; When the weighted sum value greater than 255 the time, get 255); The 4th step (was pixel s (x, y) approximation of the v rank fractional order partial differential on these 8 directions) as the result of fractional order differential mask convolution circuit 20 on these 8 directions respectively with the value of mould separately of the weighted sum value behind the amplitude limit on these 8 directions; In the 5th step, in the digital picture of pending fractional order differential, pursue the fractional order differential mask (W on above-mentioned 8 directions of pixel translation _x ^-, W _x ⁺, W _y ^-, W _y ⁺, W _{The diagonal angle, lower-left}, W _{Upper right diagonal angle}, W _{Upper left diagonal angle}And W _{Lower-right diagonal position}), constantly repeat the above-mentioned the 1st～4 operation rule that goes on foot respectively, travel through the digital picture of the pending fractional order differential of view picture, just can calculate the approximation of the v rank fractional order partial differential of view picture digital picture on these 8 directions; In addition, by the pixel translation time, be positioned at for the row or column that does not make fractional order differential mask outside the digital picture plane of pending fractional order differential, the central point that must make fractional order differential mask is not less than (n-1)/2 pixel apart from the distance of the digital picture edge pixel of pending fractional order differential, promptly the pixel apart from the digital picture edge n-1 row or column of pending fractional order differential is not carried out fractional order differential.

B. fractional order differential mask convolution circuit 20 is at the operation rule of digital color image.Fractional order differential mask convolution circuit 20 is basic identical at operation rule and its operation rule at gray level image of digital color image.Difference is each pixel s (x, y) R, G, a B3 component value all to go through respectively with fractional order differential mask convolution circuit 20 at the identical operation rule of gray level image, thereby obtain pixel s (x, the approximation of R y), G, the V rank fractional order partial differential of a B3 component value on above-mentioned 8 directions respectively.In other words, the fractional order differential mask convolution circuit 20 when handling digital color image is equivalent to fractional order differential mask convolution circuit 20 sums when handling gray level image of 3 parallel computations.Fractional order differential mask convolution circuit 20 roles when handling gray level image of these 3 parallel computations are parallel computation pixel s (x, approximations of R y), G, the B3 component value v valency fractional order partial differential on above-mentioned 8 directions respectively.

Specify the circuit structure of fractional order differential mask convolution circuit 20 below: see Fig. 1, fractional order differential mask convolution circuit 20 is made of the specific algorithm unit circuit 1～8 of 8 parallel computations; Different in kind according to pending digital picture, it is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, algorithm unit circuit 1～8 calculates the fractional order partial differential approximation of pixel on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 different directions of fractional order differential mask lower-right diagonal position line in the gray level image respectively; See Fig. 1 and Figure 11, each algorithm unit circuit lacks the individual multiplier of one n-1 (even number) 27～29, adder 30, amplitude limiter 31 and one and asks mould device 32 to constitute by count n (odd number) than the fractional order differential mask size; The non-zero weights of this n-1 multiplier 27～29 are according to being respectively in order: Amplitude limiter 31 is limited in the output valve of adder 30 in 0～255 the scope, when the input value of amplitude limiter 31 less than 0 the time, its output 0, when the input value of amplitude limiter 31 greater than 255 the time, its output 255; Ask the output valve feed-in maximum comparator 21 of mould device 32; The 2nd kind of structure: when handling digital color image, all identical by 3 and algorithm unit electronic circuit parallel computation of each the algorithm unit circuit in the algorithm unit circuit 1～8 constitutes; Algorithm unit circuit 1～8 has 8 * 3=24 algorithm unit electronic circuit; Each algorithm unit electronic circuit of the individual algorithm unit circuit of p in the algorithm unit circuit 1～8 (1≤p≤8) is all identical with the circuit structure and the parameter of above-mentioned p algorithm unit circuit when handling gray level image; R, G, the fractional order differential approximation of a B3 component value on above-mentioned 8 directions of pixel in 3 algorithm unit electronic circuits difference parallel computation digital color images in the algorithm unit circuit 1～8.See Fig. 1, fractional order differential mask convolution circuit 20 comprises that following 8 specific algorithm unit circuit constitute:

Algorithm unit circuit 1 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on x axle negative direction; According to the different in kind of pending digital picture, algorithm unit circuit 1 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)-H); Pixel S _x(k+ (n-1) gray value and weights (H+1)-2H) Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)-(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 1 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 1 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on x axle negative direction.

Algorithm unit circuit 2 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on x axle positive direction; According to the different in kind of the digital picture of handling, algorithm unit circuit 2 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)+H); Pixel S _x(k+ (n-1) gray value and weights (H+1)+2H) Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)+(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 2 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 2 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on x axle positive direction.

Algorithm unit circuit 3 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on y axle negative direction; According to the different in kind of the digital picture of handling, algorithm unit circuit 3 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _xFeed-in adder after the gray value of (k+ (n-1) (H+1)-1) and weights-v multiply each other; Pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)-2) Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)-(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 3 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 3 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on y axle negative direction.

Algorithm unit circuit 4 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on y axle positive direction; According to the different in kind of the digital picture of handling, algorithm unit circuit 4 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _xFeed-in adder after the gray value of (k+ (n-1) (H+1)+1) and weights-v multiply each other; Pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)+2) Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)+(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 4 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 4 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on y axle positive direction.

Algorithm unit circuit 5 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on the diagonal of fractional order differential mask lower-left; According to the different in kind of the digital picture of handling, algorithm unit circuit 5 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)-1+H); Pixel S _x(k+ (n-1) gray value and weights (H+1)-2+2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)-(m-1)+(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 5 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 5 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on the diagonal of fractional order differential mask lower-left.

Algorithm unit circuit 6 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on the upper right diagonal of fractional order differential mask; According to the different in kind of the digital picture of handling, algorithm unit circuit 6 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)+1-H); Pixel S _x(k+ (n-1) gray value and weights (H+1)+2-2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)+(m-1)-(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 6 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 6 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on the upper right diagonal of fractional order differential mask.

Algorithm unit circuit 7 calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on the upper left diagonal of fractional order differential mask; According to the different in kind of the digital picture of handling, algorithm unit circuit 7 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)-1-H); Pixel S _x(k+ (n-1) gray value and weights (H+1)-2-2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)-(m-1)-(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 7 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 7 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on the upper left diagonal of fractional order differential mask.

Algorithm unit circuit 8 calculating pixel S _x(k+ (n-1) (H+1)) approximation of v rank fractional order partial differential on fractional order differential mask lower-right diagonal position line direction; According to the different in kind of the digital picture of handling, algorithm unit circuit 8 is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)+1+H); Pixel S _x(k+ (n-1) gray value and weights (H+1)+2+2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)+(m-1)+(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit 8 and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit 8 when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xThe v rank fractional order partial differential approximation of 3 component values of R, G, B of (k+ (n-1) (H+1)) on fractional order differential mask lower-right diagonal position line direction.

See Fig. 1, maximum in 8 algorithm unit circuit output valves of maximum comparator 21 calculating fractional order differential mask convolution circuit 20, different in kind according to the digital picture of handling, maximum comparator 21 is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, maximum comparator 21 has 8 tunnel inputs, 1 tunnel output, input port 9～16 is the output gray level value of feed-in algorithm unit circuit 1～8 respectively, the maximum (being the v rank fractional order differential approximation of gray level image grey scale pixel value) in 8 feed-in gray values of output port 22 outputs; The 2nd kind of structure: when handling digital color image, maximum comparator 21 and maximum comparator electronic circuit parallel processing identical by 3 constitutes; Maximum comparator 21 wherein each maximum comparator electronic circuit is identical with the circuit structure and the parameter of the maximum comparator 21 when handling gray level image in the 1st kind of structure; R, the G of these 3 maximum comparator electronic circuits difference parallel computation digital color image pixels, the v rank fractional order differential approximation of a B3 component value.

Inventor of the present invention furtherd investigate with fractional order differential strengthen the digital image texture minutia basic principle and and operation rule, on this basis at this core content of signal processing circuit device of how to construct the digital image fractional order differential filter, input characteristics according to the character of digital image fractional order differential and Digital Image Processing, digital circuit, serial digital video code stream, new departure of a kind of signal processing circuit device of real-time enhancing digital picture complex texture minutia has been proposed, i.e. the fractional order differential filter of digital picture.Its popularization will particularly produce far-reaching influence in the analysis of data image signal and the application among the processing to fractional calculus among the analysis and processing of modern signal.

New departure below in conjunction with the signal processing circuit device of the fractional order differential filter example in detail of accompanying drawing and digital picture real-time enhancing digital picture complex texture minutia of the present invention:

Description of drawings

Fig. 1 is the electrical block diagram of the fractional order differential filter of digital picture of the present invention.

Fig. 2 is the fractional order differential mask n on the x axle negative direction * n square formation schematic diagram of algorithm unit circuit 1.

Fig. 3 is the operation rule schematic diagram on x axle negative direction of algorithm unit circuit 1.

Fig. 4 is the fractional order differential mask n on the x axle positive direction * n square formation schematic diagram of algorithm unit circuit 2.

The fractional order differential mask n on y axle negative direction of Fig. 5 algorithm unit circuit 3 * n square formation schematic diagram.

Fig. 6 is the fractional order differential mask n on the y axle positive direction * n square formation schematic diagram of algorithm unit circuit 4.

Fig. 7 is the fractional order differential mask n on the diagonal of the fractional order differential mask lower-left * n square formation schematic diagram of algorithm unit circuit 5.

Fig. 8 is the fractional order differential mask n on the upper right diagonal of the fractional order differential mask * n square formation schematic diagram of algorithm unit circuit 6.

Fig. 9 is the fractional order differential mask n on the upper left diagonal of the fractional order differential mask * n square formation schematic diagram of algorithm unit circuit 7.

Figure 10 is the fractional order differential mask n on the fractional order differential mask lower-right diagonal position line * n square formation schematic diagram of algorithm unit circuit 8.

Figure 11 is the common electrical block diagram of algorithm unit circuit 1～8.

Figure 12 is the fractional order differential filter circuit diagram of the digital picture when the v rank fractional order differential mask on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 directions of fractional order differential mask lower-right diagonal position line all is 3 * 3 square formation.

Wherein, 1～8 is respectively algorithm unit circuit on above-mentioned 8 directions; Port 9～16 is the approximation of the v rank fractional order partial differential of output digital image pixel on above-mentioned 8 directions respectively; Port one 7 input serial digital video code flow S _x(k); The 18th, the line storage group; The 19th, phase-locked/the shift circuit group; The 20th, the fractional order differential mask convolution circuit; The 21st, the maximum comparator; Port 22 output pixel S _xThe v rank fractional order differential S of (k+ (n-1) (H+1)) _x ^(v)The approximation of (k+ (n-1) (H+1)); Port 23 input pixel S _x(k+ (n-1) (H+1)) value; The input pixel value of port 24～26 is relevant with algorithm unit circuit 1～8, and the input pixel value difference of different algorithm unit circuit corresponding port 24～26 elaborates in the explanation of this specification about the circuit structure of algorithm unit circuit 1～8; 27～29th, n-1 the multiplier that function is identical; The 30th, adder; The 31st, amplitude limiter; The 32nd, ask the mould device; Port 33 output pixel S _xThe approximation of the gray value of (k+ (n-1) (H+1)) or R, G, the v rank fractional order partial differential of B component value on some directions of above-mentioned 8 directions; Port 34 input serial digital greyscale video code stream S _x(k); 35～38th, line storage; Port 39 output pixel S _x(k+H); Port 40 output pixel S _x(k+2H); Port 41 output pixel S _x(k+3H); Port 42 output pixel S _x(k+4H); Port 43 output pixel S _x(k+2H+2) gray value; Port 44～51 is output pixel S respectively _xThe approximation of the v rank fractional order partial differential of gray value (k+2H+2) on above-mentioned 8 directions; Port 52 output pixel S _xThe v rank fractional order differential S of gray value (k+2H+2) _x ^(v)(k+2H+2) approximation.

Embodiment

See Fig. 1, the particular circuit configurations and the circuit parameter of the cascade circuit structure of the fractional order differential filter of the digital picture of the present invention that is described in detail in the summary of the invention according to this specification and line storage group 18 thereof, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20 and maximum comparator 21 just can construct the physical circuit of the fractional order differential filter of this digital picture.In addition, in the concrete process of implementing, should also be noted that: 1., the order v of this fractional order differential mask convolution circuit 20 can get mark or reasonable fractional value between 0～1, according to the different requirements of engineering precision, order v is divided into three types floating data, the calculated data type of algorithm unit circuit 1～8 also is divided into corresponding three types: the 1st type: single (accounts for 4 byte of memorys, computational length 32bit, 6～7 of significant digits, evaluation scope 10- ³⁷～10 ³⁸); The 2nd type: double (accounts for 8 byte of memorys, computational length 64bit, 15～16 of significant digits, evaluation scope 10 ^-307～10 ³⁰⁸); The 3rd type: long double (accounts for 16 byte of memorys, computational length 128bit, 18～19 of significant digits, evaluation scope 10 ^-4931～10 ⁴⁹³²); 2., the v rank fractional order differential mask (W of the present invention on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 directions of fractional order differential mask lower-right diagonal position line _x ^-, W _x ⁺, W _y ^-, W _y ⁺, W _{The diagonal angle, lower-left}, W _{Upper right diagonal angle}, W _{Last diagonal angle}And W _{Lower-right diagonal position}) in n zero coefficient values be respectively in order:

With traditional all zero coefficient values sums based in the digital picture integer rank differential mask of integer rank differential is zero different, and n zero coefficient values sum in the v rank fractional order differential mask on these 8 directions of the present invention is non-vanishing, promptly $1+(-v)+\frac{(-v)(-v+1)}{2}+\frac{(-v)(-v+1)(-v+2)}{6}+\mathrm{\&Lambda;}+\frac{\mathrm{\&Gamma;}(-v+1)}{(n-1)!\mathrm{\&Gamma;}(-v+n)}\&NotEqual;0.$ To multiply by " 1 " its value constant because of any number again, thus when making up physical circuit in order to reduce the number of used multiplier, only choose-v,

This n-1 zero coefficient values is as the weight coefficient value of multiplier; 3., in order to make fractional order differential mask (it is the square formation of a n * n) clear and definite axial symmetry center is arranged, the size number n of fractional order differential mask is an odd number; The minimum value of n is 3, the maximum occurrences of n less than the size number of the digital picture of pending fractional order differential (if (x y) is the picture element matrix of L * H to the digital picture S of pending fractional order differential, and when L=H, its size number is L; When L ≠ H, its size number is the minimum value among L and the H); 4., according to the different in kind of pending digital picture, should treat with a certain discrimination for the processing of gray level image and digital color image.Fractional order differential mask convolution circuit 20 of the present invention is basic identical at operation rule and its operation rule at gray level image of digital color image, difference is each pixel s (x, y) R, G, a B3 component value all will be gone through respectively and fractional order differential mask convolution circuit 20 identical operation rules when handling gray level image, thereby obtain pixel s (x, the approximation of R y), G, the v rank fractional order partial differential of a B3 component value on above-mentioned 8 directions respectively.In other words, fractional order differential mask convolution circuit 20 sums when handling gray level image that are equivalent to 3 parallel computations in order to the fractional order differential mask convolution circuit 20 of handling digital color image.Fractional order differential mask convolution circuit 20 roles when handling gray level image of these 3 parallel computations are parallel computation pixel s (x, approximations of R y), G, the v rank fractional order partial differential of 3 component values of B on above-mentioned 8 directions respectively; 5., fractional order differential mask convolution circuit 20 in the fractional order differential filter of digital picture of the present invention is not limited to the scheme that Figure 11 adopts, it can adopt structure shown in the fractional order differential mask convolution circuit 20 among Fig. 1 in general, any concrete measure of the operation rule of fractional order differential mask convolution circuit 20 of the present invention of realizing with hardware circuit all can be derived a kind of concrete scheme of fractional order differential filter of digital picture, and this need be chosen at concrete use background.

Now be described below for example:

See Fig. 1 and Figure 12, if make up the physical circuit of the fractional order differential filter of a gray level image, in the engineering practical application, the scheme of the fractional order differential mask convolution of the normal employing 3 * 3 of the operation rule of the fractional order differential mask convolution circuit 20 in this filter realizes the pixel S (x to gray level image, y) v rank fractional order partial differential, as shown in the above description: in x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, v rank fractional order differential mask (W on the upper left diagonal of fractional order differential mask and 8 directions of fractional order differential mask lower-right diagonal position line _x ^-, W _x ⁺, W _y ^-, W _y ⁺, W _{The diagonal angle, lower-left}, W _{Upper right diagonal angle}, W _{Upper left diagonal angle}And W _{Lower-right diagonal position}) size number n=3,3 zero coefficient values in the v rank fractional order differential mask on these 8 directions are respectively in order: $1,-v,\frac{(-v)(-v+1)}{2}=\frac{v^2-\mathrm{<figure-callout\; id="2"\; label="v"\; filenames="A20061002170200371.png,A20061002170200381.png"\; state="\{\{state\}\}">v</figure-callout>}}{2}.$ So wherein line storage group 18 adopts 2n-2| _N=3=4 line storages are finished 2n-1| _N=3Obtaining of=5 row vedio datas; Wherein phase-locked/shift circuit group 19 adopts 3n altogether ²-3n| _N=3=18 d type flip flops produce required (2n-1) * (2n-1) of calculating gray level image fractional order differential by gray level image being carried out a time-delay | _N=3=5 * 5 pel arrays; Wherein algorithm unit circuit 1～8 has 8 * (n-1) | _N=3=16 multipliers, n-1| in each algorithm unit circuit _N=3The non-zero weights of=2 multipliers are according to being respectively in order:

So, as shown in figure 12, the particular circuit configurations and the circuit parameter of the cascade circuit structure of the fractional order differential filter of the digital picture of being narrated in the summary of the invention according to this specification of the present invention and line storage group 18 thereof, phase-locked/shift circuit group 19, fractional order differential mask convolution circuit 20 and maximum comparator 21 just can construct the physical circuit of the fractional order differential filter of this digital picture easily.Under the prerequisite of the physical circuit of the fractional order differential filter that does not influence accurate this digital picture of statement, in order to describe the physical circuit of algorithm unit circuit 1～8 wherein more clearly, Figure 12 do not draw sequential control circuit wherein and the timing control signal that is triggered and produces thereof.

Claims (7)

1, a kind of fractional order differential filter of digital picture is characterized in that: it is to be formed with maximum comparator (21) cascade by digital video frequency flow line storage group (18), phase-locked/shift circuit group (19), fractional order differential mask convolution circuit (20); Serial digital video code stream S _x(k) be divided into three the tunnel after port (17) input: the first via is passed through after line storage group (18), phase-locked/shift circuit group (19), fractional order differential mask convolution circuit (20) handle in proper order, respectively at port (9～16) output pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 directions of fractional order differential mask lower-right diagonal position line, after passing through maximum comparator (21) again and handling, export maximum in these 8 approximations as pixel S at port (22) _xThe v rank fractional order differential value approximation S of (k+ (n-1) (H+1)) _x ^(v)(k+ (n-1) (H+1)); The second the tunnel triggers sequential control circuit produces corresponding timing control signal; Third Road with the output feed-in of line storage group (18) phase-locked/shift circuit group (19) generates the pel array of (2n-1) * (2n-1).

2, the fractional order differential filter of digital picture according to claim 1 is characterized in that: wherein line storage group (18) is made of sequential control circuit, read/write address generator and two-port RAM group; Sequential control circuit produces the timing control signal of control corresponding read/write address generator, two-port RAM group, phase-locked/shift circuit group (19), fractional order differential mask convolution circuit (20) and maximum comparator (21) operation under the triggering of the row of input digit video flowing, a useful signal; The read/write address generator produces the read/write address of two-port RAM under the effect of timing control signal, and is responsible for handling read/write address initialization and rotating problem; Line storage group (18) is according to the input characteristics of serial digital video code stream, utilize current input pixel, different in kind according to the digital picture of handling, line storage group (18) is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, this line storage group (18) adopts 2n-2 line storage to finish obtaining of the capable vedio data of 2n-1; The 2nd kind of structure: when handling digital color image, line storage group (18) and line storage group electronic circuit parallel processing identical by 3 constitutes; Wherein the circuit structure and the parameter of each line storage group electronic circuit and above-mentioned line storage group (18) when handling gray level image are identical; R, G, a B3 component value of the parallel respectively storage digital color image of these 3 line storage group electronic circuits; Line storage group (18) adopts 6n-6 line storage altogether, and wherein each line storage group electronic circuit adopts 2n-2 line storage to finish obtaining of 2n-1 line number word video color image respective component value.

3, the fractional order differential filter of digital picture according to claim 1, it is characterized in that: phase-locked/shift circuit group (19) wherein is according to the input characteristics of serial digital video code stream, utilize current input pixel, different in kind according to the digital picture of handling, phase-locked/shift circuit group (19) is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, this phase-locked/shift circuit group (19) adopts 3n altogether ²-3n d type flip flop produces required (2n-1) * (2n-1) pel array of calculating gray level image fractional order differential by gray level image being carried out a time-delay; (2n-1) * (2n-1) the 1st of pel array the row adopts 2n-2 d type flip flop, and the 2nd row adopts 2n-3 d type flip flop, all is to subtract n d type flip flop of the capable employing of one, the n-1 line by line until the capable every row of n-1 adopts the number of d type flip flop; (2n-1) * (2n-1) 2n-2 d type flip flop of the capable employing of the n of pel array; (2n-1) * (2n-1) n d type flip flop of the capable employing of the n+1 of pel array, n+1 d type flip flop of the capable employing of n+2 all is to add 2n-2 d type flip flop of the capable employing of one, the 2n-1 line by line until the capable every row of 2n-1 adopts the number of d type flip flop; The 2nd kind of structure: when handling digital color image, this phase-locked/shift circuit group (19) and phase-locked/shift circuit group electronic circuit parallel processing identical by 3 constitutes; Wherein the circuit structure and the parameter of each phase-locked/shift circuit group electronic circuit and above-mentioned phase-locked/shift circuit group (19) when handling gray level image are identical; These 3 phase-locked/shift circuit group electronic circuits produce calculating digital color image fractional order differential required R, G, (2n-1) * (2n-1) pel array of a B3 component value respectively by digital color image being carried out a time-delay; This phase-locked/shift circuit group (19) adopts 9n altogether ²-9n d type flip flop.

4, the fractional order differential filter of digital picture according to claim 1 is characterized in that: fractional order differential mask convolution circuit (20) wherein is made of the specific algorithm unit circuit (1～8) of 8 parallel computations; Different in kind according to pending digital picture, it is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, algorithm unit circuit (1～8) calculates the fractional order partial differential approximation of pixel on x axle negative direction, x axle positive direction, y axle negative direction, y axle positive direction, fractional order differential mask lower-left diagonal, the upper right diagonal of fractional order differential mask, the upper left diagonal of fractional order differential mask and 8 different directions of fractional order differential mask lower-right diagonal position line in the gray level image respectively; Each algorithm unit circuit asks mould device (32) to constitute by count the individual multiplier of n-1 (even number) (27～29) that n (odd number) lacks one, an adder (30), an amplitude limiter (31) and one than the fractional order differential mask size; The non-zero weights of this n-1 multiplier (27～29) are according to being respectively in order :-v,

Amplitude limiter (31) is limited in the output valve of adder (30) in 0～255 the scope, when the input value of amplitude limiter (31) less than 0 the time, its output 0, when the input value of amplitude limiter (31) greater than 255 the time, its output 255; Ask the output valve feed-in maximum comparator (21) of mould device (32); The 2nd kind of structure: when handling digital color image, all identical by 3 and algorithm unit electronic circuit parallel computation of each the algorithm unit circuit in the algorithm unit circuit (1～8) constitutes; Algorithm unit circuit (1～8) has 24 algorithm unit electronic circuits; Each algorithm unit electronic circuit of the individual algorithm unit circuit of p (1≤p≤8) in the algorithm unit circuit (1～8) is all identical with the circuit structure and the parameter of above-mentioned p algorithm unit circuit when handling gray level image; R, G, the fractional order differential approximation of a B3 component value on above-mentioned 8 directions of pixel in 3 algorithm unit electronic circuits difference parallel computation digital color images in the algorithm unit circuit (1～8).Fractional order differential mask convolution circuit (20) comprises that following 8 specific algorithm unit circuit constitute:

Algorithm unit circuit (1) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on x axle negative direction; According to the different in kind of pending digital picture, algorithm unit circuit (1) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)-H); Pixel S _x(k+ (n-1) gray value and weights (H+1)-2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)-(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (1) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (1) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on x axle negative direction;

Algorithm unit circuit (2) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on x axle positive direction; According to the different in kind of the digital picture of handling, algorithm unit circuit (2) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)+H); Pixel S _x(k+ (n-1) gray value and weights (H+1)+2H) Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)+(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (2) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (2) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on x axle positive direction;

Algorithm unit circuit (3) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on y axle negative direction; According to the different in kind of the digital picture of handling, algorithm unit circuit (3) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _xFeed-in adder after the gray value of (k+ (n-1) (H+1)-1) and weights-v multiply each other; Pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)-2) Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)-(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (3) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (3) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on y axle negative direction;

Algorithm unit circuit (4) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on y axle positive direction; According to the different in kind of the digital picture of handling, algorithm unit circuit (4) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _xFeed-in adder after the gray value of (k+ (n-1) (H+1)+1) and weights-v multiply each other; Pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)+2)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) (H+1)+(m-1))

Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (4) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (4) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on y axle positive direction;

Algorithm unit circuit (5) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on the diagonal of fractional order differential mask lower-left; According to the different in kind of the digital picture of handling, algorithm unit circuit (5) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)-1+H); Pixel S _x(k+ (n-1) gray value and weights (H+1)-2+2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)-(m-1)+(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (5) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (5) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on the diagonal of fractional order differential mask lower-left;

Algorithm unit circuit (6) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on the upper right diagonal of fractional order differential mask; According to the different in kind of the digital picture of handling, algorithm unit circuit (6) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)+1-H); Pixel S _x(k+ (n-1) gray value and weights (H+1)+2-2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)+(m-1)-(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (6) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (6) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on the upper right diagonal of fractional order differential mask;

Algorithm unit circuit (7) calculating pixel S _xThe approximation of (k+ (n-1) (H+1)) v rank fractional order partial differential on the upper left diagonal of fractional order differential mask; According to the different in kind of the digital picture of handling, algorithm unit circuit (7) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)-1-H); Pixel S _x(k+ (n-1) gray value and weights (H+1)-2-2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)-(m-1)-(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (7) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (7) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on the upper left diagonal of fractional order differential mask;

Algorithm unit circuit (8) calculating pixel S _x(k+ (n-1) (H+1)) approximation of v rank fractional order partial differential on fractional order differential mask lower-right diagonal position line direction; According to the different in kind of the digital picture of handling, algorithm unit circuit (8) is divided into two kinds of structures: the 1st kind of structure: as the digital video frequency flow S of input _xWhen (k) being gray level image, pixel S _xThe direct feed-in adder of gray value of (k+ (n-1) (H+1)); Pixel S _x(k+ (n-1) gray value and weights-v back feed-in adder that multiplies each other (H+1)+1+H); Pixel S _x(k+ (n-1) gray value and weights (H+1)+2+2H)

Back feed-in adder multiplies each other; By that analogy, if 1≤m≤n, pixel S _xThe gray value and the weights of (k+ (n-1) is H (H+1)+(m-1)+(m-1)) Back feed-in adder multiplies each other; The 2nd kind of structure: as the digital video frequency flow S of input _xWhen (k) being digital color image, algorithm unit circuit (8) and algorithm unit electronic circuit parallel computation identical by 3 constitutes; Wherein the circuit structure and the parameter of each algorithm unit electronic circuit and above-mentioned algorithm unit circuit (8) when handling gray level image are identical; These 3 algorithm unit electronic circuits are parallel computation pixel S respectively _xR, the G of (k+ (n-1) (H+1)), the B3 component value v rank fractional order partial differential approximation on fractional order differential mask lower-right diagonal position line direction.

5, fractional order differential mask convolution circuit according to claim 4, it is characterized in that: the order v of fractional order differential mask convolution circuit (20) can get mark or reasonable fractional value between 0～1, different requirements according to engineering precision, order v is divided into three types floating data, the calculated data type of its algorithm unit circuit (1～8) also is divided into corresponding three types: the 1st type: single (accounts for 4 byte of memorys, computational length 32bit, 6～7 of significant digits, evaluation scope 10 ^-37～10 ³⁸); The 2nd type: double (accounts for 8 byte of memorys, computational length 64bit, 15～16 of significant digits, evaluation scope 10 ^-307～10 ³⁰⁸); The 3rd type: long double (accounts for 16 byte of memorys, computational length 128bit, 18～19 of significant digits, evaluation scope 10 ^-4931～10 ⁴⁹³²).

6, fractional order differential mask convolution circuit according to claim 4 is characterized in that: in order to make fractional order differential mask clear and definite axial symmetry center is arranged, the size number n of fractional order differential mask is an odd number; The minimum value of n is 3, and (if the digital picture of pending fractional order differential is the picture element matrix of L * H, when L=H, its size number is L to the maximum occurrences of n less than the size number of the digital picture of pending fractional order differential; When L ≠ H, its size number is the minimum value among L and the H).

7, the fractional order differential filter of digital picture according to claim 1, it is characterized in that: the maximum in maximum comparator (21) computational algorithm element circuit (1～8) output valve wherein, different in kind according to the digital picture of handling, maximum comparator (21) is divided into two kinds of structures: the 1st kind of structure: when handling gray level image, maximum comparator (21) has 8 tunnel inputs, 1 tunnel output, input port (9～16) is the output gray level value of feed-in algorithm unit circuit (1～8) respectively, the maximum (being the v rank fractional order differential approximation of gray level image grey scale pixel value) in 8 feed-in gray values of output port (22) output; The 2nd kind of structure: when handling digital color image, maximum comparator (21) and maximum comparator electronic circuit parallel processing identical by 3 constitutes; Maximum comparator (21) wherein each maximum comparator electronic circuit is identical with the circuit structure and the parameter of the maximum comparator (21) when handling gray level image in the 1st kind of structure; R, the G of these 3 maximum comparator electronic circuits difference parallel computation digital color image pixels, the v rank fractional order differential approximation of a B3 component value.

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