CN1913505A - Low dissipation joint balance decoder for billi Ethernet - Google Patents
Low dissipation joint balance decoder for billi Ethernet Download PDFInfo
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- CN1913505A CN1913505A CN 200610029875 CN200610029875A CN1913505A CN 1913505 A CN1913505 A CN 1913505A CN 200610029875 CN200610029875 CN 200610029875 CN 200610029875 A CN200610029875 A CN 200610029875A CN 1913505 A CN1913505 A CN 1913505A
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Abstract
This invention relates to a KM Ethernet low power loss combined balance decoder, which adds three modules on a current pre-filtered parallel judgement feed-back decoder: a symbol detection module, a symbol loading module and a control module. When the Ethernet is at the idle state, the lattice coding and decoding related part of the feed back decoder is closed to reduce power loss, when the frame head of the Ethernet appears, all related modules of the decoder are started instantly to finish data decoding and the decoder is converted back to the low power loss mode again after finishing decoding of frames so as to greatly reduce power loss of Ethernet adapters.
Description
Technical field
The present invention relates to a kind of equalizer of communication technical field, particularly a kind of 802.3ab 1000Base-T gigabit Ethernet low-power consumption joint equalization decoder that detects based on ethernet frame.
Background technology
Meet IEEE802.3ab 1000Base-T standard, become the main flow of local area network (LAN) based on the gigabit Ethernet of non-shielding Category-5 twisted pair day by day.In order in the 1000Base-T gigabit Ethernet, to have used Digital Signal Processing to eliminate various crosstalking, echo and intersymbol interference to be equivalent to the speed transceive data of ten times of Fast Ethernets on the medium identical with Fast Ethernet.And having used Trellis-coded modulation with further raising signal to noise ratio, this is coded in the coding gain that 6dB can be provided in the no intersymbol interference channel.But discrete equilibrium-decode structures in the intersymbol interference channel, for example Jing Dian DFF+Viterbi decoder performance is owing to error propagation serious in the DFF loses seriously, and high performance maximum-likelihood sequence estimation hardware algorithm complexity can't be accepted.Take into account hardware complexity simultaneously in order to make full use of the performance gain that Trellis-coded modulation brings, all kinds of joint equalization decoder architectures such as parallel judgment feedback decoder, pre-filtering parallel judgment feedback decoder have generally been used in all kinds of 1000Base-T gigabit ethernet transceivers application.Karatsch wherein, E.F. the pre-filtering parallel judgment feedback decoder (Karatsch of Ti Chuing, E.F.and Azadet, K.A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet.Solid-State Circuits, IEEE Journal of Volume 36, Issue 3, March 2001 Page (s): 374-384) under the very little situation of performance loss, have less area and power consumption, therefore obtained using the most widely.
But, gigabit Ethernet is under the idle condition state of non-transfer of data, comprise interframe, three level codings of transmitting on line under startup/training and the carrier extend all belong to 0 work song group of grid coding, therefore the work of Trellis-coded modulation decoder just no longer includes necessity, works in classical DFF three level modes under and can finish equilibrium and obtain performance above above-mentioned arbitrary joint equalization decoder.And do not consider this problem in the existing technology, therefore research is a kind of on existing joint equalization decoding technique basis can close the grid coding decoder between ethernet frame, the joint equalization decoder that just starts the grid coding decoded portion where necessary has realistic meaning for the power consumption that reduces ethernet transceiver.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art, a kind of gigabit Ethernet low-power consumption joint equalization decoder is provided.The present invention is by designing the detection of Ethernet frame head and fast initialization structure that a class goes for pre-filtering parallel judgment feedback decoder, when Ethernet is in idle condition, the grid coding decoding relevant portion of pre-filtering parallel judgment feedback decoder is closed to reduce power consumption, when detecting the Ethernet frame head and occur, the whole correlation modules of OnNow decoder are finished data decode and once more decoder is changed back low-power consumption mode after being finished frame decoding.Can reduce the power consumption of Ethernet Adaptation Unit greatly by this mode.The present invention is applicable to and respectively is used in the 1000Base-T gigabit Ethernet or has the pre-filtering parallel judgment feedback decoder that similar transmission idle signal characteristic is used, can not lose performance, and the increase of decoder hardware complexity seldom.
The present invention is achieved by the following technical solutions: the present invention adds three modules on existing pre-filtering parallel judgment feedback decoder: symbol detection module, symbol loading module and control module.The symbol detection module first input end connects the judgement output of three level decision devices of original decision-feedback pre-filtering module interpolation, second input is connected to the descrambling information output of Physical Coding Sublayer, symbol detection module first output is connected to the control module output, second output is connected to symbol loading module input, is connected to the Physical Coding Sublayer input; Symbol detection module will be from three level decision signal transmitting symbol loading modules of decision-feedback pre-filtering module, simultaneously it is finished pre decoding and sends it to Physical Coding Sublayer, if detect this busy signal of three level decision signal then send a message to control module; Control module input bound symbol detection module output, output are connected to whole original and newly-increased module except that himself pre-filtering parallel judgment feedback decoder as control signal; The process that the control decoder starts after receiving busy signal message if pre-filtering parallel judgment feedback decoder is in idle condition, and change standby over to or the carrier extend pattern changes pre-filtering parallel judgment feedback decoder over to idle pulley at present again at Physical Coding Sublayer; Symbol loading module input is connected to the symbol detection module output, output be connected to add-compare-select module input; Under the control of control module, the symbol loading module is packed correct data into so that the correct operating state of pre-filtering parallel judgment feedback decoder to be set in the retention memory cell of pre-filtering parallel judgment feedback decoder in start-up course.
Described symbol detection module, processing is from the decision signal of the three level decision devices that added in the original decision-feedback pre-filtering of pre-filtering parallel judgment feedback decoder module, and is used to finish quick pre decoding and judge whether it is in the set of signals of idle signal from the descrambling data of Physical Coding Sublayer.Then forwarding it to idle signal for idle signal is encoded to them 4 bits and is sent to Physical Coding Sublayer when insmoding.When the signal that is transmitted on the Ethernet was between ethernet frame, this signal can replace the output of former pre-filtering parallel judgment feedback decoder and fully without any performance loss.When detecting busy signal, then notify the beginning of control module with the sign ethernet frame.
Described control module, the output of accepting symbol detection module are connected to utilize its setting state self mode of operation with the Physical Coding Sublayer state machine as input simultaneously.The remainder of its output control pre-filtering parallel judgment feedback decoder comprises except that the whole original and interpolation module himself.In control module,, set the flag bit of idle and normal two patterns for finishing control operation.Under idle pulley, control module switches to low-power consumption mode with pre-filtering parallel judgment feedback decoder, and the grid coding decoder that it comprised is closed to save power consumption, and pre-filtering this moment parallel judgment feedback decoder is only finished equalization operation to idle signal; Under normal mode, then the grid coding decoder to be opened, pre-filtering this moment parallel judgment feedback decoder can be finished the equilibrium and the decode operation of the desired transmission signals of its original design.Under idle pulley, control module remove to be retained incorrect data in the memory cell (original part of pre-filtering parallel judgment feedback decoder) by the reset/set control circuit of the original retention memory cell of control, and the reset/set control circuit by original adding-compare-selected cell will add-compare-and selected cell (original part of pre-filtering parallel judgment feedback decoder) places correct initial condition.Under the idle pulley, control module is cut off the clock that does not need working portion that comprises one dimension branch metric unit/four-dimensional metric element/add-compare-selected cell/retention memory cell in the pre-filtering parallel judgment feedback decoder by Clock Gating Technique, with further reduction power consumption.When pre-filtering parallel judgment feedback decoder need be when idle pulley changes normal mode of operation over to, control module is by carrying out a start-up course to finish the fast initialization of pre-filtering parallel judgment feedback decoder to symbol loading module and amended pre-filtering module.Otherwise when the Physical Coding Sublayer state machine entered standby mode, then control module also changed idle pulley over to.
Described decision-feedback pre-filtering module, 5 level/double mode decision device of 3 level that the pre-filtering pattern of original decision-feedback pre-filtering module is comprised replaces with independently 5 level decision devices and 3 level decision devices, and the latter's judgement directly exports symbol detection module to.Under normal mode, the internal feedback of decision-feedback pre-filtering module is with originally identical, based on the output of 5 level decision devices.Under idle pulley, its internal feedback is then exported based on 3 level decision devices.This kind pattern act the feedback pre-decision device work in 3 level modes, and obtain surpassing the performance boost of the theoretical coding gain of pre-filtering parallel judgment feedback decoder, make its output can replace the output of pre-filtering parallel judgment feedback decoder and do not bring performance loss.
Described decision-feedback pre-filtering module, preceding N level in the former serial input-serial output delay line that is useful on the coupling output delay is modified to the serial input-serial output delay line with parallel set function, be used under the start-up course under the control module control will the back to intersymbol interference elimination work level and smooth be transferred to thereafter parallel judgment feedback decoder from decision-feedback pre-filtering module, add this process to eliminate the influence of retaining mismark in the memory cell.Wherein N back packing into to intersymbol interference tap number M and symbol loading module of depending on that decision-feedback pre-filtering module keeps retained the symbolic number I of memory cell, and satisfies N=M-I.
Described symbol loading module transmitting idle characters from symbol detection module as input, and is finished under the control of control module under the start-up mode for the fast initialization of retaining memory cell.Correct data are substituted in frozen 0 son group, 4 dimension branch metric element output signals under the idle pulley, make decoder be in correct initial condition in order to upgrade the retention memory cell.This process can reduce the modification to decision-feedback pre-filtering module.Improve the symbolic number I that loads and to reduce the length that need be revised as serial input-serial output delay line, but generally be no more than 2 with parallel set function.
With 1 tap pre-filtering parallel judgment feedback decoder is that example illustrates the course of work of the present invention: free of data transmission on Ethernet under the initial condition, what transmitted this moment on netting twine is idle characters.The pre-filtering parallel judgment feedback decoder of receiving terminal works in idle pulley, its grid coding decoder is closed and initialization, decision-feedback pre-filtering module works in three level judgement balanced mode, court verdict is sent to symbol detection module and is used to monitor sign pattern, is sent to the control information of Physical Coding Sublayer to recover wherein to comprise.When transmitting terminal began to send data, data were encapsulated into ethernet frame and transmit.This frame will because the SSD1 symbol belongs to 3 level signals, therefore can and be finished judgement by the correct equilibrium of the decision-feedback pre-filtering module under the idle pulley by the SSD1 sign-on.Symbol detection module is used to descramble signal from Physical Coding Sublayer and detects this judgement and do not belong to idle characters.This moment, symbol detection module notice control module was finished start-up course, changed pre-filtering parallel judgment feedback decoder over to normal operating conditions.In this process, the I/O of parallel judgment feedback decoding and internal register clock are opened; The first busy symbol that the symbol loading module is packed into and transmitted from symbol detection module in state 0 first order of retaining module; Decision-feedback pre-filtering module switches to 5 level decision patterns with internal feedback, and finishes the loading that the degree of depth is 1 delay line.Start-up course was promptly accused and was finished this moment, and the state of decoder is by correct 0 state that is set at and begin to carry out the decoding of current ethernet frame thus.After treating that ethernet frame finishes, transmission symbol comes back to idle characters after by the Ethernet postamble.The Physical Coding Sublayer state machine detects this postamble and gets back to standby mode, control module is also got back to idle pulley after detecting this state variation of Physical Coding Sublayer state machine, close and initialization grid coding decoder, decision-feedback pre-filtering module is switched back three level judgement balanced mode.So far the reception of an ethernet frame finishes, and gets back to initial condition, treats that next ethernet frame repeats this process when beginning.
The present invention is by changing all kinds of pre-filtering parallel judgment feedback decoders that are used for gigabit ethernet transceiver over to low power consumpting state at one's leisure, and the quick startup of pre-filtering parallel judgment feedback decoder when having realized that detecting frame head occurs, do not losing performance and significantly do not increasing the power consumption that significantly reduces Ethernet pre-filtering parallel judgment feedback decoder circuit under the prerequisite of hardware complexity, direct meaning is being arranged for the battery life that reduces energy resource consumption and prolong mobile device.Be to use this structure on 1 the pre-filtering parallel judgment feedback decoder a residual intersymbol interference tail length, it is reduced to 18% before using this structure in the power consumption under the idle pulley, and for the pre-filtering parallel judgment feedback decoder under other parameter configuration, because this structure is directly closed the major part of decoder by Clock Gating Technique, its validity is unquestionable equally.The present invention can be suitable for but be not limited to the joint equalization decoder of pre-filtering parallel judgment feedback decoder form.
Description of drawings
Fig. 1 is existing pre-filtering parallel judgment feedback decoder structure
Fig. 2 is a system of the present invention schematic block diagram
Fig. 3 is existing decision-feedback pre-filtering module schematic block diagram
Fig. 4 is for being applied to the present invention, amended decision-feedback pre-filtering module schematic block diagram
Embodiment
Because the SSD1 of sign Ethernet frame head and SSD2 sign also are 3 level codings but do not belong to free code signal subclass.Therefore can utilize classical three level DFF to finish to the equilibrium of interframe idle signal and by symbol judgement, and it is finished detection, if then think the beginning of ethernet frame when finding busy symbol, the correct judgment rate of the method is far above decoding of traditional pre-filtering parallel judgment feedback decoder and the mode that detects by Physical Coding Sublayer, and a large amount of error codes influences adaptive channel estimation and digital timing recovery under the situation of the frame head that can effectively prevent loss.Detecting ethernet frame finishes then can the Physical Coding Sublayer state machine to change over to and waits for or the carrier extend state is sign.In pre-filtering parallel judgment feedback decoder,, only need to add one 3 level decision device and be used for getting final product under the idle pulley by symbol judgement owing to comprised classical DFF in the realization of decision-feedback pre-filtering module.The remainder of pre-filtering parallel judgment feedback decoder can be closed and can be effectively reduced power consumption, and the each several part state is listed in the table 1 under the idle pulley.
| Pre-filtering parallel judgment feedback decoder | |
| Decision-feedback pre-filtering module | Open the PAM3 pattern |
| 1 dimension branch metric unit | Close |
| 4 dimension branch metric unit | Close |
| Add-compare-selected cell | Close |
| Retain memory cell | Close |
| The decision-feedback unit | Close |
Table 1
On the other hand, because the renewal of retention memory cell under idle pulley of pre-filtering parallel judgment feedback decoder be by freeze all, therefore can be when restarting owing to be in the action that leads to errors of the initial condition of mistake.Need decision-feedback pre-filtering module is made an amendment for this reason, add 3 level mode decision devices and be written into function for common serial input string line output delay line adds to walk abreast.
Fig. 1 is existing classical pre-filtering parallel judgment feedback decoder structure.Also can take various leading computing technique to improve the operating frequency of circuit in realization at different technology, therefore influence indicates in the drawings owing to do not have directly for the present invention.
Fig. 2 is the pre-filtering parallel judgment feedback decoder that has added after the structure of the present invention, original part is represented with solid line, dotted portion is symbol detection module, symbol loading module and control module that the present invention added, and all for clarity gated clock logic and reset control logics do not mark in the drawings.In order to be unlikely to influence the speed of circuit, all interpolation logics are not in the critical path of decoder, can prevent the influence to pre-filtering parallel judgment feedback decoder service speed.The symbol detection module first input end connects the judgement output of three level decision devices of original decision-feedback pre-filtering module interpolation, second input is connected to the descrambling information output of Physical Coding Sublayer, symbol detection module first output is connected to the control module output, second output is connected to symbol loading module input, is connected to the Physical Coding Sublayer input; Symbol detection module will be from three level decision signal transmitting symbol loading modules of decision-feedback pre-filtering module, simultaneously it is finished pre decoding and sends it to Physical Coding Sublayer, if detect this busy signal of three level decision signal then send a message to control module; Control module input bound symbol detection module output, output are connected to whole original and newly-increased module except that himself pre-filtering parallel judgment feedback decoder as control signal; Symbol loading module input is connected to the symbol detection module input, output be connected to add-compare-select module input;
Owing to retain memory cell is blank when starting, therefore all intersymbol interference afterbody reduction work all need be finished and along with the filling of retaining memory cell is transferred to the parallel judgment feedback decoder gradually, needed decision-feedback pre-filtering module is made amendment for this reason by decision-feedback pre-filtering module when starting beginning.If the retention memory cell to the parallel judgment feedback decoder before the parallel judgment feedback decoder is started working prerequisite is loaded into a correct symbol sebolic addressing, then needed modification can further be cut down to decision-feedback pre-filtering module.Because SSD1/SSD2 must belong to 0 work song group category-B, therefore the preloaded module only need be added one group of 2:1 selector at 0 work song group of 0 state, in start-up course, can utilize to add-compare-the 0 state 0 group input of selected cell imports the idle signal from decision-feedback pre-filtering module, and its number equals the bit wide 12 of 4 dimension symbols.Can predict 8 symbols that ethernet frame begins from SSD1 in theory, so the preloaded operation can reach 8 symbols at most.But the child group except SSD1/SSD2 under all the other symbols is uncertain, need to use 5 level mode decoders of decision-feedback pre-filtering module that it is finished decoding and finishes decoding in the son group by 4 extra dimension branch metric unit, need bigger expense, and judgement brings influence to erroneous frame.Therefore we do not advise that preloaded surpasses 2 above symbols, allow but so do still.Symbol preloaded module then need be added the loading logic at all 8 states when preloaded surpasses 2 symbols, amounting to needs 96 2:1 selectors.
Fig. 3 is existing decision-feedback pre-filtering modular structure schematic block diagram, and fallout predictor wherein can adopt direct type/changing type or mixed type finite impulse response filter structure, is the mixed type finite impulse response filter among the figure.The double mode decision device of 5/3 level works in 3 level modes when training, all work in 5 level modes in all the other situations.Serial input string line output shift register delay line is used to mate the operating lag of mixed type finite impulse response filter.
Fig. 4 is amended decision-feedback pre-filtering module schematic block diagram.Solid line has partly been represented the decision-feedback pre-filtering module of common structure among the figure, adds in the present invention with the part of revising to be indicated by dotted line.In order to connect the correct startup of grid coding decoder after finishing, 3 level decision devices that are applicable to idle condition have been added, switch by control module control with original 5 level decision devices output, symbol detection module and symbol loading module are directly delivered in the output of 3 level decision devices.Original serial input string line output shift register delay line increases the loaded in parallel function in the frame of broken lines, its loading operation and clock close the control that is controlled logic.Its clock will be cut off reducing power consumption under idle pulley, and control module will control to walk abreast and be loaded into decision-feedback pre-filtering module and switch back one group of last under 5 level modes prediction signal in the start-up course.The work that the intersymbol interference afterbody is eliminated can be finished start-up course by the parallel judgment feedback decoder of decision-feedback pre-filtering module seamless branches to the rear portion under the prerequisite of not losing performance in this way.The work of decoder can not be subjected to the influence that decision-feedback pre-filtering module is switched back incorrect symbol in the retention memory cell of the error rate that rises behind 5 level modes and parallel judgment feedback decoder in the whole process.By the operation of preloaded module, then parallel length of packing into can further reduce.The number that reduces equals to retain the symbol numbers of memory cell preloaded.If for example in 1 tap parallel judgment feedback decoder preloaded the SSD1 symbol, in the 2 tap parallel judgment feedback decoders preloaded SSD1/SSD2 symbol then so the delay line of decision-feedback pre-filtering module just do not need to revise.
Claims (7)
1, a kind of gigabit Ethernet low-power consumption joint equalization decoder, it is characterized in that: on existing pre-filtering parallel judgment feedback decoder, add three modules: symbol detection module, symbol loading module and control module, the symbol detection module first input end connects the judgement output of three level decision devices of original decision-feedback pre-filtering module interpolation, second input is connected to the descrambling information output of Physical Coding Sublayer, symbol detection module first output is connected to the control module output, second output is connected to symbol loading module input, be connected to the Physical Coding Sublayer input, symbol detection module will be from three level decision signal transmitting symbol loading modules of decision-feedback pre-filtering module, simultaneously it is finished pre decoding and sends it to Physical Coding Sublayer, if detect this busy signal of three level decision signal then send a message to control module; Control module input bound symbol detection module output, output is connected to whole original and newly-increased module except that himself pre-filtering parallel judgment feedback decoder as control signal, the process that the control decoder starts after receiving busy signal message if pre-filtering parallel judgment feedback decoder is in idle condition, and change standby over to or the carrier extend pattern changes pre-filtering parallel judgment feedback decoder over to idle pulley at present again at Physical Coding Sublayer; Symbol loading module input is connected to the symbol detection module output, output be connected to add-compare-select module input, under the control of control module, the symbol loading module is packed correct data into so that the correct operating state of pre-filtering parallel judgment feedback decoder to be set in the retention memory cell of pre-filtering parallel judgment feedback decoder in start-up course.
2, gigabit Ethernet low-power consumption joint equalization decoder as claimed in claim 1, it is characterized in that: described symbol detection module, processing is from the decision signal of the three level decision devices that added in the original decision-feedback pre-filtering of pre-filtering parallel judgment feedback decoder module, and be used to finish quick pre decoding and judge whether it is in the set of signals of idle signal from the descrambling data of Physical Coding Sublayer, then forwarding it to idle signal for idle signal is encoded to them 4 bits and is sent to Physical Coding Sublayer when insmoding, when the signal that is transmitted on the Ethernet is between ethernet frame, this signal can replace the output of former pre-filtering parallel judgment feedback decoder and fully without any performance loss, when detecting busy signal, then notify the beginning of control module with the sign ethernet frame.
3, gigabit Ethernet low-power consumption joint equalization decoder as claimed in claim 1, it is characterized in that: described control module, the output of accepting symbol detection module is as input, be connected to utilize its setting state self mode of operation with the Physical Coding Sublayer state machine simultaneously, the whole original and interpolation module of its output control pre-filtering parallel judgment feedback decoder except that control module self, in control module,, set the flag bit of idle and normal two patterns for finishing control operation.
4, gigabit Ethernet low-power consumption joint equalization decoder as claimed in claim 3, it is characterized in that: described control module, under idle pulley, control module switches to low-power consumption mode with pre-filtering parallel judgment feedback decoder, the grid coding decoder that it comprised is closed, and pre-filtering this moment parallel judgment feedback decoder is only finished equalization operation to idle signal; Under normal mode, then the grid coding decoder to be opened, pre-filtering this moment parallel judgment feedback decoder is finished the equilibrium and the decode operation of the desired transmission signals of its original design; Under idle pulley, control module remove to be retained incorrect data in the memory cell by the reset/set control circuit of the original retention memory cell of control, and the reset/set control circuit by original adding-compare-selected cell will add-compare-and selected cell places correct initial condition; Under the idle pulley, control module is cut off the clock that does not need working portion that comprises one dimension branch metric unit/four-dimensional metric element/add-compare-selected cell/retention memory cell in the pre-filtering parallel judgment feedback decoder by Clock Gating Technique; When pre-filtering parallel judgment feedback decoder need be when idle pulley changes normal mode of operation over to, control module is by carrying out a start-up course to finish the fast initialization of pre-filtering parallel judgment feedback decoder to symbol loading module and amended pre-filtering module, otherwise, when the Physical Coding Sublayer state machine entered standby mode, then control module also changed idle pulley over to.
5, gigabit Ethernet low-power consumption joint equalization decoder as claimed in claim 1, it is characterized in that: described symbol loading module, to transmit idle characters from symbol detection module as input, and finish under the control of control module under the start-up mode for the fast initialization of retaining memory cell, correct data are substituted in frozen 0 son group, 4 dimension branch metric element output signals under the idle pulley, make decoder be in correct initial condition in order to upgrade the retention memory cell.
6, gigabit Ethernet low-power consumption joint equalization decoder as claimed in claim 1, it is characterized in that: described decision-feedback pre-filtering module, 5 level/double mode decision device of 3 level that the pre-filtering pattern of original decision-feedback pre-filtering module is comprised replaces with independently 5 level decision devices and 3 level decision devices, the latter's judgement directly exports symbol detection module to, under normal mode, the internal feedback of decision-feedback pre-filtering module is with originally identical, based on the output of 5 level decision devices; Under idle pulley, its internal feedback is then exported based on 3 level decision devices, this kind pattern act the feedback pre-decision device work in 3 level modes, and obtain surpassing the performance boost of the theoretical coding gain of pre-filtering parallel judgment feedback decoder, make its output can replace the output of pre-filtering parallel judgment feedback decoder and do not bring performance loss.
7, as claim 1 or 6 described gigabit Ethernet low-power consumption joint equalization decoders, it is characterized in that: described decision-feedback pre-filtering module, the former serial input-serial output delay line that is useful on the coupling output delay is modified to the serial input-serial output delay line with parallel set function, be used under the start-up course under the control module control will the back to intersymbol interference elimination work level and smooth be transferred to thereafter parallel judgment feedback decoder from decision-feedback pre-filtering module, add this process to eliminate the influence of retaining mismark in the memory cell.
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| CN101729189B (en) * | 2008-10-13 | 2012-12-26 | 九旸电子股份有限公司 | Transmitting-receiving device and receiver |
| WO2023245863A1 (en) * | 2022-06-23 | 2023-12-28 | 长鑫存储技术有限公司 | Data receiving circuit, data receiving system, and storage device |
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| CN101729189B (en) * | 2008-10-13 | 2012-12-26 | 九旸电子股份有限公司 | Transmitting-receiving device and receiver |
| WO2023245863A1 (en) * | 2022-06-23 | 2023-12-28 | 长鑫存储技术有限公司 | Data receiving circuit, data receiving system, and storage device |
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