CN109194338A - A kind of polarization code coding method of the more bit process of mixed node - Google Patents
A kind of polarization code coding method of the more bit process of mixed node Download PDFInfo
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
The invention discloses a kind of polarization code coding method of the more bit process of mixed node, include the following steps: 1) configuration decoding parameter；2) maximum order passed through required for decoding is determined；3) type of each decoding stage each node is determined according to vector p；4) preferential 0 Rate Node of hard decision and 1 Rate Node；5) judge mixed node sub-node type and decode；6) decoding according to step 4) and each node of step 5) is as a result, the complete decoding result u:{ u of output1,...uN}.This method can improve the decoding speed of polarization code under the premise of not losing decoding error-correcting performance.
Description
Technical field
The invention belongs to digital communication technology fields, are related to channel decoding technology, especially a kind of to be based on polarization code SSC
More bit decoding method (Multibit- of (Simplified Successive-Cancellation, abbreviation SSC) decoding
Decoding on Simplified Successive-Cancellation, abbreviation MD-SSC), specifically a kind of mixed node
The polarization code coding method of more bit process.
Background technique
The polarization code that Arikan was proposed in 2009 is the forward error correction that the first can achieve channel capacity.Polarization code
Serial counteracting (Successive Cancellation, abbreviation SC) decoding algorithm systematicness it is strong, complexity is low, be convenient for hardware
It realizes, has been the hot spot of research since proposition.Ido Tal and Alexander Vardy is based on SC interpretation method and proposes string
Row offsets list decoding (Successive cancellation list, abbreviation SCL), and decoding performance is very close to most
Maximum-likelihood decoding；Niu Kaiyu Chen Kai proposes the serial counteracting list decoding of cyclic redundancy check auxiliary based on SCL algorithm
(CRC-aided SCL, abbreviation CA-SCL), CA-SCL algorithm greatly improves the decoding error-correcting performance of polarization code, error correction
Performance has been better than existing Turbo code and low density parity check code (Low Density Parity Check Code, letter
Claim LDPC).Improve the error-correcting performance of coding in practical application, the length of code word generally can be more than 2 10 powers, and SC
Decoding algorithm has that the longer decoding latency of code word is higher, causes the throughput of polarization code lower, limits polarization code
Practicability is difficult to promote the use of.In order to reduce the decoding latency of SC algorithm, Alamdar-Yazdi et al. is based on part code concept and mentions
A kind of SSC decoding algorithm is gone out, SSC sorts out 0 Rate Node and 1 Rate Node according to part code, both nodes need not wait
To previous bit decoding result and directly adopt hard decision mode and decode, this method also drops while reducing decoding latency
Low algorithm complexity, however in addition to 0,1 Rate Node is there is also the node that do not classify largely during the decoding of this method,
Especially leaf node is respectively the unfiled node for freezing bit and information bit.In SSC algorithm, these unfiled nodes can be bad
SC algorithm is turned to, biggish decoding latency is still remained.
Summary of the invention:
The purpose of the present invention is in view of the deficiencies of the prior art, and provide a kind of polarization code of more bit process of mixed node
Interpretation method.This method can improve the decoding speed of polarization code under the premise of not losing decoding error-correcting performance.
Realizing the technical solution of the object of the invention is:
A kind of polarization code coding method of the more bit process of mixed node, unlike the prior art, including walks as follows
It is rapid:
1) it configuration decoding parameter: is determined according to the channel-polarization process of polarization code coding stage comprising freezing bit and information
The vector p:{ p of bit position information0,p1,…pN-1, wherein N is the code length of polarization code, piFor the element in vector p, 0≤i≤
N-1, piWhen value is 0, i-th of bit of code word is represented to freeze bit, piWhen value is 1, i-th of bit of code word is represented as letter
Bit is ceased, under awgn channel, the codeword sequence after coding is x:{ x1,x2,...xN-1, the information sequence that decoder receives
For y:{ y0,y1,...,yN-1, the log-likelihood ratio z:{ z of each code word is calculated further according to the information sequence received1,z2,
...zN-1, whereinσ2For the noise figure variance of awgn channel；
2) it determines the maximum order passed through required for decoding: warp required for decoding is determined according to the fixed code length N of polarization code
The maximum order S, S=log crossed2N, arbitrary order is s during definition decoding, and value range is 0≤s≤S, and s rank is corresponding
Number of nodes is m=2s, root node is 0 rank, belongs to 1 rank by 2 child nodes that root node is born, is born by 21 rank child nodes
4 child nodes be 2 ranks, by parity of reasoning until S rank N number of leaf node, each leaf node corresponds to a bit in code word；
3) type of each decoding stage each node is determined according to vector p: determine node type be one from bottom to top
Process, first according to the 2 of N number of leaf node backstepping S-1 rank of S rankS-1A node type, then by S-1 rank backstepping S-2 rank, until
Until 1st rank, a node v equipped with S-1 rank, if 2 leaf nodes that the node derives are to freeze bit, node v is 0
Rate Node；2 leaf nodes derived are information bit, then node v is 1 Rate Node；The 2 leaf nodes difference derived
Freeze bit and an information bit for one, then node v is mixed node, a node u equipped with S-2 rank, if the node
2 child nodes derived are 0 Rate Node, then node u is also 0 Rate Node；If 2 child nodes that the node derives are
1 Rate Node, then node u is also 1 Rate Node；2 child nodes derived are respectively 0 Rate Node and one 1 speed
Rate node, then node u is mixed node；
4) preferential 0 Rate Node of hard decision and 1 Rate Node: if 1 rank node is 0 Rate Node, it includes N/2 it is a
Bit is to freeze bit, bit u0~uN/2Court verdict be directly 0 bit, if some node be 0 Rate Node,
The derivative node of the node is also 0 Rate Node, is to freeze bit by all leaf nodes that the derivative node of 0 rate is born, if section
Point is 1 Rate Node, then the leaf node that node derives downwards always is directly decoded by hard decision, adjudicates foundation are as follows:Wherein αvThe Soft Inform ation vector of child node is passed to for parent node v, Soft Inform ation vector contains this
The log-likelihood ratio of each bit, β in nodevIt is the decoding result vector that child node feeds back to parent node v；
5) judge mixed node sub-node type and decode: if what is encountered during decoding is mixed node, judging
2 sub-node types of its sub-node type, mixed node have 4 kinds of situations, the first is 0 Rate Node and 1 Rate Node, and
Two kinds are 0 Rate Node and mixed node, the third is 1 Rate Node and mixed node, and the 4th kind is 2 mixed nodes, are met
When to 0 Rate Node and 1 Rate Node, operation 4) is thened follow the steps, the judgement operation of mixed node sub-node type is always
Until proceeding to S-1 rank, the mixed node of S-1 rank is then the mixed node that can not be subdivided, and it must have 2 leaf nodes,
Respectively 1 is freezed bit and 1 information bit, can use more bit decoding methods, section for the mixed node c of S-1 rank
Point c has 2 likelihood ratio input values, 2 decoded output values, and decodes output result and there was only 0,0,0,1,1,1,1,0 these four feelings
Condition, therefore mixed node is practical is considered as polynary decoding unit, can accelerate decoding speed, detailed process in this way are as follows:
(1) the parent node input message vector for assuming node c is αc:{z2i-1,z2i}；
(2) judge 2 leaf node u that node c is derived2i-1With u2iBit type, herein can be there are four types of situation:
The first: u2i-1, u2iIt is message bit, then has following decision method:
Second: u2i-1, u2iIt is to freeze bit, then (u2i-1,u2i)=(0,0)；
The third: u2i-1To freeze bit, u2iFor information bit, then u2i-1=0,
4th kind: u2i-1For information bit, u2iTo freeze bit, then u2i=0,
The above operation exports bit u after completing2i-1With u2i；
6) decoding according to step 4) and each node of step 5) is as a result, the complete decoding result u:{ u of output1,...uN}。
This method is the method that more bit decodings are used on unfiled node.
Compared with prior art, the technical program proposes the general of mixed node in the S-1 rank decoding stage of SSC algorithm
It reads, and handles the mixed node in the stage using more bit decoding methods, so that mixed node is by can only once decode 1 ratio
Spy becomes once decoding 2 bits, improves node throughput；And node decoding directly uses log-likelihood ratio information, reduces
Unnecessary information transmitting, reduces method complexity, so that the decoding latency of SSC algorithm obtained further reduction,
Meanwhile the concept of mixed node has further segmented the type of polarization code part code, makes SSC for the interpretation method of new node
Overall complexity be reduced.
This method can improve the decoding speed of polarization code under the premise of not losing decoding error-correcting performance.
Detailed description of the invention
Fig. 1 is method flow schematic diagram in embodiment；
Fig. 2 is that each node decodes flow diagram respectively in embodiment；
Fig. 3-1 is polarization code SC decoded data stream structural schematic diagram in embodiment, and the circular part of dotted line can simplify in figure
For
Node in SSC decoding；
Fig. 3-2 is the SSC decoding tree figure structure schematic representation that the simplification of Fig. 3-1 in embodiment obtains；
Fig. 4 is the SSC decoding node information transmitting schematic diagram that code length is 8 in embodiment；
Fig. 5 is that mixed node structure and LLR value transmit schematic diagram in embodiment；
Fig. 6 be embodiment in SC algorithm, SSC algorithm and MD-SSC algorithm decoding period comparison diagram, wherein SSC algorithm and
MD-SSC algorithm is constrained to one node of a clock cycle processing.
Specific embodiment
The content of present invention is further elaborated with reference to the accompanying drawings and examples, but is not limitation of the invention.
Embodiment:
Referring to Fig.1, a kind of Fig. 2, polarization code coding method of the more bit process of mixed node, includes the following steps:
1) it configuration decoding parameter: is determined according to the channel-polarization process of polarization code coding stage comprising freezing bit and information
The vector p:{ p of bit position information0,p1,…pN-1, wherein N is the code length of polarization code, piFor the element in vector p, 0≤i≤
N-1, piWhen value is 0, i-th of bit of code word is represented to freeze bit, piWhen value is 1, i-th of bit of code word is represented as letter
Bit is ceased, under awgn channel, the codeword sequence after coding is x:{ x1,x2,...xN-1, the information sequence that decoder receives
For y:{ y0,y1,...,yN-1, the log-likelihood ratio z:{ z of each code word is calculated further according to the information sequence received1,z2,
...zN-1, whereinσ2For the noise figure variance of awgn channel, this example access code
A length of 8 polarization code is decoded, and SC decoding data flow structure as shown in figure 3-1, is operated by channel-polarization determine pole first
That changes code freezes bit and the selection of information bit position, i.e. acquisition vector of position p:{ p0,p1,…pN-1, this example determines that p is
{ 0,0,0,0,0,1,1,1 }, therefore in addition to the the 6th, the 7th, the 8th bit is other than information bit, remaining bit is in code word
Freeze bit, the codeword sequence after coding is x:{ 0,0,0,0,0,0,1,1 }, it is transmitted after being modulated through BPSK by awgn channel,
The information sequence that decoder receives is y:{ 1.1253,0.0304,0.9754,0.4366,0.9919,2.2013 ,-
1.4192, -1.5127 }, in order to facilitate hardware realization, need to handle information sequence in log-domain, so taking pair of information sequence
Number likelihood ratio z:{ z1,z2,...zN-1, whereinThe noise figure variance of channel is
0.5, result is z:{ 4.5012,0.1214,3.9014,1.7463,3.9678,8.8053, -5.6768, -6.0508 }；
2) it determines the maximum order passed through required for decoding: warp required for decoding is determined according to the fixed code length N of polarization code
The maximum order S, S=log crossed2N, arbitrary order is s during definition decoding, and value range is 0≤s≤S, and s rank is corresponding
Number of nodes is m=2s, root node is 0 rank, belongs to 1 rank by 2 child nodes that root node is born, is born by 21 rank child nodes
4 child nodes be 2 ranks, by parity of reasoning until S rank N number of leaf node, each leaf node corresponds to a bit in code word,
The code length that this example is chosen is N=8, it may be determined that the maximum order passed through required for decoding is S=3, any during definition decoding
Rank is s, and value range is { 0,1,2,3 }, and the corresponding number of nodes of s rank is m=2s, as shown in figure 3-2,0 rank is root node,
1 rank is 2 child nodes born by root node, and 2 ranks are 4 child nodes born by 21 rank child nodes, and 3 ranks are 2 rank sub- sections
8 leaf nodes that point generates, each leaf node correspond to a bit in code word；
3) type of each decoding stage each node is determined according to vector p: determine node type be one from bottom to top
Process, first according to the 2 of N number of leaf node backstepping S-1 rank of S rankS-1A node type, then by S-1 rank backstepping S-2 rank, until
Until 1st rank, a node v equipped with S-1 rank, if 2 leaf nodes that the node derives are to freeze bit, node v is 0
Rate Node；2 leaf nodes derived are information bit, then node v is 1 Rate Node；The 2 leaf nodes difference derived
Freeze bit and an information bit for one, then node v is mixed node, a node u equipped with S-2 rank, if the node
2 child nodes derived are 0 Rate Node, then node u is also 0 Rate Node；If 2 child nodes that the node derives are
1 Rate Node, then node u is also 1 Rate Node；2 child nodes derived are respectively 0 Rate Node and one 1 speed
Rate node, then node u is mixed node, specially first according to 4 node types of the 8 of 3 ranks 2 ranks of leaf node backstepping, then
By 2 rank backstepping, 1 rank, as shown in figure 4, u0,u1,u2,u3It is to freeze bit, then can determine node wl,wrFor 0 Rate Node, into
And determining node w is 0 Rate Node, u4,u5Respectively freeze bit and information bit, it may be determined that node vlFor mixed node,
u6,u7To be information bit, it may be determined that node vrFor 1 Rate Node；
4) preferential 0 Rate Node of hard decision and 1 Rate Node: if 1 rank node is 0 Rate Node, it includes N/2 it is a
Bit is to freeze bit, bit u0~uN/2Court verdict be directly 0 bit, if some node be 0 Rate Node,
The derivative node of the node is also 0 Rate Node, is to freeze bit by all leaf nodes that the derivative node of 0 rate is born, if section
Point is 1 Rate Node, then the leaf node that node derives downwards always is directly decoded by hard decision, adjudicates foundation are as follows:Wherein αvThe Soft Inform ation vector of child node is passed to for parent node v, Soft Inform ation vector contains this
The log-likelihood ratio of each bit, β in nodevIt is the decoding result vector that child node feeds back to parent node v, specially first processing
0 Rate Node w and 1 Rate Node vr, node w be 0 Rate Node, then it includes 4 bits be to freeze bit, decoding is sentenced
Certainly result is directly 0 bit, node vrFor 1 Rate Node, then the leaf node that node derives downwards always is directly by hard decision
It is decoded, adjudicates foundation are as follows:Wherein αr:{z6,z7It is that node v passes to child node vrPair
Number likelihood ratio information, βr: { 1,1 } is the decoding result vector that child node feeds back to parent node v, i.e., result is u6=1, u7=1；
5) judge mixed node sub-node type and decode: if what is encountered during decoding is mixed node, judging
2 sub-node types of its sub-node type, mixed node have 4 kinds of situations, the first is 0 Rate Node and 1 Rate Node, and
Two kinds are 0 Rate Node and mixed node, the third is 1 Rate Node and mixed node, and the 4th kind is 2 mixed nodes, are met
When to 0 Rate Node and 1 Rate Node, operation 4) is thened follow the steps, the judgement operation of mixed node sub-node type is always
Until proceeding to S-1 rank, the mixed node of S-1 rank is then the mixed node that can not be subdivided, and it must have 2 leaf nodes, point
Not Wei 1 freeze bit and 1 information bit, for the mixed node c of S-1 rank can use more bit decoding methods, node c
There are 2 likelihood ratio input values, 2 decoded output values, and decode output result and there was only 0,0,0,1,1,1,1,0 these four situations,
Therefore mixed node is practical is considered as polynary decoding unit, can accelerate decoding speed, detailed process in this way are as follows:
(1) the parent node input message vector for assuming node c is αc:{z2i-1,z2i}；
(2) judge 2 leaf node u that node c is derived2i-1With u2iBit type, herein can be there are four types of situation:
The first: u2i-1, u2iIt is message bit, then has following decision method:
Second: u2i-1, u2iIt is to freeze bit, then (u2i-1,u2i)=(0,0)；
The third: u2i-1To freeze bit, u2iFor information bit, then u2i-1=0,
4th kind: u2i-1For information bit, u2iTo freeze bit, then u2i=0,
The above operation exports bit u after completing2i-1With u2i, specifically:
Handle mixed node vl, as shown in Figure 5:
Judge node vl2 leaf node u4With u5Bit type, herein can be there are four types of situation；
The first: u4, u5It is message bit, then has following decision method:
Second: u4, u5It is to freeze bit, then (u4,u5)=(0,0)；
The third: u4To freeze bit, u5For information bit, then u4=0；
4th kind: u4For information bit, u5To freeze bit, then u5=0；
V can be determined by vector of position plBelong to the third situation, and z4+z5> 0, it can be deduced that decoding result u4
=0, u5=0；
6) decoding according to step 4) and each node of step 5) is as a result, the complete decoding result u:{ u of output1,...uN,
That is u:{ 0,0,0,0,0,0,1,1 }, it is consistent with code word x, decoding is completed.
Verifying:
As shown in fig. 6, the polarization code that code length is 8 needs 14 clock cycle using SC decoding, when needing 5 using SSC
The clock period then needs 4 clock cycle using MD-SSC.SSC method is compared, this example saves 1 mixing using MD-SSC method
Point carries out more bit decodings, has saved 1 clock cycle；It can be seen that the clock periodicity measurer of MD-SSC method reduction with compared more
The mixed node quantity of spy's decoding is directly proportional, and with the increase of code length, the clock cycle of MD-SSC reduction is also more, decoding latency
Also lower.
Claims (1)
1. a kind of polarization code coding method of the more bit process of mixed node, characterized in that include the following steps:
1) it configuration decoding parameter: according to the channel-polarization process of polarization code coding stage, determines comprising freezing bit and information ratio
The vector of special location informationWherein N is the code length of polarization code, piFor the element in vector p, 0≤i≤
N-1, piWhen value is 0, i-th of bit of code word is represented to freeze bit, piWhen value is 1, i-th of bit of code word is represented as letter
Bit is ceased, under awgn channel, the codeword sequence after coding is x:{ x1,x2,...xN-1, the information sequence that decoder receives
For y:{ y0,y1,...,yN-1, the log-likelihood ratio z:{ z of each code word is calculated further according to the information sequence received1,z2,
...zN-1, whereinσ2For the noise figure variance of awgn channel；
2) it determines the maximum order of process required for decoding: process required for decoding is determined according to the fixed code length N of polarization code
Maximum order S, S=log2N, arbitrary order is s during definition decoding, and value range is 0≤s≤S, the corresponding node of s rank
Quantity is m=2s, root node is 0 rank, belongs to 1 rank by 2 child nodes that root node is born, 4 born by 21 rank child nodes
A child node is 2 ranks, by parity of reasoning until S rank N number of leaf node, each leaf node corresponds to a bit in code word；
3) type of each decoding stage each node: a node v equipped with S-1 rank is determined according to vector p, if the node is derivative
2 leaf nodes out are to freeze bit, then node v is 0 Rate Node；2 leaf nodes derived are information bit, then node
V is 1 Rate Node；2 leaf nodes derived are respectively one and freeze bit and an information bit, then node v is mixing
Node, a node u equipped with S-2 rank, if 2 child nodes that the node derives are 0 Rate Node, node u is also 0 speed
Rate node；If 2 child nodes that the node derives are 1 Rate Node, node u is also 1 Rate Node；2 derived
Child node is respectively 0 Rate Node and 1 Rate Node, then node u is mixed node；
4) preferential 0 Rate Node of hard decision and 1 Rate Node: if 1 rank node is 0 Rate Node, it includes N/2 bit
It is to freeze bit, bit u0~uN/2Court verdict be directly 0 bit, if some node be 0 Rate Node, the section
The derivative node of point is also 0 Rate Node, is to freeze bit by all leaf nodes that the derivative node of 0 rate is born, if node is 1
Rate Node, the then leaf node that node derives downwards always are directly decoded by hard decision, and foundation is adjudicated are as follows:Wherein αvThe Soft Inform ation vector of child node is passed to for parent node v, Soft Inform ation vector contains this
The log-likelihood ratio of each bit, β in nodevIt is the decoding result vector that child node feeds back to parent node v；
5) judge mixed node sub-node type and decode: if what is encountered during decoding is mixed node, judging its son
2 sub-node types of node type, mixed node have 4 kinds of situations, the first is 0 Rate Node and 1 Rate Node, and second
It is 0 Rate Node and mixed node, the third is 1 Rate Node and mixed node, and the 4th kind is 2 mixed nodes, encounters 0 speed
When rate node and 1 Rate Node, operation 4) is thened follow the steps, the judgement operation of mixed node sub-node type will carry out always
Until S-1 rank, the mixed node of S-1 rank is then the mixed node that can not be subdivided, and it must have 2 leaf nodes, respectively 1
Freeze bit and 1 information bit, for the mixed node c of S-1 rank can use more bit decoding methods, node c have 2 seemingly
So than input value, 2 decoded output values, and decodes output result and there was only 0,0,0,1,1,1,1,0 these four situations, therefore mix
Node is practical to be considered as polynary decoding unit, can accelerate decoding speed, detailed process in this way are as follows:
(1) the parent node input message vector for assuming node c is αc:{z2i-1,z2i}；
(2) judge 2 leaf node u that node c is derived2i-1With u2iBit type, herein can be there are four types of situation:
The first: u2i-1, u2iIt is message bit, then has following decision method:
Second: u2i-1, u2iIt is to freeze bit, then (u2i-1,u2i)=(0,0)；
The third: u2i-1To freeze bit, u2iFor information bit, then u2i-1=0,
4th kind: u2i-1For information bit, u2iTo freeze bit, then u2i=0,
The above operation exports bit u after completing2i-1With u2i；
6) decoding according to step 4) and each node of step 5) is as a result, the complete decoding result u:{ u of output1,...uN}。
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