CN114142964B - Method and device for transmitting ultra-short distance data among chips in multi-chip module - Google Patents
Method and device for transmitting ultra-short distance data among chips in multi-chip module Download PDFInfo
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Abstract
The application discloses a method and a device for transmitting ultra-short distance data among chips in a multi-chip module, the method comprises the steps of transmitting related non-return-to-zero code (CNRZ-n) coded string signaling between a sending end and a receiving end through multiple paths of differential signals, wherein n in the CNRZ-n coding refers to the data bit width in the CNRZ-n coding, and the code of the sending end on the string signaling is a matrix of the CNRZ-n coding, a common mode voltage Vcm between the sending end and the receiving end and n bit data D 0 ～D n Multiplying the formed matrixes to obtain the encoded n+1 bit chord signaling; the decoding of the chord signaling by the receiving end is to multiply the inversion matrix of the n+1 bit chord signaling and the CNRZ-n coding matrix to restore the n bit data D sent by the sending end 0 ～D n . The application can realize a high-speed and energy-saving chip-to-chip link, has high sensitivity and pin efficiency, lower requirement on balanced complexity and lower power consumption during transmission.
Description
Technical Field
The application belongs to the technical field of integrated circuit design and data transmission, and particularly relates to an ultra-short distance data transmission method and device between chips in a multi-chip module.
Background
High-speed data transmission is one of key technologies of high-performance computers, data centers, 5G, intelligent driving and other applications, and bandwidth, power consumption and delay indexes of the high-speed data transmission are bottlenecks of development of high-end chips such as CPU, GPU, DPS, AI and exchange.
FIG. 1 shows a typical multi-module (MCM) chip interconnection scheme, which integrates core particles with different functions onto the same substrate, so that the problems of limited illumination size, low yield, long design period and high cost during large-size chip design are avoided, and the overall performance of the high-end chip is further improved.
Typical data transmission currently has two main classifications of serial and parallel, and fig. 2 shows the development trend of different types in the two main classifications. Single-ended binary pulse amplitude modulation (PAM 2-SES) has very good pin efficiency (PEPAM 2, ses=1, one bit of data per line: 1bit/1 wire), but this signal transmission method exhibits high sensitivity to Common Mode Noise (CMN) and signal crosstalk (XTALK) and simultaneously generates switching noise (SSN). The differential transmission mode (1 bit/2 wire) can well solve the problem of common mode noise, but the lower pin efficiency can reduce the throughput of the link. To further increase throughput, the industry has turned to the use of higher order PAMs, such as PAM4 and PAM8.PAM4 has been successfully used in the design of 56Gb/s and 112Gb/s links. PAM4 and PAM8 have a higher sensitivity to intersymbol interference, especially in the reflected form, to signal crosstalk, since small transitions are disturbed by large transitions (and also for reflections).
Disclosure of Invention
The application aims to solve the technical problems: aiming at the problems in the prior art, the ultra-short distance data transmission method and device between chips in the multi-chip module are provided. The present application provides a USR (ultra short distance) link based on a correlated non-return to zero (CNRZ) signaling scheme (called chordal signaling) that transmits n bits (nb/n+1w) over n+1 wires, thereby enabling a very high speed and very energy efficient chip-to-chip link for MCM applications. The chord signaling has the same sensitivity as PAM2-DS and provides higher pin efficiency. Compared with PAM4 and PAM8, chord signaling requires less equalization complexity and power consumption in transmission. The method does not lose indexes such as channel crosstalk, common mode noise, synchronous switching noise, intersymbol interference and the like, and does not need an analog-to-digital converter (ADC), so that higher pin efficiency is finally realized.
In order to solve the technical problems, the application adopts the following technical scheme:
an ultra-short distance data transmission method between chips in a multi-chip module comprises the steps of transmitting CNRZ-n coded string signaling between a transmitting end and a receiving end through multipath differential signals, wherein n in the CNRZ-n coding refers to the data bit width in the CNRZ-n coding, and the code of the transmitting end on the string signaling is to code a CNRZ-n coding matrix, a common mode voltage Vcm between the transmitting end and the receiving end and n bit data D 0 ～D n Multiplying the formed matrixes to obtain the encoded n+1 bit chord signaling; the decoding of the chord signaling by the receiving end is to multiply the inversion matrix of the n+1 bit chord signaling and the CNRZ-n coding matrix to restore the n bit data D sent by the sending end 0 ～D n 。
Optionally, the magnitude of the common-mode voltage Vcm between the transmitting end and the receiving end satisfies:
in the above, W i The i-th bit data obtained after the encoding.
Optionally, the CNRZ-n code refers to CNRZ-7 code, and the function expression of the sending end for chord signaling code is:
in the above, CNRZ 7 Is a CNRZ-7 coding matrix, vcm is the common mode voltage of the output end of the transmitting end, D 0 ～D 6 For 7-bit data to be encoded, w 0 ～w 7 The 8-bit data obtained after the encoding is obtained.
Optionally, the functional expression of decoding the chord signaling by the receiving end is:
in the above, vcm is the common-mode voltage between the transmitting end and the receiving end, D 0 ～D 6 For 7-bit data obtained after decoding, CNRZ 7 T An inversion matrix of the CNRZ-7 coding matrix.
Alternatively, the CNRZ-7 encoding matrix CNRZ 7 The functional expression of (2) is:
optionally, the transmitting end side encodes a CNRZ-n encoding matrix, a common mode voltage Vcm of the transmitting end output end and n-bit data D 0 ～D n When the formed matrix is multiplied to obtain the n+1 bit chord signaling obtained after coding, the transmitting end uses an encoder for each column of the CNRZ-n coding matrix, and each row is used as a decoder of a sub-channel corresponding receiving end.
Optionally, the transmitting end side encodes a CNRZ-n encoding matrix, a common mode voltage Vcm of the transmitting end output end and n-bit data D 0 ～D n When the formed matrix is multiplied to obtain the encoded n+1 bit chord signaling, the transmitting end adopts a voltage mode driving mode in each preset unit interval UI, and drives the encoder and simultaneously drives n bit data D 0 ～D n Encoded and transmitted.
Optionally, the receiving end side multiplies the string signaling with n+1 bits and the inversion matrix of the CNRZ-n coding matrix to restore the n-bit data D sent by the sending end 0 ～D n When n+1 conductors are connected to n multiple-input comparator circuits, the input stage of each comparator circuit performs an inverse linear transformation to achieve linear combination, producing n equal-eye binary data.
In addition, the embodiment also provides an ultra-short distance data transmission device between chips in the multi-chip module, which comprises a transmitter, a receiver and a coding and decoding transmission module positioned between the transmitter and the receiver, wherein the coding and decoding transmission module consists of an encoder, a decoder and a plurality of transmission lines positioned between the encoder and the decoder, and the coding and decoding transmission module is programmed or configured to execute the steps of the ultra-short distance data transmission method between chips in the multi-chip module.
In addition, the embodiment also provides a multi-core computing device, which comprises a multi-core processor and a memory which are connected with each other, and is characterized in that the multi-core processor is programmed or configured to execute the steps of the ultra-short distance data transmission method among chips in the multi-chip module.
Compared with the prior art, the application has the following advantages: the present application provides a USR (ultra short distance) link based on a correlated non-return to zero (CNRZ) signaling scheme (called chordal signaling) that transmits n bits (nb/n+1w) over n+1 wires, thereby enabling a very high speed and very energy efficient chip-to-chip link for MCM applications. The chord signaling has the same sensitivity as PAM2-DS and provides higher pin efficiency. Compared with PAM4 and PAM8, the chord signaling has lower requirement on equalization complexity, lower power consumption in transmission, no analog-to-digital converter (ADC) is needed, and higher pin efficiency is finally realized.
Drawings
Fig. 1 illustrates a typical prior art multi-module (MCM) chip interconnect scheme.
Fig. 2 is a development trend chart of the data transmission mode of the prior serial and parallel two main classifications.
FIG. 3 is a schematic diagram of a basic flow of a method according to an embodiment of the present application.
Fig. 4 is a diagram of the simplest coding transmission scheme of n=1 (CNRZ-1) in the embodiment of the present application.
Fig. 5 is a coding transmission schematic diagram of n=7 (CNRZ-7) in the embodiment of the present application.
FIG. 6 is an example of SST encoding logic in an embodiment of the application.
Fig. 7 is a schematic diagram of a multi-input comparator in an embodiment of the application.
FIG. 8 is a diagram of a 7-bit data D in an embodiment of the application 0 ～D 6 And outputting an eye diagram simulation result diagram.
Detailed Description
As shown in fig. 3, the present embodiment provides an ultra-short distance data transmission method between chips in a multi-chip module, which includes transmitting a CNRZ-n encoded string signaling between a transmitting end and a receiving end through multiple differential signals, wherein n in the CNRZ-n encoding refers to a data bit width in the CNRZ-n encoding, and the encoding of the string signaling by the transmitting end is to encode the CNRZ-n encoding matrix, a common-mode voltage Vcm between the transmitting end and the receiving end, and n-bit data D 0 ～D n Multiplying the formed matrixes to obtain the encoded n+1 bit chord signaling; the decoding of the chord signaling by the receiving end is to multiply the inversion matrix of the n+1 bit chord signaling and the CNRZ-n coding matrix to restore the n bit data D sent by the sending end 0 ～D n . In order to solve the problem of low pin efficiency caused by differential transmission (DS), the embodiment adopts a CNRZ-n signaling transmission method with coding characteristics, so that the pin efficiency of a link is improved under the condition of maintaining indexes such as channel crosstalk, common mode noise, synchronous switching noise, intersymbol interference and the like in differential transmission.
CNRZ-n is essentially a generalization of Differential Signaling (DS), one of the transmission modes of chordal signaling. In this embodiment, the main attributes of chord signaling using CNRZ-n coding are as follows:
1) nb/(n+1) w, namely: n+1 channels transmit n bits of data.
2) The magnitude of the common-mode voltage Vcm between the transmitting end and the receiving end satisfies:
in the above, W i The i-th bit data obtained after the encoding. By introducing a common mode voltage Vcm between the transmitting and receiving ends, the advantages of differential transmission are maintained.
3) The input and output of a chordal signaling based link is always binary. Although the number of signal levels on each line may exceed 2 or even more. The binary signal generated after decoding at the receiving end saves the requirement of a high-resolution ADC and can be communicated after a simple sler circuit is utilized.
Wherein n in the CNRZ-n coding can be selected to take on value according to the requirement.
Fig. 4 shows the simplest link topology of n=1 (CNRZ-1) and the corresponding mathematical model, which is the simplest coding form of chordal signaling, for coding 1bit data for 1b/2w transmission. In its simplest form, consider a PAM2-DS link. In order to convert single bits into differential values, the following conversion is performed at encoding:
in the above formula, D is 1-bit binary data to be transmitted of n=1 (CNRZ-1). Furthermore, the total gain usage of the encoder and decoderThe factors are normalized. The single-ended to differential transformation is based on a Walsh-Hadamard matrix H, where H -1 ＝H T =h. This property means that the original binary data can be recovered at the receiver end using the conversion matrix of the coding matrix, i.e.:
for common differential signaling, voltage mode or current mode drivers are often used for the transmitter to send data, while the receiver front-end may use differential amplifiers to extract the binary data.
To achieve a more efficient chordal signaling scheme, higher order encoding and decoding matrices are used. Fig. 5 shows the link topology of n=7 (CNRZ-7) and the corresponding mathematical model in this embodiment, and the same orthogonal multi-line signaling is adopted, so that 7b/8w transmission is finally completed, and the pin efficiency is improved by 175%. The corresponding CNRZ-7 link transmits 7 bits of data in parallel on 8 lines. At this time, CNRZ-n coding refers to CNRZ-7 coding, and the function expression of the sending end for string signaling coding is:
in the above, CNRZ 7 Is a CNRZ-7 coding matrix, vcm is the common mode voltage of the output end of the transmitting end, D 0 ～D 6 For 7-bit data to be encoded, w 0 ～w 7 The 8-bit data obtained after the encoding is obtained. Correspondingly, the function expression of decoding the chord signaling by the receiving end is as follows:
in the above, vcm is the common-mode voltage between the transmitting end and the receiving end, D 0 ～D 6 For 7-bit data obtained after decoding, CNRZ 7 T An inversion matrix of the CNRZ-7 coding matrix. In the link topology of n=7 (CNRZ-7) and corresponding mathematical model, CNRZ-7 encodes the matrix CNRZ 7 The functional expression of (2) is:
in this embodiment, the transmitting end side encodes a CNRZ-n encoding matrix, a common-mode voltage Vcm of the transmitting end output end, and n-bit data D 0 ～D n When the formed matrix is multiplied to obtain the encoded n+1 bit chord signaling, the transmission is carried outEach column of the CNRZ-n encoding matrix is encoded with one encoder (voltage-modulo drive: w 0-w 7), and each row serves as one decoder for one subchannel for the receiving end.
As shown in fig. 6, the transmitting end side code in this embodiment is to encode CNRZ-n code matrix, common mode voltage Vcm of the transmitting end output end, and n-bit data D 0 ～D n When the formed matrix is multiplied to obtain the encoded n+1 bit chord signaling, the transmitting end adopts a voltage mode driving mode in each preset unit interval UI, and drives the encoder and simultaneously drives n bit data D 0 ～D n Encoded and transmitted, and fig. 6 shows a case where 7bit data (D 0 ～D 6 ) Encoding to 8 lines (w 0 ～w 7 ) And (3) upper part. For each conductor (each column of the CNRZ-7 matrix) the correct input bit will be selected, weighted for the output driver. The combined signal will be placed on the corresponding conductor at the target output impedance. In this embodiment, the receiving end multiplies the n+1 bit string signaling and the inversion matrix of the CNRZ-n coding matrix to restore the n bit data D sent by the sending end 0 ～D n When n+1 conductors are connected to n multiple-input comparator circuits, the input stage of each comparator circuit performs an inverse linear transformation to achieve linear combination, producing n equal-eye binary data. Fig. 7 shows eight conductors connected to seven multi-input comparator circuits, the input stages of each of which perform an inverse linear transformation to achieve linear combination, producing seven equal eye binary data. The example shown in fig. 7 implements the first row (subchannel number 0) of the CNRZ-7 matrix, whose functional expression is:
V OUT,0 ＝[w 0 +w 1 +w 2 +w 3 -w 4 -w 5 -w 6 -w 7 ]×g m R D ， (7)
in the above, V OUT,0 To output data D 0 Is a differential signal, w i Representing the signal on channel i, R D Is the load resistance g m Is the transconductance of each transistor of the differential pair in fig. 7. The output of each multiple-input comparator circuit is binary, although there are multiple levels on the conductors. Thus (2)Communication is enabled through the slicing circuit. Although CNRZ-7 increases pin efficiency from 1/2 of the double-ended differential to 7/8 of CNRZ-7, it does not exhibit excessive sensitivity to intersymbol interference, and maintains good immunity to common mode noise and signal crosstalk. In this embodiment, the linear and orthogonal transforms on which the signaling is based are encoded and driven in the transmitter (see fig. 6), and decoded in the Multiple Input Comparator (MIC) of the receiver (see fig. 7), which reduces sensitivity to crosstalk and other noise sources while maintaining high data rates and pin efficiency.
It is generally believed that signaling methods with more levels exhibit higher sensitivity to ISI. ISI sensitivity is directly related to the number of signal levels at the input of a slicer or decision circuit, as opposed to the number of levels on the transmission line. Consider a channel with an impulse response denoted by h (t). If c i Is from having N C Data symbols selected in the symbol set:
c i ∈c＝{c j :j＝0,…,N C -1}， (8)
in the above, N C Is N C Total number of data symbols of the symbol set.
Then, after passing through the ideal multiple-input comparator circuit, the transmitted signal can be described as:
in the above formula, s (t) is a transmitted signal, c i Is from having N C Data symbols selected in the symbol set, P u (T) represents a rectangular pulse of width T, T being the application, T being the symbol duration (corresponding to one unit interval UI).
Thus, the received signal will be the result of a discrete convolution of the transmitted signal with the transfer function:
H T,i(t) is defined as:
in the above formula, r (t) is a received signal, H (t) is a transfer function, H T,i(t) Is a fading term.
Assuming that the received signal t e [0, T), there are:
in the above, c 0 Is from having N C The first data symbol selected in the symbol set, H T,0(t) The dominant fading term, while the second factor is the fading coefficient related to intersymbol interference, namely:
wherein H is T,i(t) /H T,0(t) Is a fading factor due to channel ISI, and c i /c 0 Is due to intersymbol interference sensitivity caused by the chordal signaling method. The intersymbol interference ratio of the coding scheme is defined as:
in the above, I R The inter-symbol interference ratio (abbreviated as interference ratio) of the coding scheme, c', c is arbitrary data. Then in the worst case of intersymbol interference c i /c 0 Equal to interference ratio I R Thus, there are:
it is important to note that in addition to channel loss, i.e. H T,i(t) /H T,0(t) Besides, there is a second factor that exacerbates the sensitivity to intersymbol interference: interference ratio I of coding scheme as defined above R . If the distances from all the data symbols to the receiving end are equal, I R =1, and there is no additional sensitivity to intersymbol interference. The single-ended and differential PAM2 signaling methods both meet I R =1. However, in PAM4 signaling, I R =3 (see table 1), which explains why this signaling method exhibits a higher sensitivity to intersymbol interference and therefore requires more complex equalization.
Table 1: the main characteristics of different signaling methods.
Analysis here shows that the choice of signaling method directly affects the link budget, and that a well-designed signaling scheme helps to avoid unnecessary eye-open losses. As with the chord signaling, the signal delivered to the slicer is binary, ir=1, similar to PAM2 signaling. Therefore, it does not exhibit any excessively high ISI sensitivity. In this embodiment, the width of the eye can be calculated using (15). At time interval [0, T]Where r (t) =0. If we call these two time points t L (left side of eye) and t R (right side of the eye), then the eye width is:
t eye,width ＝t R -t L ， (16)
in the above, t eye,width Representing the eye width (eye width).
As is evident from (15) and (16), when IR>At 1, the eye width decreases faster. The same analysis can be performed to show that eye height also decreases in proportion to IR, and table 1 compares ISI sensitivity and pin efficiency for several main signaling methods. In this embodiment, the foregoing method is simulated by a circuit, and the input is PRBS7 pseudo-randomCode, adding channel extracted parameter (channel attenuation about 7.5 dB), and after equalization, D of 7-bit high-speed data 0 ～D 6 The simulation results of the output eye patterns are shown in FIG. 8, respectively, where (a) in FIG. 8 is D 0 (b) is D 1 (c) is D 2 (D) is D 3 (e) is D 4 (f) is D 5 (g) is D 6 . As can be seen from fig. 8, the decoded signal is entirely a binary NRZ signal.
In addition, the embodiment also provides an ultra-short distance data transmission device between chips in the multi-chip module, which comprises a transmitter, a receiver and a coding and decoding transmission module positioned between the transmitter and the receiver, wherein the coding and decoding transmission module consists of an encoder, a decoder and a plurality of transmission lines positioned between the encoder and the decoder, and the coding and decoding transmission module is programmed or configured to execute the steps of the ultra-short distance data transmission method between chips in the multi-chip module.
In addition, the embodiment also provides a multi-core computing device, which comprises a multi-core processor and a memory which are connected with each other, wherein the multi-core processor is programmed or configured to execute the steps of the ultra-short distance data transmission method between chips in the multi-chip module.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present application, and the protection scope of the present application is not limited to the above examples, and all technical solutions belonging to the concept of the present application belong to the protection scope of the present application. It should be noted that modifications and adaptations to the present application may occur to one skilled in the art without departing from the principles of the present application and are intended to be within the scope of the present application.
Claims (7)
1. The ultra-short distance data transmission method between chips in a multi-chip module is characterized by comprising the steps of transmitting CNRZ-n coded string signaling between a transmitting end and a receiving end through multipath differential signals, wherein n in the CNRZ-n coding refers to the data bit width in the CNRZ-n coding, and the code of the transmitting end on the string signaling is a common mode voltage between a CNRZ-n coding matrix, the transmitting end and the receiving endVcmN-bit dataD 0 ~D n Multiplying the formed matrixes to obtain the encoded n+1 bit chord signaling; receiving terminalDecoding the chord signaling is to multiply the inversion matrix of the n+1 bit chord signaling and the CNRZ-n coding matrix to restore the n bit data sent by the sending endD 0 ~D n Common mode voltage between the transmitting end and the receiving endVcmThe size of (2) satisfies the following:
in the above-mentioned method, the step of,W i the i bit data obtained after the encoding is used; the CNRZ-n code refers to CNRZ-7 code, and the function expression of the sending end for the chord signaling code is as follows:
in the above-mentioned method, the step of,for the CNRZ-7 encoding matrix,Vcmfor the common mode voltage between the transmitting and receiving ends,D 0 ~D 6 for 7 bits of data to be encoded,W 0 ~W 7 8 bits of data obtained after encoding; CNRZ-7 coding matrix->The functional expression of (2) is:
。
2. the method for transmitting ultra-short distance data between chips in a multi-chip module according to claim 1, wherein the function expression of decoding chord signaling by the receiving end is:
in the above-mentioned method, the step of,Vcmfor the common mode voltage between the transmitting and receiving ends,D 0 ~D 6 in order to obtain 7-bit data after decoding,an inversion matrix of the CNRZ-7 coding matrix.
3. The method for transmitting ultra-short distance data between chips in a multi-chip module according to claim 1, wherein said transmitting side codes a CNRZ-n code matrix, a common-mode voltage between a transmitting side and a receiving sideVcmN-bit dataD 0 ~D n When the formed matrix is multiplied to obtain the n+1 bit chord signaling obtained after coding, the transmitting end uses an encoder for each column of the CNRZ-n coding matrix, and each row is used as a decoder of a sub-channel corresponding receiving end.
4. The method for transmitting ultra-short distance data between chips in a multi-chip module according to claim 3, wherein said transmitting side codes a CNRZ-n code matrix, a common-mode voltage between a transmitting side and a receiving sideVcmN-bit dataD 0 ~D n When the formed matrix is multiplied to obtain the encoded n+1 bit string signaling, the transmitting end adopts a voltage mode driving mode in each preset unit interval UI, and drives the encoder and simultaneously drives the n bit dataD 0 ~D n Encoded and transmitted.
5. The method for transmitting ultra-short distance data between chips in a multi-chip module according to claim 4, wherein said receiving end side multiplies n+1 bit chord signaling and inversion matrix of CNRZ-n coding matrix to restore n bit data transmitted by transmitting endD 0 ~D n When n+1 conductors are connected to n multiple-input comparator circuits, the input stage of each comparator circuit performs an inverse linear transformation to achieve linear combination, producing n equal-eye binary data.
6. An apparatus for transmitting ultra-short distance data between chips in a multi-chip module, comprising a transmitter, a receiver, and a codec transmission module located between the transmitter and the receiver, the codec transmission module being comprised of an encoder, a decoder, and a plurality of transmission lines located between the encoder and the decoder, the codec transmission module being programmed or configured to perform the steps of the method for transmitting ultra-short distance data between chips in a multi-chip module according to any one of claims 1 to 5.
7. A multi-core computing device comprising a multi-core processor and a memory interconnected, wherein the multi-core processor is programmed or configured to perform the steps of the inter-chip ultrashort distance data transmission method in a multi-chip module of any one of claims 1-5.
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| CN112838999A (en) * | 2019-11-25 | 2021-05-25 | 上海华为技术有限公司 | Signal modulation method and device |
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| CN105993151A (en) * | 2014-02-02 | 2016-10-05 | 康杜实验室公司 | Method and apparatus for low power chip-to-chip communications with constrained ISI ratio |
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