CN114142964A

CN114142964A - Ultra-short distance data transmission method and device between chips in multi-chip module

Info

Publication number: CN114142964A
Application number: CN202111415637.3A
Authority: CN
Inventors: 赖明澈; 张庚; 吕方旭; 郭凯乐; 许超龙; 庞征斌; 常俊胜; 齐星云; 陆平静; 曹继军; 王强; 罗章; 李晋文; 廖湘科
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2021-11-25
Filing date: 2021-11-25
Publication date: 2022-03-04
Anticipated expiration: 2041-11-25
Also published as: CN114142964B

Abstract

The invention discloses a method and a device for transmitting ultra-short distance data between chips in a multi-chip module, wherein the method comprises the step of transmitting string signaling of related non-return-to-zero (CNRZ-n) codes between a transmitting end and a receiving end through a multi-path differential signal, wherein n in the CNRZ-n codes refers to the data bit width in the CNRZ-n codes, and the codes of the transmitting end to the string signaling are that a CNRZ-n code matrix, common-mode voltage Vcm between the transmitting end and the receiving end and n bit data D are transmitted₀～D_nMultiplying the formed matrix to obtain n + 1bit string signaling obtained after coding; the receiving end decodes the string signaling into n bit data D which is obtained by multiplying the string signaling of n + 1bit and the inverse matrix of the CNRZ-n coding matrix and is transmitted by the transmitting end₀～D_n. The invention can realize high-speed and energy-saving chip-to-chip link, has high sensitivity and pin efficiency, lower requirement on balance complexity and lower power consumption during transmission.

Description

Ultra-short distance data transmission method and device between chips in multi-chip module

Technical Field

The invention belongs to the technical field of integrated circuit design and data transmission, and particularly relates to a method and a device for ultra-short distance data transmission among chips in a multi-chip module.

Background

High-speed data transmission is one of key technologies of applications such as high-performance computers, data centers, 5G and intelligent driving, and bandwidth, power consumption and delay indexes of the high-speed data transmission are bottlenecks in development of high-end chips such as a CPU (central processing unit), a GPU (graphic processing unit), a DPS (data processing system), an AI (analog-to-digital converter) and exchange.

Fig. 1 shows a typical multi-module (MCM) chip interconnection scheme, which integrates core particles with different functions on the same substrate, thereby avoiding the problems of limited illumination size, low yield, long design cycle, and high cost in large-size chip design, and further improving the overall performance of high-end chips.

The current typical data transmission has two categories of serial and parallel, and fig. 2 shows the development trend of different types in the two categories. Single-ended binary pulse amplitude modulation (PAM2-SES) has very good pin efficiency (PEPAM2, SES 1, one bit of data per line: 1bit/1wire), but this signal transmission method exhibits high sensitivity to Common Mode Noise (CMN) and signal crosstalk (XTALK), and simultaneously generates switching noise (SSN). The problem of common mode noise can be well solved by adopting a differential transmission mode (1bit/2wire), but the throughput of a link can be reduced due to the lower pin efficiency of the differential transmission mode. To further improve throughput, the industry has turned to using higher order PAMs, such as PAM4 and PAM 8. PAM4 has been successfully used in the design of 56Gb/s and 112Gb/s links. PAM4 and PAM8 are more sensitive to intersymbol interference, and in particular in the reflective form, to signal crosstalk, since small transitions are disturbed by large transitions (and so on for reflections).

Disclosure of Invention

The technical problems to be solved by the invention are as follows: in view of the above problems in the prior art, a method and an apparatus for transmitting data with an ultra-short distance between chips in a multi-chip module are provided. The invention provides a USR (ultra short distance) link based on a correlated non return to zero (CNRZ) signaling transmission scheme (called chord signaling), which transmits n bits (nb/n +1w) through n +1 wires, thereby enabling a very high-speed and very energy-saving chip-to-chip link for MCM applications. Chordal signaling has the same sensitivity as PAM2-DS and provides higher pin efficiency. Compared with PAM4 and PAM8, chord signaling has lower requirements on equalization complexity and lower power consumption during transmission. The indexes such as channel crosstalk, common mode noise, synchronous switching noise and intersymbol interference are not lost, an analog-to-digital converter (ADC) is not needed, and high pin efficiency is finally achieved.

In order to solve the technical problems, the invention adopts the technical scheme that:

a method for transmitting ultra-short distance data between chips in a multi-chip module comprises transmitting string signaling of CNRZ-n codes between a transmitting end and a receiving end through multi-path differential signals, wherein n in the CNRZ-n codes refers to data bit width in the CNRZ-n codes, and the encoding of the transmitting end to the string signaling is that a CNRZ-n code matrix, common mode voltage Vcm between the transmitting end and the receiving end and n bit data D are encoded₀～D_nIs composed ofMatrix multiplication is carried out to obtain n + 1bit string signaling obtained after coding; the receiving end decodes the string signaling into n bit data D which is obtained by multiplying the string signaling of n + 1bit and the inverse matrix of the CNRZ-n coding matrix and is transmitted by the transmitting end₀～D_n。

Optionally, the magnitude of the common-mode voltage Vcm between the transmitting end and the receiving end satisfies:

in the above formula, W_iThe coded data is the ith data.

Optionally, the CNRZ-n coding refers to CNRZ-7 coding, and a functional expression of the sending end to the string signaling coding is as follows:

in the above formula, CNRZ₇Is a CNRZ-7 coding matrix, Vcm is the common-mode voltage of the output end of a sending end, D₀～D₆For 7 bits of data to be encoded, w₀～w₇The 8-bit data obtained after encoding.

Optionally, the functional expression of the receiving end for decoding the chord signaling is:

in the above formula, Vcm is the common mode voltage between the transmitting terminal and the receiving terminal, D₀～D₆For the decoded 7-bit data, CNRZ₇ ^TIs an inverse matrix of the CNRZ-7 encoding matrix.

Alternatively, the CNRZ-7 encoding matrix CNRZ₇The functional expression of (a) is:

optionally, the transmitting end side is encoded by using a CNRZ-n encoding matrix, a common mode voltage Vcm at the output end of the transmitting end and n bit data D₀～D_nWhen the formed matrix is multiplied to obtain n + 1bit string signaling obtained after coding, a coder is used by a sending end for each column of the CNRZ-n coding matrix, and each row is used as a decoder of a sub-channel corresponding to a receiving end.

Optionally, the transmitting end side is encoded by using a CNRZ-n encoding matrix, a common mode voltage Vcm at the output end of the transmitting end and n bit data D₀～D_nWhen n + 1bit string signaling obtained after the formed matrix multiplication is coded, a sending end adopts a voltage mode driving mode in each preset unit interval UI, and the encoder is driven and simultaneously n bit data D are also subjected to n bit data D₀～D_nEncoded and transmitted.

Optionally, the receiving end multiplies the n +1 string signaling and the inverse matrix of the CNRZ-n coding matrix to restore the n-bit data D transmitted by the transmitting end₀～D_nAt this time, n +1 wires are connected to n multi-input comparator circuits, each of which has an input stage that performs inverse linear transformation to realize linear combination, generating n equal-eye binary data.

In addition, the present embodiment further provides an apparatus for transmitting data in an ultra-short distance between chips in a multi-chip module, which includes a transmitter, a receiver, and a codec transmission module located between the transmitter and the receiver, where the codec transmission module includes an encoder, a decoder, and a plurality of transmission lines located between the encoder and the decoder, and the codec transmission module is programmed or configured to perform the steps of the method for transmitting data in an ultra-short distance between chips in a multi-chip module.

In addition, the present embodiment also provides a multi-core computing device, including a multi-core processor and a memory connected to each other, wherein the multi-core processor is programmed or configured to execute the steps of the method for transmitting data in an ultra-short distance between chips in the multi-chip module.

Compared with the prior art, the invention has the following advantages: the invention provides a USR (ultra short distance) link based on a correlated non return to zero (CNRZ) signaling transmission scheme (called chord signaling), which transmits n bits (nb/n +1w) through n +1 wires, thereby enabling a very high-speed and very energy-saving chip-to-chip link for MCM applications. Chordal signaling has the same sensitivity as PAM2-DS and provides higher pin efficiency. Compared with PAM4 and PAM8, chord signaling has lower requirements on equalization complexity, lower power consumption during transmission, no need of an analog-to-digital converter (ADC), and finally higher pin efficiency is realized.

Drawings

Fig. 1 illustrates a typical multi-module (MCM) chip interconnection scheme.

Fig. 2 is a development trend diagram of a data transmission method of the prior serial and parallel classification.

FIG. 3 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.

Fig. 4 is a simplest encoding transmission schematic diagram of n-1 (CNRZ-1) in the embodiment of the present invention.

Fig. 5 is a schematic diagram of coded transmission of n-7 (CNRZ-7) in the embodiment of the present invention.

Figure 6 is an example of SST encoding logic in an embodiment of the invention.

Fig. 7 is an example of a multi-input comparator in an embodiment of the present invention.

FIG. 8 shows D of 7-bit data in the embodiment of the present invention₀～D₆And outputting an eye pattern simulation result diagram.

Detailed Description

As shown in fig. 3, this embodiment provides a method for transmitting ultra-short distance data between chips in a multi-chip module, which includes transmitting string signaling of CNRZ-n codes between a transmitting end and a receiving end through multiple paths of differential signals, where n in the CNRZ-n codes refers to a data bit width in the CNRZ-n codes, and the coding of the transmitting end on the string signaling is to encode a CNRZ-n code matrix, a common mode voltage Vcm between the transmitting end and the receiving end, and n-bit data D₀～D_nMultiplying the formed matrix to obtain n + 1bit string signaling obtained after coding; the receiving end decodes the string signaling into n bit data D which is obtained by multiplying the string signaling of n + 1bit and the inverse matrix of the CNRZ-n coding matrix and is transmitted by the transmitting end₀～D_n. In order to solve the problem of low pin efficiency caused by differential transmission (DS), the embodiment adopts a CNRZ-n signaling transmission method with coding characteristics, so as to improve the pin efficiency of the link while maintaining indexes such as channel crosstalk, common mode noise, synchronous switching noise and intersymbol interference in differential transmission.

CNRZ-n is essentially a generalization of Differential Signaling (DS), and is one of the transmission modes of string signaling. In this embodiment, the chord signaling using CNRZ-n coding has the following main attributes:

1) nb/(n +1) w, i.e.: n +1 channels transmit n-bit data.

2) The size of the common-mode voltage Vcm between the sending end and the receiving end meets the following requirements:

in the above formula, W_iThe coded data is the ith data. By introducing a common-mode voltage Vcm between the transmitting terminal and the receiving terminal, the advantages of differential transmission are maintained.

3) The input and output of a link based on chord signaling is always binary. Although the number of signal levels on each line may exceed 2 or even more. The binary signal generated after decoding at the receiving end saves the requirement of high-resolution ADC, and communication can be realized by using a simple slicer circuit.

Wherein, n in the CNRZ-n code can be selected to be valued according to the requirement.

Fig. 4 shows the simplest link topology and the corresponding mathematical model of n ═ 1(CNRZ-1), which is the simplest coding form of chordal signaling, and is used for coding 1-bit data to realize 1b/2w transmission. In its simplest form, consider a PAM2-DS link. To convert a single-ended bit into a differential value, the following conversion is performed at the time of encoding:

in the above formula, D is n1-bit binary data to be transmitted of 1 (CNRZ-1). In addition, the total gain usage of the encoder and decoder

The factors are normalized. The single-ended to differential transform is based on a Walsh-Hadamard matrix H, where H is^-1＝H^TH. This property means that the original binary data can be recovered at the receiver end by decoding using the transformation matrix of the coding matrix, i.e.:

for common differential signaling transmission, voltage mode or current mode drivers are often used for transmitter transmit data, while the receiver front-end may extract binary data using a differential amplifier.

To achieve a more efficient chordal signaling scheme, higher order encoding and decoding matrices are used. Fig. 5 shows a link topology and a corresponding mathematical model of the present embodiment where n is 7(CNRZ-7), and the same orthogonal multiline signaling is used to finally complete 7b/8w transmission, so that the pin efficiency is improved by 175%. The corresponding CNRZ-7 link transfers 7 bits of data in parallel over 8 lines. At this time, the CNRZ-n encoding refers to CNRZ-7 encoding, and the functional expression of the transmitting end for string signaling encoding is:

in the above formula, CNRZ₇Is a CNRZ-7 coding matrix, Vcm is the common-mode voltage of the output end of a sending end, D₀～D₆For 7 bits of data to be encoded, w₀～w₇The 8-bit data obtained after encoding. Correspondingly, the functional expression of the receiving end for decoding the chord signaling is as follows:

in the above formula, Vcm is the common mode voltage between the transmitting terminal and the receiving terminal, D₀～D₆For the decoded 7-bit data, CNRZ₇ ^TIs an inverse matrix of the CNRZ-7 encoding matrix. Link topology with n-7 (CNRZ-7) and corresponding mathematical model, CNRZ-7 coding matrix CNRZ₇The functional expression of (a) is:

in this embodiment, the encoding at the transmitting end side is performed by using a CNRZ-n encoding matrix, a common mode voltage Vcm at the output end of the transmitting end, and n-bit data D₀～D_nWhen the formed matrix is multiplied to obtain n + 1bit string signaling obtained after coding, a coder (voltage mode driving: w 0-w 7) is used for each column of the CNRZ-n coding matrix at the transmitting end, and each row is used as a decoder corresponding to a receiving end of a subchannel.

As shown in fig. 6, the transmitting end side in this embodiment encodes the CNRZ-n encoding matrix, the common mode voltage Vcm at the transmitting end output end, and the n-bit data D₀～D_nWhen n + 1bit string signaling obtained after the formed matrix multiplication is coded, a sending end adopts a voltage mode driving mode in each preset unit interval UI, and the encoder is driven and simultaneously n bit data D are also subjected to n bit data D₀～D_nEncoded and transmitted, and fig. 6 shows 7-bit data (D)₀～D₆) Encoding to 8 lines (w)₀～w₇) The above. For each conductor (each column of the CNRZ-7 matrix) the correct input bit will be selected, weighted and used for the output drivers. The combined signal will be placed on the corresponding wire at the target output impedance. In this embodiment, the receiving end multiplies the n +1 string signaling and the inverse matrix of the CNRZ-n coding matrix to restore the n-bit data D transmitted by the transmitting end₀～D_nAt this time, n +1 wires are connected to n multi-input comparator circuits, each of which has an input stage that performs inverse linear transformation to realize linear combination, generating n equal-eye binary data. FIG. 7 shows eight wire connectionsThe input stage of each comparator performs inverse linear transformation to realize linear combination, and seven equal-eye binary data are generated. The example shown in FIG. 7 implements the first row of the CNRZ-7 matrix (subchannel number 0), whose functional expression is:

V_OUT,0＝[w₀+w₁+w₂+w₃-w₄-w₅-w₆-w₇]×g_mR_D， (7)

in the above formula, V_OUT,0For outputting data D₀Differential signal of (w)_iRepresenting the signal on channel i, R_DIs a load resistance, g_mIs the transconductance of each transistor of the differential pair of fig. 7. The output of each multiple-input comparator circuit is binary, despite the multiple levels on the conductors. Thus, communication can be performed through the slicing circuit. Although CNRZ-7 improves pin efficiency from double-ended differential 1/2 to 7/8 for CNRZ-7, it does not exhibit too high sensitivity to intersymbol interference, and maintains good immunity to common mode noise and signal crosstalk. In this embodiment, the linear and orthogonal transforms upon which the signaling is based are encoded and driven in the transmitter (see fig. 6), and decoded in the receiver's Multiple Input Comparator (MIC) (see fig. 7), which reduces sensitivity to crosstalk and other noise sources while maintaining high data rates and pin efficiency.

It is generally believed that signaling methods with more levels exhibit higher sensitivity to ISI. ISI sensitivity is directly related to the number of signal levels at the input of the slicer or decision circuit, as opposed to the number of levels on the transmission line. Consider a channel with an impulse response denoted by h (t). If c is_iIs from having N_CData symbols selected in the symbol set:

c_i∈c＝{c_j:j＝0,…,N_C-1}， (8)

in the above formula, N_CIs N_CTotal number of data symbols of the symbol set.

Then, after passing through an ideal multi-input comparator circuit, the transmitted signal can be described as:

in the above formula, s (t) is the transmitted signal, c_iIs from having N_CData symbols selected in the symbol set, P_u(T) denotes a rectangular pulse of width T, T applied, T symbol duration (corresponding to one unit interval UI).

Thus, the received signal will be the result of a discrete convolution of the transmitted signal with the transfer function:

H_T,i(t)is defined as:

in the above formula, r (t) is the received signal, H (t) is the transfer function, H_T,i(t)Is a fading term.

Assuming that the received signal T e [0, T), then there is:

in the above formula, c₀Is from having N_CThe first data symbol selected in the symbol set, H_T,0(t)Is the dominant fading term, and the second factor is the fading coefficient associated with intersymbol interference, i.e.:

wherein H_T,i(t)/H_T,0(t)Due to fading factors caused by channel ISI, and c_i/c₀Is due to inter-symbol interference sensitivity caused by the chordal signaling method. WhileThe intersymbol interference ratio of the coding scheme is defined as:

in the above formula, I_RThe code-to-code interference ratio (simply referred to as interference ratio) of the coding scheme, c' and c are arbitrary data. Then c in the worst case of intersymbol interference_i/c₀Equal to the interference rate I_RThus, there are:

it is important to note that in addition to channel loss, i.e., H_T,i(t)/H_T,0(t)In addition, there is a second factor that exacerbates susceptibility to intersymbol interference: interference rate I of the coding scheme as defined above_R. If all data symbols are equidistant from the receiving end, I_R1 and has no additional sensitivity to intersymbol interference. Both single-ended and differential PAM2 signaling methods satisfy I_R1. However, in PAM4 signaling, I_RThis explains why this signaling method exhibits a higher sensitivity to intersymbol interference and therefore requires a more complex equalization (see table 1).

Table 1: the main characteristics of the different signaling methods.

Analysis here shows that the choice of signaling method directly affects the link budget, and a well-designed signaling scheme helps to avoid unnecessary eye-opening loss. As with the chord signaling, the signal delivered to the slicer is binary, with IR ═ 1, similar to PAM2 signaling. Therefore, it will not watchExhibiting any excessive ISI sensitivity. In this embodiment, the width of the eye can be calculated using (15). At time interval [0, T]There are two time points in which r (t) is 0. If we call these two time points t_L(left side of eye) and t_R(right side of eye), the eye width is:

t_eye,width＝t_R-t_L， (16)

in the above formula, t_eye,widthIndicating the eye width (eye width).

As is apparent from (15) and (16), when IR>At 1, the eye width decreases more rapidly. The same analysis can be performed to show that eye height also decreases in direct proportion to IR, table 1 compares ISI sensitivity and pin efficiency for several major signaling methods. In this embodiment, the circuit simulation is performed on the method, a PRBS7 pseudo random code is input, a parameter extracted by a channel (channel attenuation is about 7.5dB) is added, and after equalization, D of 7-bit high-speed data is obtained₀～D₆The output eye diagram simulation results are shown in FIG. 8, where D is (a) in FIG. 8₀And (b) is D₁And (c) is D₂And (D) is D₃And (e) is D₄(f) is D₅(g) is D₆. As can be seen from fig. 8, the decoded signal is a completely binary NRZ signal.

In addition, the present embodiment further provides an apparatus for transmitting ultra-short distance data between chips in a multi-chip module, which includes a transmitter, a receiver, and a codec transmission module located between the transmitter and the receiver, where the codec transmission module includes an encoder, a decoder, and a plurality of transmission lines located between the encoder and the decoder, and the codec transmission module is programmed or configured to perform the steps of the method for transmitting ultra-short distance data between chips in a multi-chip module.

In addition, the present embodiment also provides a multi-core computing device, including a multi-core processor and a memory, which are connected to each other, where the multi-core processor is programmed or configured to execute the steps of the foregoing method for transmitting data with an ultra-short distance between chips in a multi-chip module.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims

1. A method for transmitting ultra-short distance data between chips in a multi-chip module is characterized by comprising a chord signaling for transmitting CNRZ-n codes between a transmitting end and a receiving end through multi-path differential signals, wherein n in the CNRZ-n codes refers to data bit width in the CNRZ-n codes, and the codes of the transmitting end to the chord signaling are that a CNRZ-n code matrix, common-mode voltage Vcm between the transmitting end and the receiving end and n-bit data D are encoded₀～D_nMultiplying the formed matrix to obtain n + 1bit string signaling obtained after coding; the receiving end decodes the string signaling into n bit data D which is obtained by multiplying the string signaling of n + 1bit and the inverse matrix of the CNRZ-n coding matrix and is transmitted by the transmitting end₀～D_n。

2. The method of claim 1, wherein the magnitude of the common mode voltage Vcm between the transmitter and the receiver satisfies the following requirements:

in the above formula, W_iThe coded data is the ith data.

3. The method of claim 2, wherein the CNRZ-n encoding is CNRZ-7 encoding, and the functional expression of the sending end for the string signaling encoding is:

4. The method of claim 3, wherein the function expression for decoding chordal signaling at the receiving end is:

5. The method of claim 4, wherein the CNRZ-7 coding matrix CNRZ₇The functional expression of (a) is:

6. the method of claim 5, wherein the transmitter side codes a CNRZ-n coding matrix, a common mode voltage Vcm at the output end of the transmitter, and n bits of data D₀～D_nWhen the formed matrix is multiplied to obtain n + 1bit string signaling obtained after coding, a coder is used by a sending end for each column of the CNRZ-n coding matrix, and each row is used as a decoder of a sub-channel corresponding to a receiving end.

7. The method of claim 6,the method is characterized in that the code on the transmitting end side is a CNRZ-n code matrix, a common-mode voltage Vcm at the output end of the transmitting end and n bit data D₀～D_nWhen n + 1bit string signaling obtained after the formed matrix multiplication is coded, a sending end adopts a voltage mode driving mode in each preset unit interval UI, and the encoder is driven and simultaneously n bit data D are also subjected to n bit data D₀～D_nEncoded and transmitted.

8. The method of claim 7, wherein the receiving end multiplies the n +1 bits of string signaling and the inverse matrix of the CNRZ-n coding matrix to restore the n bits of data D transmitted from the transmitting end₀～D_nAt this time, n +1 wires are connected to n multi-input comparator circuits, each of which has an input stage that performs inverse linear transformation to realize linear combination, generating n equal-eye binary data.

9. An apparatus for ultra-short distance data transmission between chips in a multi-chip module, comprising a transmitter, a receiver, and a codec transmission module located between the transmitter and the receiver, wherein the codec transmission module comprises an encoder, a decoder, and a plurality of transmission lines located between the encoder and the decoder, and the codec transmission module is programmed or configured to perform the steps of the method for ultra-short distance data transmission between chips in a multi-chip module according to any one of claims 1 to 8.

10. A multi-core computing device comprising an interconnected multi-core processor and a memory, characterized in that the multi-core processor is programmed or configured to perform the steps of the method for ultra-short distance data transmission between chips in a multi-chip module according to any of claims 1-8.