CN1905177A - Circuit assembly structure and method for making the same - Google Patents

Circuit assembly structure and method for making the same Download PDF

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Publication number
CN1905177A
CN1905177A CNA2006100991758A CN200610099175A CN1905177A CN 1905177 A CN1905177 A CN 1905177A CN A2006100991758 A CNA2006100991758 A CN A2006100991758A CN 200610099175 A CN200610099175 A CN 200610099175A CN 1905177 A CN1905177 A CN 1905177A
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Prior art keywords
layer
silicon compound
connection pad
metal level
compound layer
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CNA2006100991758A
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CN1905177B (en
Inventor
林茂雄
罗心荣
周秋明
周健康
陈科宏
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Qualcomm Inc
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Megica Corp
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Priority claimed from US11/383,762 external-priority patent/US8148822B2/en
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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Abstract

The invention relates a circuitry component and a producing method thereof. At least a pad is over the top of the semiconductor substrate; A passivation layer is loaded on the top of the semiconductor substrate, and at least an opening in said passivation layer exposing the pad; and a metalic layer is stacked on the pad.

Description

Circuit assembly structure and preparation method thereof
Technical field
The present invention relates to a kind of making and structure thereof of semiconductor subassembly, be particularly related to a kind of manufacture method and structure thereof that forms metal level on the semiconductor-based end, it is more can engage, paste band with routing to engage (TAB), film compound crystal automatically and engage (COF) or glass compound crystal and engage manufacture methods such as (COG) and mate mutually.
Background technology
In semiconductor technology now, if desire reduces the size of semiconductor subassembly, certainly will make that the packaging density of single IC for both chip presents dramatically in the assembly improves, yet, when the size of semiconductor subassembly is dwindled, component package density will improve, and the number of plies in order to articulamentum in the metal that electric connection is provided also must increase on the integrated circuit (IC) chip, to connect the structure that is separated from each other in the substrate effectively, for example, known single IC for both chip is to have articulamentum structure in two to six layers the metal in this field.
After the articulamentum structure, metallic pad is the top that is formed at articulamentum structure in this metal, in order to provide chip or crystal grain as external electric connection in the metal of multilayer of having grown up; Then, form a protective layer and be subjected to humidity and pollutant effects, and the material of protective layer is to can be silica (SiO to avoid chip 2), silicon nitride (Si 3N 4), silicon oxynitride (silicon oxy-nitride) or the combination of above-mentioned material; And after the growth protective layer, the crystal grain with plurality of circuits pattern then can be connected on the package substrates, and this package substrates is can have a plurality of envelope pin (pin) the circuit on it is connected on the outside printed circuit board (PCB).
Known wherein a kind of method in order to electric connection crystal grain and package substrates is to utilize the routing technology, wherein, one group of corresponding connection pad is to be positioned on the package substrates, one connecting line (connection wire) is to utilize routing that each metallic pad is connected on the package substrates on the corresponding connection pad, and wherein the method for routing is the mode of ultrasonic waves routing; Then, after finishing routing, encapsulating structure is to encapsulate (encapsulated) and sealing.
In fact, the reliability of routing joint manufacture method is the subject under discussion for a key, because it is one of back segment manufacture method for the whole production flow process that routing engages manufacture method, employed crystal grain is to have encapsulated and process test and screening (sorted), therefore, engaging the mistake that is produced in the manufacture method at routing is directly to damage good crystal grain.And in order to promote the reliability that routing engages, be used in metallic pad that routing engages must by can with engage the metal that manufacture method mates mutually and formed, and generally engage in the manufacture method at routing, commonly used is to be aluminium and aluminium alloy with the metal as metallic pad.
For fear of engage the problem that injected plastic step in the manufacture method or extension jointing metal line step are subjected to displacement at routing, the metallic pad that engages must be formed at earlier chip around, in addition, also must increase its length in order to the conducting wire layer between coupling assembling and the metallic pad (conductive trace).And,, the more development trend of highly compatible quicker towards having gradually along with chip, the number that I/O connects (I/O connetions) increases just very fastly, yet the inductance that produces between metallic pad and the jointing metal line will hinder the high speed operation of chip.
In view of this, The present invention be directed to above-mentioned problem, propose a kind of manufacture method and structure thereof that on the semiconductor-based end, forms metal level, to solve the difficulty that is met with in the prior art.
Summary of the invention
The object of the present invention is to provide a kind of metal level of sandwich construction, it is directly to engage with the suprabasil connection pad of semiconductor, and this metal level is to be applicable in the manufacture methods such as routing joint, the automatic joint of subsides band, film compound crystal joint or glass compound crystal joint.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; One bronze medal layer is positioned on this copper connection pad; And a palladium layer, be positioned on this copper layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; And a palladium layer, be positioned on this copper connection pad, and the thickness of this palladium layer is greater than 1.6 microns.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; One nickel dam is positioned on this copper connection pad, and the thickness of this nickel dam is greater than 1.6 microns; And a palladium layer, be positioned on this nickel dam.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; One bronze medal layer is positioned on this copper connection pad; And a platinum layer, be positioned on this copper layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; And a platinum layer, be positioned on this copper connection pad, and the thickness of this platinum layer is greater than 1.6 microns.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; One nickel dam is positioned on this copper connection pad, and the thickness of this nickel dam is greater than 1.6 microns; And a platinum layer, be positioned on this nickel dam.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and an opening that is positioned at this protective layer exposes this copper connection pad; And a rhodium layer, be positioned on this copper connection pad that this opening exposes.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and an opening that is positioned at this protective layer exposes this connection pad; And a ruthenium layer, be positioned on this connection pad that this opening exposes.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and an opening that is positioned at this protective layer exposes this connection pad; And a rhenium layer, be positioned on this connection pad that this opening exposes.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad; One bronze medal layer is positioned on this connection pad that this opening exposes; One nickel dam is positioned on this copper layer; One platinum layer is positioned on this nickel dam; And a routing lead, be positioned on this platinum layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad; One bronze medal layer is positioned on this connection pad that this opening exposes; One nickel dam is positioned on this copper layer; One palladium layer is positioned on this nickel dam; And a routing lead, be positioned on this palladium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad; One bronze medal layer is positioned on this connection pad that this opening exposes; One nickel dam is positioned on this copper layer; One rhodium layer is positioned on this nickel dam; And a routing lead, be positioned on this rhodium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad; One bronze medal layer is positioned on this connection pad that this opening exposes; One nickel dam is positioned on this copper layer; One ruthenium layer is positioned on this nickel dam; And a routing lead, be positioned on this ruthenium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first bronze medal connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a bronze medal layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first bronze medal connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a palladium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first bronze medal connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a platinum layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first bronze medal connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a rhodium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first connection pad; And a metallic circuit, being positioned on this protective layer, this metallic circuit comprises a ruthenium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a rhenium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad and a protective layer, wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; Form a metal level on this copper connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a palladium layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this palladium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad and a protective layer, wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; Form a metal level on this copper connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a platinum layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this platinum layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad and a protective layer, wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; Form a metal level on this copper connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a rhodium layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this rhodium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one connection pad and a protective layer, wherein this protective layer and this connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this connection pad; Form a metal level on this connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a ruthenium layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this ruthenium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one connection pad and a protective layer, wherein this protective layer and this connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this connection pad; Form a metal level on this connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a rhenium layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this rhenium layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one connection pad and a protective layer, wherein this protective layer and this connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this connection pad; Form a metal level on this connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a bronze medal layer on this metal level that this second opening is exposed; Form a nickel dam on this copper layer; Form a platinum layer on this nickel dam; Remove this patterning photoresist layer; Remove not this metal level under this platinum layer; Cutting this semiconductor-based end forms plural semiconductor subassembly; And utilize a routing manufacture method to form a routing lead on this platinum layer of this semiconductor subassembly, and be electrically connected to an external circuitry via this routing lead.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one connection pad and a protective layer, wherein this protective layer and this connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this connection pad; Form a metal level on this connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and be positioned at one of this patterning photoresist layer second opening and expose this metal level; Form a bronze medal layer on this metal level that this second opening is exposed; Form a nickel dam on this copper layer; Form a palladium layer on this nickel dam; Remove this patterning photoresist layer; Remove not this metal level under this palladium layer; Cutting this semiconductor-based end forms plural semiconductor subassembly; And utilize a routing manufacture method to form a routing lead on this palladium layer of this semiconductor subassembly, and be electrically connected to an external circuitry via this routing lead.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one connection pad and a protective layer, wherein this protective layer and this connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this connection pad; Form a metal level on this connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and be positioned at one of this patterning photoresist layer second opening and expose this metal level; Form a bronze medal layer on this metal level that this second opening is exposed; Form a nickel dam on this copper layer; Form a rhodium layer on this nickel dam; Remove this patterning photoresist layer; Remove not this metal level under this rhodium layer; Cutting this semiconductor-based end forms plural semiconductor subassembly; And utilize a routing manufacture method to form a routing lead on this rhodium layer of this semiconductor subassembly, and be electrically connected to an external circuitry via this routing lead.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one connection pad and a protective layer, wherein this protective layer and this connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this connection pad; Form a metal level on this connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and be positioned at one of this patterning photoresist layer second opening and expose this metal level; Form a bronze medal layer on this metal level that this second opening is exposed; Form a nickel dam on this copper layer; Form a ruthenium layer on this nickel dam; Remove this patterning photoresist layer; Remove not this metal level under this ruthenium layer; Cutting this semiconductor-based end forms plural semiconductor subassembly; And utilize a routing manufacture method to form a routing lead on this ruthenium layer of this semiconductor subassembly, and be electrically connected to an external circuitry via this routing lead.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; At least one metal level that contains tantalum coats the lower surface and the sidewall of this connection pad; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad; The metal level of one titaniferous is positioned on this connection pad that this opening exposes; And a gold medal layer, be positioned on the metal level of this titaniferous.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer, be positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad, and wherein this protective layer comprises one first nitrogen silicon compound layer, one of is positioned on this first nitrogen silicon compound layer the first oxygen silicon compound layer and is positioned at one second nitrogen silicon compound layer on this first oxygen silicon compound layer; The metal level of one titaniferous is positioned on this connection pad that this opening exposes; And a gold medal layer, be positioned on the metal level of this titaniferous.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; Dielectric constant values (k) is positioned on this semiconductor-based end between 1.5 to 3 plural thin dielectric film; Plural number wiring thin film layer was positioned on this semiconductor-based end, exist between those wiring thin film layers those thin dielectric films at least one of them, and see through those wiring thin film layers of the plural via connection adjacent two layers that is positioned at those thin dielectric films; At least one connection pad is positioned on those thin dielectric films; One protective layer, be positioned on those thin dielectric films and those wiring thin film layers on, and at least one opening that is positioned at this protective layer exposes this connection pad; The metal level of one titaniferous is positioned on this connection pad that this opening exposes; And a gold medal layer, be positioned on the metal level of this titaniferous.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One contains the first metal layer of tantalum, coats the lower surface and the sidewall of this first bronze medal connection pad; One protective layer was positioned on this semiconductor-based end, and one first opening that is positioned at this protective layer exposes this first bronze medal connection pad; One metallic circuit is positioned on this protective layer, and this metallic circuit comprises a gold medal layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One protective layer, be positioned on this semiconductor-based end, and one first opening that is positioned at this protective layer exposes this first bronze medal connection pad, and wherein this protective layer comprises one first nitrogen silicon compound layer, is positioned at the oxygen silicon compound layer on this first nitrogen silicon compound layer and one of is positioned on this oxygen silicon compound layer the second nitrogen silicon compound layer; One metallic circuit is positioned on this protective layer, and this metallic circuit comprises a gold medal layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; Dielectric constant values (k) is positioned on this semiconductor-based end between 1.5 to 3 plural thin dielectric film; Plural number wiring thin film layer was positioned on this semiconductor-based end, and saw through those wiring thin film layers that the plural via that is positioned at those thin dielectric films is communicated with adjacent two layers; One first bronze medal connection pad is positioned on those thin dielectric films; One protective layer, be positioned on those thin dielectric films and those wiring thin film layers on, and be positioned at one of this protective layer first opening and expose this first bronze medal connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a gold medal layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; One bronze medal layer is positioned on this copper connection pad; And a silver layer, be positioned on this copper layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; And a silver layer, be positioned on this copper connection pad, and the thickness of this silver layer is greater than 1.6 microns.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one copper connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; One nickel dam is positioned on this copper connection pad, and the thickness of this nickel dam is greater than 1.6 microns; And a silver layer, be positioned on this nickel dam.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; At least one metal level that contains tantalum coats the lower surface and the sidewall of this connection pad; One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad; And a sn-ag alloy layer, be positioned on this connection pad that this opening exposes.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; At least one connection pad was positioned on this semiconductor-based end; One protective layer, be positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this connection pad, and wherein this protective layer comprises one first nitrogen silicon compound layer, one of is positioned on this first nitrogen silicon compound layer the oxygen silicon compound layer and one of is positioned on this oxygen silicon compound layer the second nitrogen silicon compound layer; And a sn-ag alloy layer, be positioned on this connection pad that this opening exposes.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; Dielectric constant values (k) is positioned on this semiconductor-based end between 1.5 to 3 plural thin dielectric film; Plural number wiring thin film layer was positioned on this semiconductor-based end, and saw through those wiring thin film layers that the plural via that is positioned at those thin dielectric films is communicated with adjacent two layers; At least one connection pad is positioned on those thin dielectric films; One protective layer, be positioned on those thin dielectric films and those wiring thin film layers on, and at least one opening that is positioned at this protective layer exposes this connection pad; And a sn-ag alloy layer, be positioned on this connection pad that this opening exposes.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first bronze medal connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first bronze medal connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a silver layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuit assembly structure is proposed, comprise the semiconductor substrate; One first connection pad was positioned on this semiconductor-based end; One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first connection pad; And a metallic circuit, be positioned on this protective layer, and this metallic circuit comprises a sn-ag alloy layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad, an at least one metal level and protective layer that contains tantalum, wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, this metal level that contains tantalum coats the lower surface and the sidewall of this copper connection pad, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; The metal level that forms a titaniferous is on this copper connection pad that this first opening is exposed and on this protective layer; Form a patterning photoresist layer on the metal level of this titaniferous, and at least one second opening is positioned at this patterning photoresist layer; Form a gold medal layer in this second opening; Remove this patterning photoresist layer; And remove the not metal level of this titaniferous under this gold layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad and a protective layer, wherein this copper connection pad was positioned on this semiconductor-based end, this protective layer comprises one first nitrogen silicon compound layer, one of be positioned on this first nitrogen silicon compound layer the oxygen silicon compound layer and be positioned at one second nitrogen silicon compound layer on this oxygen silicon compound layer, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; The metal level that forms a titaniferous is on this copper connection pad that this first opening is exposed and on this protective layer; Form a patterning photoresist layer on the metal level of this titaniferous, and at least one second opening is positioned at this patterning photoresist layer; Form a gold medal layer in this second opening; Remove this patterning photoresist layer; And remove the not metal level of this titaniferous under this gold layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides the semiconductor substrate, an at least one copper connection pad and a protective layer, wherein this semiconductor-based end, comprise that complex dielectric constant value (k) is between 1.5 to 3 thin dielectric film and plural wiring thin film layer, those wiring thin film layers are between those thin dielectric films, and see through those wiring thin film layers of the plural via connection adjacent two layers be positioned at those thin dielectric films, this protective layer be positioned on those thin dielectric films and those wiring thin film layers on, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; The metal level that forms a titaniferous is on this copper connection pad that this first opening is exposed and on this protective layer; Form a patterning photoresist layer on the metal level of this titaniferous, and at least one second opening is positioned at this patterning photoresist layer; Form a gold medal layer in this second opening; Remove this patterning photoresist layer; And remove the not metal level of this titaniferous under this gold layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides the semiconductor substrate, be positioned at the suprabasil at least one copper connection pad of this semiconductor and one of be positioned on this semiconductor-based end protective layer, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; Form a patterning photoresist layer on this protective layer, and at least one second opening is positioned at this patterning photoresist layer; Electroless-plating one the first metal layer is in this second opening; And remove this patterning photoresist layer.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides the semiconductor substrate; Form a first metal layer on this semiconductor-based end; Form a patterning photoresist layer on this first metal layer, and at least one opening that is positioned at this patterning photoresist layer exposes this first metal layer; Electroplate one second metal level on this first metal layer that this opening exposed; Electroless-plating 1 the 3rd metal level is on this second metal level; Remove this patterning photoresist layer; And remove not this first metal layer under the 3rd metal level.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides the semiconductor substrate; Form a first metal layer on this semiconductor-based end; Form a patterning photoresist layer on this first metal layer, and at least one opening that is positioned at this patterning photoresist layer exposes this first metal layer; Electroless-plating one second metal level is on this first metal layer that this opening exposed; Electroplate one the 3rd metal level on this second metal level; Remove this patterning photoresist layer; And remove not this first metal layer under the 3rd metal level.
In order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad and a protective layer, wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; Form a metal level on this copper connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a silver layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this silver layer.
Realization is in order to realize above-mentioned purpose of the present invention, a kind of circuitry component fabricating method is proposed, its step comprises provides semiconductor substrate, at least one copper connection pad and a protective layer, wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this copper connection pad; Form a metal level on this copper connection pad and this protective layer; Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level; Form a sn-ag alloy layer on this metal level that this second opening is exposed; Remove this patterning photoresist layer; And remove not this metal level under this sn-ag alloy layer.
Below in conjunction with specific embodiment, explanation in detail in conjunction with the accompanying drawings, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 a to Fig. 1 e is the manufacture method generalized section of the semiconductor-based end of the present invention, thin on-line composition and protective layer;
Fig. 2 a to Fig. 2 k is the manufacture method generalized section of first embodiment of the invention;
Fig. 3 a to Fig. 3 g is the manufacture method generalized section of second embodiment of the invention;
Fig. 4 a to Fig. 4 h is the manufacture method generalized section of third embodiment of the invention;
Fig. 5 a to Fig. 5 i is the manufacture method generalized section of fourth embodiment of the invention;
Fig. 6 a to Fig. 6 k is the manufacture method generalized section of fifth embodiment of the invention;
Fig. 7 a to Fig. 7 d is the manufacture method generalized section of sixth embodiment of the invention;
Fig. 8 a to Fig. 8 k is the manufacture method generalized section of seventh embodiment of the invention;
Fig. 9 a to Fig. 9 j is the manufacture method generalized section of eighth embodiment of the invention;
Figure 10 a to Figure 10 j is the manufacture method generalized section of ninth embodiment of the invention;
Figure 11 a to Figure 11 f is the manufacture method generalized section of tenth embodiment of the invention;
Figure 12 a to Figure 12 i is the manufacture method generalized section of eleventh embodiment of the invention.
Description of reference numerals: the 10 semiconductor-based ends; 12 electronic building bricks; 14 thin on-line compositions; 16 thin dielectric films; 18 wiring thin film layers; 20 inorganic protective layers; 22 irrigation canals and ditches; 24 vias; 26 barrier layers; 28 Seed Layer; 30 bronze medal metals; 32 bronze medal connection pads; 34 protective layers; 36 openings; 38 the first metal layers; 40 Seed Layer; 42 photoresist layers; 44 openings; 46 second metal levels; 48 polymeric layers; 50 openings; 52 semiconductor subassemblies; 54 routing leads; 56 flexible base plates; 58 polymer; 60 anisotropic conductives; 62 glass substrates; 64 flexible base plates; 66 second metal levels; 68 the 3rd metal levels; 70 second metal levels; 72 the 3rd metal levels; 74 the 4th metal levels; 76 second metal levels; 78 the 3rd metal levels; 80 the 4th metal levels; 82 the 5th metal levels; 84 the first metal layers; 86 second metal levels; 88 photoresist layers; 90 the 3rd metal levels; 92 Seed Layer; 94 photoresist layers; 96 openings; 98 the 4th metal levels; 100 gaps; 102 the 4th metal levels; 104 the 5th metal levels; 106 the 6th metal levels; 108 polymeric layers; 110 first openings; 112 second openings; 114 the first metal layers; 116 Seed Layer; 118 photoresist layers; 120 openings; 122 second metals; 124 metallic circuits; 126 polymeric layers; 128 openings; 130 routing leads; 132 polymeric layers; 134 the first metal layers; 136 Seed Layer; 138 photoresist layers; 140 openings; 142 second metal levels; 144 metallic circuits; 146 polymeric layers; 148 openings; 150 routing leads; 152 polymeric layers; 154 openings; 156 the first metal layers; 158 Seed Layer; 160 photoresist layers; 162 openings; 164 second metal levels; 166 metallic circuits; 168 polymeric layers; 170 openings; 172 routing leads; 174 the first metal layers; 176 Seed Layer; 178 photoresist layers; 180 openings; 182 metal couplings; 184 contain tin projection; 186 the first metal layers; 188 Seed Layer; 190 patterning photoresist layers; The 192a opening; The 192b opening; The 192c opening; 194a second metal level; 194b second metal level; 194c second metal level; 196a the 3rd metal level; 196b the 3rd metal level; 196c the 3rd metal level; 198 patterning photoresist layers; The 200a opening; The 200b opening; 202a the 4th metal level; 202b the 4th metal level; 204a the 5th metal level; 204b the 5th metal level; 206 photoresist layers; 208 openings; 210 metal couplings; 320 first bronze medal connection pads; 322 second bronze medal connection pads; 324 bronze medal connection pads; 326 bronze medal connection pads; 328 bronze medal connection pads; 340 openings; 342 openings; 344 openings.
Embodiment
The invention relates to a kind of the utilization and electroplate manufacture method or electroless-plating manufacture method structure and manufacture method with the metal level that forms a sandwich construction, it is to engage with suprabasil copper connection pad of semiconductor or aluminium connection pad, and this metal level is to be applicable in the manufacture methods such as routing joint, the automatic joint of subsides band, film compound crystal joint or glass compound crystal joint.In addition; in disclosed each structure of the present invention and method all is to be built in the semiconductor substrate; and on this semiconductor-based end, more be provided with a thin on-line composition and a protective layer; therefore at first with explaining orally the structure and the formation method of the relevant semiconductor-based end, thin on-line composition and protective layer, then carry out the explanation of various embodiments of the invention again.
At first, see also shown in Fig. 1 a, the form at the semiconductor-based end 10 is such as being silicon base, the GaAs based end (GaAs), the germanium silicide substrate, has crystal silicon of heap of stone (silicon-on-insulator on insulating barrier, SOI) substrate, and the semiconductor-based in this embodiment end 10 is the semiconductor wafers for circle, and this semiconductor-based end 10, have an active surface, and the active surface of ion (for example boron ion or phosphonium ion etc.) at the semiconductor-based end 10 that sees through doping pentavalent or trivalent forms a plurality of electronic building bricks 12, and this electronic building brick 12 for example is metal-oxide semiconductor assembly (MOS devices), p channel metal-oxide semiconductor assembly (p-channel MOS devices), n channel metal-oxide semiconductor assembly (n-channel MOS devices), two-carrier CMOS (Complementary Metal Oxide Semiconductor) assembly (BiCMOSdevices), two-carrier connects transistor (Bipolar Junction Transistor, BJT), complementary metal oxide semiconductor (CMOS), diffusion region (Diffusion area), resistor assembly (resistor) and capacitance component (capacitor) etc.
Continue to see also shown in Fig. 1 b, on the active surface at the semiconductor-based end 10, form a thin on-line composition 14, this thin on-line composition 14 is less than the thin dielectric film 16 of 3 microns (μ m) and thickness 18 formation of wiring thin film layer less than 3 microns by plural thickness, wherein wiring thin film layer 18 is to be selected from copper metal material or aluminum metal material, and thin dielectric film 16 is called dielectric layer, generally is to utilize the mode of chemical vapour deposition (CVD) to form.This thin dielectric film 16 is such as the compound (Si for example that is tetraethoxysilane (TEOS) oxide of silica, chemical vapour deposition (CVD), siliceous, carbon, oxygen and hydrogen wC xO yH z), nitrogen silicon compound, fluoride glass (FSG), black diamond film (BlackDiamond), silk-screen layer (SiLK), poriness silicon oxide (porous silicon oxide) or nitrogen-oxygen-silicon compound, or the glass (SOG) that forms in the spin coating mode, poly-aryl ester (polyarylene ether), polyphenyl oxazole (polybenzoxazole, PBO), or other dielectric constant values (k) between 1.5 to 3 material.
See also shown in Fig. 1 c, with regard to the damascene manufacture method, forming the mode of plural wiring thin film layer 18 on the semiconductor-based end 10 is to utilize chemical vapour deposition (CVD) (chemical vapor deposition earlier, CVD) deposition one inorganic protective layer 20 is on the upper surface of thin dielectric film 16, the material of this inorganic protective layer 20 is to be selected from the nitrogen silicon compound, nitrogen-oxygen-silicon compound or carbon-silicon compound, then form a patterning photoresist layer on inorganic protective layer 20, and utilize the patterning opening etching inorganic protective layer 20 that is positioned at the patterning photoresist layer to form the opening of being formed by irrigation canals and ditches 22 and via 24 with thin dielectric film 16, then utilize the mode of sputter or chemical vapour deposition (CVD) deposit a barrier layer 26 in this opening lower surface and sidewall on and on the upper surface of inorganic protective layer 20, wherein the material of this barrier layer 26 is to be selected from tantalum (Ta), tantalum nitride (TaN), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), niobium (Nb), alumina silicate (aluminum silicate), titanium nitride (TiN) and titanium silicon nitride (TiSiN) one of them, or the formed alloy of above-mentioned material; Coming to utilize equally the mode of sputter or chemical vapour deposition (CVD) to deposit one deck more for example is that the Seed Layer 28 of copper material is on barrier layer 26; then electroplate a bronze medal metal 30 on this Seed Layer 28; utilize cmp (chemical mechanical polish at last; CMP) mode is removed and is positioned at this opening outer copper metal 30, Seed Layer 28 and barrier layer 26; till the upper surface that exposes inorganic protective layer 20; for making structure letter understandable, only show thin on-line composition 14 wherein the detailed structure of one deck in figure.
Shown in Fig. 1 c, formed barrier layer 26, Seed Layer 28 and copper metal 30 are to be wiring thin film layer 18 in irrigation canals and ditches 22 in this way, and the thickness of wiring thin film layer 18 is between 0.1 micron to 2 microns, and these a little wiring thin film layers 18 can or be connected on the electronic building brick 12 through the wiring thin film layer 18 between the 24 connection adjacent two layers of the plural vias in the thin dielectric film 16.In addition, see also shown in Fig. 1 d, is to be called copper connection pad 32 in the described mode of Fig. 1 c at the formed wiring thin film layer 18 in the top of thin on-line composition 14, its use in order to externally to electrically connect as electronic building brick 12, and similarly the lower surface and the sidewall of this copper connection pad 32 are coated with barrier layer 26 and Seed Layer 28.
Continue to see also shown in Fig. 1 f; behind the upper surface of the inorganic protective layer 20 that exposes thin on-line composition 14 tops; then utilize the mode of chemical vapour deposition (CVD) one protective layer 34 to be set on the upper surface and copper connection pad 32 of the inorganic protective layer 20 that exposes; and this protective layer 34 offers plural opening 36 and exposes most copper connection pads 32; wherein the maximum transverse size of these a little openings 36 is between 0.5 micron to 15 microns, or between 15 microns to 300 microns.
Protective layer 34 can protect the electronic building brick 12 at the semiconductor-based end 10 to avoid the destruction of moisture and foreign ion pollutant (foreign ion contamination); that is to say that protective layer 34 can prevent that moving iron (mobile ions) (such as being sodium ion), aqueous vapor (moisture), transition metal (transition metal) (such as being gold, silver, copper) and other impurity (impurity) from penetrating, and damage the electronic building brick 12 or the wiring thin film of transistor, polysilicon resistance assembly or the polysilicon-polysilicon silicon capacitance component of protective layer 34 belows.In order to reach the purpose of protection; protective layer 34 normally is made up of institutes such as oxygen silicon compound, phosphorosilicate glass, nitrogen silicon compound and nitrogen-oxygen-silicon compounds; and wherein above-mentioned oxygen silicon compound is to comprise organic oxygen compound or inorganic oxide; and the protective layer 34 present production methods that are applicable to copper connection pad 32 have four kinds of distinct methods approximately, are described below.
First kind of protective layer 34 manufacture method can be to utilize the step of chemical vapour deposition (CVD) to form the nitrogen-oxygen-silicon compound layer of thickness between 0.05 to 0.15 micron earlier; then utilize again the step of chemical vapour deposition (CVD) form thickness between the oxygen silicon compound layer between 0.2 to 1.2 micron on this nitrogen-oxygen-silicon compound layer, the step formation thickness that then utilizes chemical vapour deposition (CVD) again between the nitrogen silicon compound layer between 0.2 to 1.2 micron on this oxygen silicon compound layer.
Second kind of protective layer 34 manufacture method can be optionally to utilize the step of chemical vapour deposition (CVD) to form the one first nitrogen-oxygen-silicon compound layer of thickness between 0.05 to 0.15 micron earlier; then utilize again the step of chemical vapour deposition (CVD) form thickness between the oxygen silicon compound layer between 0.2 to 1.2 micron on this first nitrogen-oxygen-silicon compound layer; then can optionally utilize the step of chemical vapour deposition (CVD) form thickness between one second nitrogen-oxygen-silicon compound layer between 0.05 to 0.15 micron on this oxygen silicon compound layer; then utilize again the step of chemical vapour deposition (CVD) form thickness between the nitrogen silicon compound layer between 0.2 to 1.2 micron on this second nitrogen-oxygen-silicon compound layer or on this oxygen silicon compound layer; then can optionally utilize the step of chemical vapour deposition (CVD) form thickness between one the 3rd nitrogen-oxygen-silicon compound layer between 0.05 to 0.15 micron on this nitrogen silicon compound layer, the step formation thickness that then utilizes chemical vapour deposition (CVD) again between the oxygen silicon compound layer between 0.2 to 1.2 micron on this 3rd nitrogen-oxygen-silicon compound layer or on this nitrogen silicon compound layer.
The third protective layer 34 manufacture methods can be to utilize the step of chemical vapour deposition (CVD) to form the one first nitrogen silicon compound layer of thickness between 0.2 to 1.2 micron earlier; then utilize again the step of chemical vapour deposition (CVD) form thickness between the oxygen silicon compound layer between 0.2 to 1.2 micron on this first nitrogen silicon compound layer, the step formation thickness that then utilizes chemical vapour deposition (CVD) again between one second nitrogen silicon compound layer between 0.2 to 1.2 micron on this oxygen silicon compound layer.
The 4th kind of protective layer 34 manufacture methods can be to utilize the step of chemical vapour deposition (CVD) to form the nitrogen-oxygen-silicon compound layer of thickness between 0.05 to 0.15 micron earlier; then utilize the step of chemical vapour deposition (CVD) form thickness between one first oxygen silicon compound layer between 0.2 to 1.2 micron on this nitrogen-oxygen-silicon compound layer; utilize again the step of chemical vapour deposition (CVD) form thickness between the nitrogen silicon compound layer between 0.2 to 1.2 micron on this first oxygen silicon compound layer, the step formation thickness that then utilizes chemical vapour deposition (CVD) again between one second oxygen silicon compound layer between 0.2 to 1.2 micron on this nitrogen silicon compound layer.
Wherein the thickness of the protective layer 34 on the semiconductor-based end 10 generally is greater than 0.35 micron, and under preferable situation, the thickness of nitrogen silicon compound layer is usually greater than 0.3 micron.
So far finish the explanation of the semiconductor-based end 10, thin on-line composition 14 and protective layer 34, beneathly will each embodiment of the present invention be described in regular turn respectively at semiconductor-based the end 10 to have copper connection pad 32.
First embodiment
First embodiment is to serve as the explanation target to form metal level on copper connection pad 32.See also shown in Fig. 2 a, at first utilize sputter, the mode of plating or chemical vapour deposition (CVD) forms a first metal layer 38 on copper connection pad 32 and protective layer 34, the material of this first metal layer 38 is to be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them, then utilize sputter equally, the mode of plating or chemical vapour deposition (CVD) forms a Seed Layer 40 on the first metal layer 38, this Seed Layer 40 helps the setting of subsequent metal layer, therefore the material of Seed Layer 40 can change to some extent with follow-up metal level material, for example when on the Seed Layer 40 being the metal level of the golden material of plating formation, the material of Seed Layer 40 is with Jin Weijia; In the time will electroplating the metal level that forms silver-colored material, the material of Seed Layer 40 is to be good with silver; When being when electroplate forming the metal level of copper material on the Seed Layer 40, the material of Seed Layer 40 is to be good with copper; In the time will electroplating the metal level that forms the palladium material, the material of Seed Layer 40 is to be good with palladium; In the time will electroplating the metal level that forms platinum product matter, the material of Seed Layer 40 is to be good with platinum; In the time will electroplating the metal level that forms the rhodium material, the material of Seed Layer 40 is to be good with rhodium; In the time will electroplating the metal level that forms the ruthenium material, the material of Seed Layer 40 is to be good with ruthenium; In the time will electroplating the metal level that forms the rhenium material, the material of Seed Layer 40 is to be good with rhenium; In the time will electroplating the metal level that forms the nickel material, the material of Seed Layer 40 is to be good with nickel.
Come again, see also shown in Fig. 2 b, utilize the mode of spin coating (spin-coating) to form a photoresist layer 42 on Seed Layer 40, the pattern of this photoresist layer 42 is to be positive photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Continue to see also shown in Fig. 2 c, this photoresist layer 42 of patterning exposes Seed Layer 40 to form most openings 44, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening 44, then when photoresist layer 42 is the sensitization material, then such as utilizing little shadow manufacture method (photolithographyprocess), photoresist layer 42 patternings are formed most openings 44, and when photoresist layer 42 is non-sensitization material, then, photoresist layer 42 patternings are formed most openings 44 such as utilizing lithography manufacture method (photolithography process and etching process).
In addition, forming on photoresist layer 42 and the opening 44 thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 42, if wherein forming 42 of photoresist layers in the screen painting mode can directly form most openings 44 and expose Seed Layer 40 in photoresist layer 42, if so form photoresist layer 42 in hot pressing dry film mode, then can be after forming photoresist layer 42, form most openings 44 again and expose Seed Layer 40, but also can be directly in photoresist layer 42, form most openings 44 and expose Seed Layer 40.
Then see also shown in Fig. 2 d, with electroplate or the mode of electroless-plating form thickness greater than 1.6 microns or greater than 2 microns one second metal level 46 on the Seed Layer 40 that opening 44 is exposed, these second metal level, 46 preferable thickness are between 2 microns to 10 microns, and this second metal level 46 is such as being gold, copper, silver, palladium, platinum, rhodium, the single-layer metal layer structure of ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only second metal level 46 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be the leypewter layer, the sn-ag alloy layer, the SAC alloy-layer, the lead-free solder layer.If this second metal level 46 is the scolder material, then the preferred thickness of second metal level 46 is between 3 microns to 150 microns.
At last, shown in Fig. 2 e, remove photoresist layer 42 and not Seed Layer under second metal level 46 40 and the first metal layer 38, and on the mode of removing the first metal layer 38 and Seed Layer 40, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 46 40 and the first metal layer 38, and when carrying out Wet-type etching if Seed Layer 40 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 38 is titanium-tungsten, then can use hydrogen peroxide to remove.
With the structure shown in Fig. 2 e, the present invention can see through and be exposed to the second extraneous metal level 46, engage, paste band with routing and engage (Tape Automated Bonding automatically, TAB), the glass compound crystal engages (Chip-on-glass, COG) or the film compound crystal engage that (chip on film, COF) etc. manufacture method is mated mutually.For example see also shown in Fig. 2 f to Fig. 2 h; it is the generalized section that is applied to the manufacture method step of routing joint for present embodiment; at first see also shown in Fig. 2 f; after finishing the structure shown in Fig. 2 e; then form a polymeric layer 48 on the protective layer 34 and second metal level 46; wherein this polymeric layer 48 has insulation function; its material is such as being thermoplastics; thermoset plastics; polyimide (polyimide; PI); benzyl ring butylene (benzo-cyclo-butene; BCB); polyurethane (polyurethane); epoxy resin; the Parylene family macromolecule; the weldering cover material; elastomeric material or porousness dielectric material; this polymeric layer 48 mainly is to utilize the spin coating mode to be provided with in addition, so also can utilize hot pressing dry film or screen painting mode to carry out.
Continue to see also shown in Fig. 2 g, utilize etching mode that this polymeric layer 48 is carried out patterning, expose second metal level 46 to form most openings 50, wherein, when polymeric layer 48 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with polymeric layer 48 patternings; When polymeric layer 48 is non-sensitization material, then such as utilizing lithography manufacture method (photolithographyprocess and etching process), with polymeric layer 48 patternings.After polymeric layer 48 patternings, can utilize baking heating, microwave heating, infrared ray to heat one of them mode and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 48 that hardens.
Then see also Fig. 2 h, carry out cutting semiconductor substrate 10 and form most semiconductor subassemblies 52, and form routing lead 54 on second metal level, 46 end faces that exposed by the routing manufacture method, make semiconductor subassembly 52 be electrically connected to external circuitry, when wherein serving as gold layer, platinum layer or palladium layer, be for carrying out the preferable material of routing manufacture method with second metal level 46.
In addition, also can be shown in Fig. 2 i, after finishing the formed structure of Fig. 2 e, carry out cutting semiconductor substrate 10 and form most semiconductor subassemblies 52, and engage manufacture method automatically by winding, second metal level 46 on the semiconductor subassembly 52 is bonded on the flexible base plate 56, then coats the joint of the flexible base plate 56 and second metal level 46 again with a polymer 58; In addition, see also shown in Fig. 2 i, also can utilize anisotropic conductive (ACF) 60 that second metal level 46 on the semiconductor subassembly 52 is electrically connected a connection pad that is positioned on the glass substrate 62 by the glass flip chip encapsulation technology; See also shown in Fig. 2 k, equally also can be by film compound crystal technology, utilize anisotropic conductive 60 that second metal level 46 on the semiconductor subassembly 52 is electrically connected a connection pad that is positioned on the flexible base plate 64, then coat the joint of the flexible base plate 64 and second metal level 46 again with a polymer 58.
Second embodiment
This embodiment is similar to first embodiment, and difference is to form two metal layers on the Seed Layer 40 that opening 44 exposed.See also shown in Fig. 3 a, after finishing the structure shown in Fig. 2 c, then form one second metal level 66 on the Seed Layer 40 that opening 44 is exposed in the mode of electroplating, and the thickness of this second metal level 66 can be that thickness is greater than 1.6 microns or between 2 microns to 10 microns, again this second metal level 66 such as be thickness between the copper between 0.1 micron to 10 microns (preferred thickness is between 0.5 micron to 5 microns), or thickness is between the single-layer metal layer structure of the nickel between 0.1 micron to 10 microns (preferred thickness is between 0.5 micron to 3 microns).
Continue to see also shown in Fig. 3 b, mode with plating or electroless-plating forms one the 3rd metal level 68 on second metal level 66, and the thickness of this 3rd metal level 68 can be greater than 1.6 microns, greater than 2 microns or between 2 microns to 10 microns, this the 3rd metal level 68 is such as being gold again, copper, silver, palladium, platinum, rhodium, ruthenium, the single-layer metal layer structure of rhenium or nickel, or the composite bed of forming by above-mentioned metal material, only the 3rd metal level 68 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be the leypewter layer, the sn-ag alloy layer, the SAC alloy-layer, the lead-free solder layer.If this 3rd metal level 68 is the scolder material, then the preferred thickness of the 3rd metal level 68 is between 3 microns to 150 microns.
At last, shown in Fig. 3 c, remove photoresist layer 42 and not Seed Layer under the 3rd metal level 68 40 and the first metal layer 38, and on the mode of removing the first metal layer 38 and Seed Layer 40, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 42 40 and the first metal layer 38, and when carrying out Wet-type etching if Seed Layer 40 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 38 is titanium-tungsten, then can use hydrogen peroxide to remove.
In addition, see also shown in Fig. 3 d to Fig. 3 g, after finishing the structure shown in Fig. 3 c, then cut the most semiconductor subassemblies 52 of these semiconductor-based end 10 formation, and all can using routing manufacture method, winding to engage manufacture method, glass flip chip encapsulation technology and film compound crystal joining technique automatically, each semiconductor subassembly 52 is connected on the external circuitry, wherein the process of Jie Heing explains orally in first embodiment, in this just not repeat specification.
The 3rd embodiment
This embodiment is similar to first embodiment, and difference is to form the three-layer metal layer on the Seed Layer 40 that opening 44 exposed.See also shown in Fig. 4 a, after finishing the structure shown in Fig. 2 c, then form one second metal level 70 of thickness between 0.1 micron to 10 microns on the Seed Layer 40 that opening 44 is exposed in the mode of electroplating, for example electroplate a bronze medal layer on the Seed Layer 40 that opening 44 is exposed, and the preferable thickness of this copper layer is between 0.5 micron to 5 microns.
Then see also shown in Fig. 4 b, with electroplate or the mode of electroless-plating form thickness between one the 3rd metal level 72 between 0.1 micron to 10 microns on second metal level 70, for example electroplate a nickel dam on second metal level 70, and the preferable thickness of this nickel dam is between 0.5 micron to 3 microns, and for example electroless-plating one material is that the metal of gold, silver, platinum, palladium, rhodium, ruthenium, rhenium is on second metal level 70 again.
See also again shown in Fig. 4 c, mode with plating or electroless-plating forms one the 4th metal level 74 on the 3rd metal level 72, and the thickness of this second metal level 46 can be greater than 1.6 microns, greater than 2 microns, between between 2 microns to 10 microns or between 2 microns to 30 microns, this the 4th metal level 74 is such as being gold again, copper, silver, palladium, platinum, rhodium, the single-layer metal layer structure of ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only the 4th metal level 74 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be the leypewter layer, the sn-ag alloy layer, the SAC alloy-layer, the lead-free solder layer.If this 4th metal level 74 is the scolder material, then the preferred thickness of the 4th metal level 74 is between 3 microns to 150 microns.
See also at last shown in Fig. 4 d, remove photoresist layer 42 and not Seed Layer under the 4th metal level 74 40 and the first metal layer 38, and on the mode of removing the first metal layer 38 and Seed Layer 40, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 42 40 and the first metal layer 38, and when carrying out Wet-type etching if Seed Layer 40 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 38 is titanium-tungsten, then can use hydrogen peroxide to remove.
In addition, see also shown in Fig. 4 e to Fig. 4 h, after finishing the structure shown in Fig. 4 d, then cut the most semiconductor subassemblies 52 of these semiconductor-based end 10 formation, and all can using routing manufacture method, winding to engage manufacture method, glass flip chip encapsulation technology and film compound crystal joining technique automatically, each semiconductor subassembly 52 is connected on the external circuitry, wherein the process of Jie Heing explains orally in first embodiment, in this just not repeat specification.
The 4th embodiment
This embodiment is similar to first embodiment, and difference forms double layer of metal with electroless-plating after being to electroplate earlier on the Seed Layer 40 that opening 44 exposed and forming two metal layers again.See also shown in Fig. 5 a, after finishing the structure shown in Fig. 2 c, then form one second metal level 76 of thickness between 0.1 micron to 10 microns on the Seed Layer 40 that opening 44 is exposed in the mode of electroplating, for example electroplate a bronze medal layer on the Seed Layer 40 that opening 44 is exposed, and the preferable thickness of this copper layer is between 0.5 micron to 5 microns.
Continue to see also shown in Fig. 5 b, with the mode of electroplating form thickness between one the 3rd metal level 78 between 0.1 micron to 10 microns on second metal level 76, for example electroplate a nickel dam on second metal level 76, and the preferable thickness of this nickel dam is between 0.5 micron to 3 microns.
Then see also shown in Fig. 5 c, with the mode of electroless-plating form thickness between one the 4th metal level 80 between 0.001 micron to 2 microns on the 3rd metal level 78, this 4th metal level 80 is such as the single-layer metal layer structure that is gold, copper, silver, palladium, platinum, rhodium, ruthenium or rhenium.
See also again shown in Fig. 5 d, with the mode of electroless-plating form thickness between one the 5th metal level 82 between 2 microns to 30 microns on the 4th metal level 80, this 5th metal level 82 is such as the single-layer metal layer structure that is gold, copper, silver, palladium, platinum, rhodium, ruthenium or rhenium.
See also at last shown in Fig. 5 e, remove photoresist layer 42 and not Seed Layer under the 5th metal level 82 40 and the first metal layer 38, and on the mode of removing the first metal layer 38 and Seed Layer 40, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 42 40 and the first metal layer 38, and when carrying out Wet-type etching if Seed Layer 40 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 38 is titanium-tungsten, then can use hydrogen peroxide to remove.
In addition, see also shown in Fig. 5 f to Fig. 5 i, after finishing the structure shown in Fig. 5 e, then cut the most semiconductor subassemblies 52 of these semiconductor-based end 10 formation, and all can using routing manufacture method, winding to engage manufacture method, glass flip chip encapsulation technology and film compound crystal joining technique automatically, each semiconductor subassembly 52 is connected on the external circuitry, wherein the process of Jie Heing explains orally in first embodiment, in this just not repeat specification.
The 5th embodiment
This embodiment is developed by Fig. 1 f; see also shown in Fig. 6 a; at first utilize the mode of sputter, plating or chemical vapour deposition (CVD) to form a first metal layer 84 on copper connection pad 32 and protective layer 34, the material of this first metal layer 84 be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them.
Continue to see also shown in Fig. 6 b, utilize the mode of sputter, plating or chemical vapour deposition (CVD) to form one second metal level 86 on the first metal layer 84, the material of this second metal level 86 be selected from aluminium, gold, silver, palladium, platinum, rhodium, ruthenium, rhenium, leypewter and sn-ag alloy one of them or the group that formed at least one of them.
Then, see also shown in Fig. 6 c, utilize the mode of spin coating (spin-coating) to form a photoresist layer 88 on second metal level 86, the pattern of this photoresist layer 88 is to be negative photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Continue to see also shown in Fig. 6 d, this photoresist layer 88 of patterning exposes second metal level 86 to form most openings, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening, then when photoresist layer 88 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), photoresist layer 88 patternings are formed most openings, and when photoresist layer 88 is non-sensitization material, then, photoresist layer 88 patternings are formed most openings such as utilizing lithography manufacture method (photolithography process andetching process).
In addition, forming on photoresist layer 88 and the opening thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 88, if wherein forming 88 of photoresist layers in the screen painting mode can directly form most openings and expose second metal level 86 in photoresist layer 88, if so form photoresist layer 88 in hot pressing dry film mode, then can be after forming photoresist layer 88, form most openings again and expose second metal level 86, but also can be directly in photoresist layer 88, form most openings and expose second metal level 86.
Come again, see also shown in Fig. 6 e, at first remove not second metal level 86 and the first metal layer 84 under photoresist layer 88, then remove photoresist layer 88 again.See also shown in Fig. 6 f; after finishing the structure shown in Fig. 6 e; utilize the mode of sputter, plating or chemical vapour deposition (CVD) to form one the 3rd metal level 90 on second metal level 86 and protective layer 34, the material of this 3rd metal level 90 be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them.Then utilize the mode of sputter, plating or chemical vapour deposition (CVD) to form a Seed Layer 92 on the 3rd metal level 90 equally, this Seed Layer 92 helps the setting of subsequent metal layer, therefore the material of Seed Layer 92 can change to some extent with follow-up metal level material, for example when on the Seed Layer 92 being the metal level of the golden material of plating formation, the material of Seed Layer 92 is with Jin Weijia; In the time will electroplating the metal level that forms silver-colored material, the material of Seed Layer 92 is to be good with silver; When being when electroplate forming the metal level of copper material on the Seed Layer 92, the material of Seed Layer 92 is to be good with copper; In the time will electroplating the metal level that forms the palladium material, the material of Seed Layer 92 is to be good with palladium; In the time will electroplating the metal level that forms platinum product matter, the material of Seed Layer 92 is to be good with platinum; In the time will electroplating the metal level that forms the rhodium material, the material of Seed Layer 92 is to be good with rhodium; In the time will electroplating the metal level that forms the ruthenium material, the material of Seed Layer 92 is to be good with ruthenium; In the time will electroplating the metal level that forms the rhenium material, the material of Seed Layer 92 is to be good with rhenium; In the time will electroplating the metal level that forms the nickel material, the material of Seed Layer 92 is to be good with nickel.
Continue to see also shown in Fig. 6 g, utilize the mode of spin coating (spin-coating) to form a photoresist layer 94 on Seed Layer 92, the pattern of this photoresist layer 94 is to be positive photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Then see also shown in Fig. 6 h, this photoresist layer 94 of patterning exposes Seed Layer 92 to form most openings 96, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening 96, then when photoresist layer 94 is the sensitization material, then such as utilizing little shadow manufacture method (photolithographyprocess), photoresist layer 94 patternings are formed most openings 96, and when photoresist layer 94 is non-sensitization material, then, photoresist layer 94 patternings are formed most openings 96 such as utilizing lithography manufacture method (photolithography process and etching process).
In addition, forming on photoresist layer 94 and the opening 96 thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 94, if wherein forming 94 of photoresist layers in the screen painting mode can directly form most openings 96 and expose Seed Layer 92 in photoresist layer 94, if so form photoresist layer 94 in hot pressing dry film mode, then can be after forming photoresist layer 94, form most openings 96 again and expose Seed Layer 92, but also can be directly in photoresist layer 94, form most openings 96 and expose Seed Layer 92.
Then see also shown in Fig. 6 i, mode with plating or electroless-plating forms one four metal level 98 of thickness between 0.1 micron to 10 microns on the Seed Layer 92 that opening 96 is exposed, this the 4th metal level 98 is such as the single-layer metal layer structure that is gold, copper, silver, palladium, platinum, rhodium, ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only the 4th metal level 98 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be leypewter layer, sn-ag alloy layer, SAC alloy-layer, lead-free solder layer.If this 4th metal level 98 is the scolder material, then the preferred thickness of the 4th metal level 98 is between 3 microns to 150 microns.
At last, shown in Fig. 6 j, remove photoresist layer 94 and not Seed Layer under the 4th metal level 98 92 and the first metal layer 90, and on the mode of removing the first metal layer 90 and Seed Layer 92, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under the 4th metal level 98 92 and the first metal layer 90, and when carrying out Wet-type etching if Seed Layer 92 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 90 is titanium-tungsten, then can use hydrogen peroxide to remove.
In addition; when the top layer of protective layer 34 is during for the oxygen silicon compound layer; if the Seed Layer under the 4th metal level 98 92 can be shown in Fig. 6 k with 90 of the first metal layers to use the dry-etching removal; the oxygen silicon compound layer of protective layer 34 top layers also can be etched, and form a gap 100 between protective layer 34 and the first metal layer 84.
In addition, after finishing the structure shown in Fig. 6 j, then cut the most semiconductor subassemblies of these semiconductor-based end 10 formation, and all can using routing manufacture method, winding to engage manufacture method, glass flip chip encapsulation technology and film compound crystal joining technique automatically, each semiconductor subassembly is connected on the external circuitry, wherein the process of Jie Heing explains orally in first embodiment, in this just not repeat specification.
The 6th embodiment
This embodiment is similar to the 5th embodiment, and difference is to form three metal levels on the Seed Layer 92 that opening 96 exposed.See also shown in Fig. 7 a, after finishing the structure shown in Fig. 6 h, then form one four metal level 102 of thickness between 0.1 micron to 10 microns on the Seed Layer 92 that opening 96 is exposed, for example electroplate a bronze medal metal on the Seed Layer 92 that opening 96 is exposed in the mode of electroplating.See also again shown in Fig. 7 b, equally with the mode of electroplating form thickness between one the 5th metal level 104 between 0.1 micron to 10 microns on the 4th metal level 102, for example electroplate a nickel metal on the 4th metal level 102.Continue to see also shown in Fig. 7 c, with electroplate or the mode of electroless-plating form thickness between one the 6th metal level 106 between 0.1 micron to 10 microns on the 5th metal level 104, this the 6th metal level 106 is such as the single-layer metal layer structure that is gold, copper, silver, palladium, platinum, rhodium, ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only the 6th metal level 106 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be leypewter layer, sn-ag alloy layer, SAC alloy-layer, lead-free solder layer.If this 6th metal level 106 is the scolder material, then the preferred thickness of the 6th metal level 106 is between 3 microns to 150 microns.
At last, shown in Fig. 7 d, remove photoresist layer 94 and not Seed Layer under the 6th metal level 106 92 and the first metal layer 90, and on the mode of removing the first metal layer 90 and Seed Layer 92, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under the 6th metal level 106 92 and the first metal layer 90, and when carrying out Wet-type etching if Seed Layer 92 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 90 is titanium-tungsten, then can use hydrogen peroxide to remove.
In addition, after finishing the structure shown in Fig. 7 d, then cut the most semiconductor subassemblies of these semiconductor-based end 10 formation, and all can using routing manufacture method, winding to engage manufacture method, glass flip chip encapsulation technology and film compound crystal joining technique automatically, each semiconductor subassembly is connected on the external circuitry, wherein the process of Jie Heing explains orally in first embodiment, in this just not repeat specification.
The 7th embodiment
This embodiment is the application of first embodiment on connection line (interconnection), so for making the structure letter understandable, only show the schematic diagram that two copper connection pads 32 utilize a metallic circuit to link together, and do following explanation, but can not limit the present invention with this with this.
See also shown in Fig. 8 a, the thin on-line composition 14 in the semiconductor substrate 10 has two bronze medal connection pads 32, is respectively the first bronze medal connection pad 320 and the second bronze medal connection pad 322.Then see also shown in Fig. 8 b; form a polymeric layer 108 at protective layer 34; on the first bronze medal connection pad 320 and the second bronze medal connection pad 322; wherein this polymeric layer 108 has insulation function; its material is such as being thermoplastics; thermoset plastics; polyimide (polyimide; PI); benzyl ring butylene (benzo-cyclo-butene; BCB); polyurethane (polyurethane); epoxy resin; the Parylene family macromolecule; the weldering cover material; elastomeric material or porousness dielectric material; this polymeric layer 108 mainly is to utilize the spin coating mode to be provided with in addition, so also can utilize hot pressing dry film or screen painting mode to carry out.
Continue to see also shown in Fig. 8 c, utilize etching mode that this polymeric layer 108 is carried out patterning, expose the first bronze medal connection pad 320 and the second bronze medal connection pad 322 respectively to form most first openings 110 and second opening 112, wherein, when polymeric layer 108 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with polymeric layer 108 patternings; When polymeric layer 108 is non-sensitization material, then such as utilizing lithography manufacture method (photolithography process and etchingprocess), with polymeric layer 108 patternings.After polymeric layer 108 patternings, can utilize baking heating, microwave heating, infrared ray to heat one of them mode and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 108 that hardens.
See also again shown in Fig. 8 d, utilize sputter, the mode of plating or chemical vapour deposition (CVD) forms a first metal layer 114 at the first bronze medal connection pad 320, on the second bronze medal connection pad 322 and the polymeric layer 108 (or comprising on the part protective layer 34), the material of this first metal layer 114 is to be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them, then utilize sputter equally, the mode of plating or chemical vapour deposition (CVD) forms a Seed Layer 116 on the first metal layer 114, this Seed Layer 116 helps the setting of subsequent metal layer, therefore the material of Seed Layer 116 can change to some extent with follow-up metal level material, for example when on the Seed Layer 116 being the metal level of the golden material of plating formation, the material of Seed Layer 116 is with Jin Weijia; In the time will electroplating the metal level that forms silver-colored material, the material of Seed Layer 116 is to be good with silver; When being when electroplate forming the metal level of copper material on the Seed Layer 116, the material of Seed Layer 116 is to be good with copper; In the time will electroplating the metal level that forms the palladium material, the material of Seed Layer 116 is to be good with palladium; In the time will electroplating the metal level that forms platinum product matter, the material of Seed Layer 116 is to be good with platinum; In the time will electroplating the metal level that forms the rhodium material, the material of Seed Layer 116 is to be good with rhodium; In the time will electroplating the metal level that forms the ruthenium material, the material of Seed Layer 116 is to be good with ruthenium; In the time will electroplating the metal level that forms the rhenium material, the material of Seed Layer 116 is to be good with rhenium; In the time will electroplating the metal level that forms the nickel material, the material of Seed Layer 116 is to be good with nickel.
Come again, see also shown in Fig. 8 e, utilize the mode of spin coating (spin-coating) to form a photoresist layer 118 on Seed Layer 116, the pattern of this photoresist layer 118 is to be positive photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Continue to see also shown in Fig. 8 f, this photoresist layer 118 of patterning exposes with formation opening 120 and is positioned on the first bronze medal connection pad 320, on the second bronze medal connection pad 322 and the Seed Layer 116 between the first bronze medal connection pad 320 and the second bronze medal connection pad 322, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening 120, then when photoresist layer 118 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), photoresist layer 118 patternings are formed most openings 120, and when photoresist layer 118 is non-sensitization material, then, photoresist layer 118 patternings are formed most openings 120 such as utilizing lithography manufacture method (photolithography processand etching process).
In addition, forming on photoresist layer 118 and the opening 120 thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 118, if wherein forming 118 of photoresist layers in the screen painting mode can directly form most openings 120 and expose Seed Layer 116 in photoresist layer 118, if so form photoresist layer 118 in hot pressing dry film mode, then can be after forming photoresist layer 118, form most openings 120 again and expose Seed Layer 116, but also can be directly in photoresist layer 118, form most openings 120 and expose Seed Layer 116.
Then see also shown in Fig. 8 g, mode with plating or electroless-plating forms one second metal 122 on the Seed Layer 116 that opening 120 is exposed, these second metal level, 122 preferable thickness are between 2 microns to 10 microns, and this second metal level 122 is such as being gold, copper, silver, palladium, platinum, rhodium, the single-layer metal layer structure of ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only second metal level 122 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be the leypewter layer, the sn-ag alloy layer, the SAC alloy-layer, the lead-free solder layer.If this second metal level 122 is the scolder material, then the preferred thickness of second metal level 122 is between 3 microns to 150 microns.
Continue to see also shown in Fig. 8 h, remove photoresist layer 118 and not Seed Layer under second metal level 122 116 and the first metal layer 114, and on the mode of removing the first metal layer 114 and Seed Layer 116, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 122 116 and the first metal layer 114, and when carrying out Wet-type etching if Seed Layer 116 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 114 is titanium-tungsten, then can use hydrogen peroxide to remove.
Therefore, shown in Fig. 8 h, the metallic circuit 124 that is formed by left the first metal layer 114, Seed Layer 116 and second metal level 122 connects the first bronze medal connection pad 320 and the second bronze medal connection pad 322, and the first bronze medal connection pad 320 and the second bronze medal connection pad 322 are electrically connected.
In addition, see also Fig. 8 i, form a polymeric layer 126 on metallic circuit 124 and polymeric layer 108, wherein this polymeric layer 126 has insulation function, its material is such as being thermoplastics, thermoset plastics, polyimide (polyimide, PI), benzyl ring butylene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy resin, the Parylene family macromolecule, the weldering cover material, elastomeric material or porousness dielectric material, this polymeric layer 126 mainly is to utilize the spin coating mode to be provided with in addition, so also can utilize hot pressing dry film or screen painting mode to carry out.
Continue to see also shown in Fig. 8 j, utilize etching mode that this polymeric layer 126 is carried out patterning, to form second metal level 122 that most openings 128 expose metallic circuit 124, wherein, when polymeric layer 126 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with polymeric layer 126 patternings; When polymeric layer 126 is non-sensitization material, then such as utilizing lithography manufacture method (photolithography process and etching process), with polymeric layer 126 patternings.After polymeric layer 126 patternings, can utilize baking heating, microwave heating, infrared ray to heat one of them mode and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 126 that hardens.
See also Fig. 8 k at last, carry out cutting semiconductor substrate 10 and form most semiconductor subassemblies 52, and form routing lead 130 on the end face of second metal level 122 of exposing metallic circuit 124 by the routing manufacture method, make semiconductor subassembly 52 be electrically connected to external circuitry, when wherein serving as gold layer, platinum layer or palladium layer, be for carrying out the preferable material of routing manufacture method with second metal level 122.
The mode that present embodiment forms connection line (interconnection) also can be applicable on second embodiment to the, six embodiment,, does not only narrate in detail once more with explanation this spy.
The 8th embodiment
This embodiment is to serve as the explanation target to form passive component on the semiconductor-based end 10, and wherein this passive component for example is inductance (coil) assembly, resistor assembly, capacitance component etc., and has copper connection pad 32 on this semiconductor-based end 10.See also shown in Fig. 9 a; utilize spin coating (spin-coating) mode to form a polymeric layer 132 on protective layer 34; this polymeric layer 132 has insulation function; and the material of this polymeric layer 132 is to be selected from material such as being thermoplastics, thermoset plastics, polyimide (polyimide; PI), the benzyl ring butylene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy resin, Parylene family macromolecule, weldering cover material, elastomeric material or porousness dielectric material one of them.In addition, this polymeric layer 132 also can utilize hot pressing dry film mode, screen painting mode to carry out except utilizing spin coating (spin-coating) mode, and the thickness of this polymeric layer 132 is between 2 microns to 50 microns.
Then polymeric layer 132 is heated one of them mode with baking heating, microwave heating, infrared ray and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 132 that hardens.
See also shown in Fig. 9 b, utilize sputter again, the mode of plating or chemical vapour deposition (CVD) forms a first metal layer 134 on polymeric layer 132, the material of this first metal layer 134 is to be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them, then utilize sputter equally, the mode of plating or chemical vapour deposition (CVD) forms a Seed Layer 136 on the first metal layer 134, this Seed Layer 136 helps the setting of subsequent metal layer, therefore the material of Seed Layer 136 can change to some extent with follow-up metal level material, for example when on the Seed Layer 136 being the metal level of the golden material of plating formation, the material of Seed Layer 136 is with Jin Weijia; In the time will electroplating the metal level that forms silver-colored material, the material of Seed Layer 136 is to be good with silver; When being when electroplate forming the metal level of copper material on the Seed Layer 136, the material of Seed Layer 136 is to be good with copper; In the time will electroplating the metal level that forms the palladium material, the material of Seed Layer 136 is to be good with palladium; In the time will electroplating the metal level that forms platinum product matter, the material of Seed Layer 136 is to be good with platinum; In the time will electroplating the metal level that forms the rhodium material, the material of Seed Layer 136 is to be good with rhodium; In the time will electroplating the metal level that forms the ruthenium material, the material of Seed Layer 136 is to be good with ruthenium; In the time will electroplating the metal level that forms the rhenium material, the material of Seed Layer 136 is to be good with rhenium; In the time will electroplating the metal level that forms the nickel material, the material of Seed Layer 136 is to be good with nickel.
Continue to see also shown in Fig. 9 c, utilize the mode of spin coating (spin-coating) to form a photoresist layer 138 on Seed Layer 136, the pattern of this photoresist layer 138 is to be positive photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Then see also shown in Fig. 9 d, this photoresist layer 138 of patterning exposes Seed Layer 136 with the opening 140 that forms a coil shape, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening 140, then when photoresist layer 138 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), photoresist layer 138 patternings are formed the opening 140 of coil shape, and when photoresist layer 138 is non-sensitization material, then, photoresist layer 138 patternings are formed the opening 140 of coil shape such as utilizing lithography manufacture method (photolithographyprocess and etching process).
In addition, on the opening 140 that forms photoresist layer 138 and coil shape thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 138, if wherein form photoresist layer 138 in the screen painting mode, then can directly in photoresist layer 138, form the opening 140 of coil shape and expose Seed Layer 136, if so form photoresist layer 138 in hot pressing dry film mode, then can be after forming photoresist layer 138, the opening 140 that forms coil shape again exposes Seed Layer 136, but also can be directly forms the opening 140 of coil shape and expose Seed Layer 136 in photoresist layer 138.
Then see also shown in Fig. 9 e, with electroplate or the mode of electroless-plating form thickness greater than 1 micron one second metal level 142 on the Seed Layer 136 that opening 140 is exposed, these second metal level, 142 preferable thickness are between 2 microns to 30 microns, and this second metal level 142 is such as being gold, copper, silver, palladium, platinum, rhodium, the single-layer metal layer structure of ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only second metal level 142 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be the leypewter layer, the sn-ag alloy layer, the SAC alloy-layer, the lead-free solder layer.If this second metal level 142 is the scolder material, then the preferred thickness of second metal level 142 is between 3 microns to 150 microns.
See also shown in Fig. 9 f, remove photoresist layer 138 and not Seed Layer under second metal level 142 136 and the first metal layer 134 at last, and on the mode of removing the first metal layer 134 and Seed Layer 136, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 142 136 and the first metal layer 134, and when carrying out Wet-type etching if Seed Layer 136 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 134 is titanium-tungsten, then can use hydrogen peroxide to remove.
Therefore; the second left metal level 142, Seed Layer 136 and the first metal layer 134 promptly form a metallic circuit 144 that is coil shape; shown in 9g figure; the metallic circuit 144 of this coil shape can be made the inductance in the passive component; when the metallic circuit 144 of this coil shape passes through electric current; promptly produce induced electromotive force, make wiring thin film layer 18 induction of protective layer 34 belows.In addition, at this metallic circuit 144 that this coil shape is described (feeding electric current) in use, can produce a large amount of static, be approximately 1500 volts (V), because polymeric layer 132 must have thickness to a certain degree, can prevent that just wiring thin film layer 18 and thin dielectric film 16 from damaging.
Come again, shown in Fig. 9 h, form a polymeric layer 146 on metallic circuit 144 and polymeric layer 132, wherein this polymeric layer 146 has insulation function, its material is such as being thermoplastics, thermoset plastics, polyimide (polyimide, PI), benzyl ring butylene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy resin, the Parylene family macromolecule, the weldering cover material, elastomeric material or porousness dielectric material, this polymeric layer 146 mainly is to utilize the spin coating mode to be provided with in addition, so also can utilize hot pressing dry film or screen painting mode to carry out.
Continue to see also shown in Fig. 9 i, utilize etching mode that this polymeric layer 146 is carried out patterning, to form second metal level 142 that most openings 148 expose metallic circuit 144, wherein, when polymeric layer 146 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with polymeric layer 146 patternings; When polymeric layer 146 is non-sensitization material, then such as utilizing lithography manufacture method (photolithography process and etching process), with polymeric layer 146 patternings.After polymeric layer 146 patternings, can utilize baking heating, microwave heating, infrared ray to heat one of them mode and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 146 that hardens.
See also Fig. 9 j at last, carry out cutting semiconductor substrate 10 and form most semiconductor subassemblies 52, and form routing lead 150 on the end face of second metal level 142 of exposing metallic circuit 144 by the routing manufacture method, make semiconductor subassembly 52 be electrically connected to external circuitry, when wherein serving as gold layer, platinum layer or palladium layer, be for carrying out the preferable material of routing manufacture method with second metal level 142.
Only the mode of the metallic circuit of present embodiment formation coiled type also can be applicable on second embodiment to the, six embodiment,, does not only narrate in detail once more with explanation this spy.
The 9th embodiment
This embodiment be for first embodiment in the application of reshuffling on the circuit (RDL), so for making structure letter understandable, only show a bronze medal connection pad and utilize a metallic circuit to be connected to the schematic diagram of a pair of outer connection pad, and do following explanation with this.
See also shown in Figure 10 a; after forming protective layer 34; then form thickness between the polymeric layer 152 between 3 microns to 50 microns on this protective layer 34 and copper connection pad 32; this polymeric layer 152 has insulation function; and the material of this polymeric layer 152 is to be selected from material such as being thermoplastics; thermoset plastics; polyimide (polyimide; PI); benzyl ring butylene (benzo-cyclo-butene; BCB); polyurethane (polyurethane); epoxy resin; the Parylene family macromolecule; the weldering cover material; elastomeric material or porousness dielectric material; this polymeric layer 152 mainly is to utilize the spin coating mode to be provided with in addition, also can utilize hot pressing dry film or screen painting mode to carry out in addition.
Then shown in Figure 10 b, utilize etching mode that this polymeric layer 152 is carried out patterning, expose copper connection pad 32 to the open air to form most openings 154.Wherein it should be noted that when polymeric layer 152 be during for the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with polymeric layer 152 patternings; When polymeric layer 152 is during for non-sensitization material, then such as utilizing lithography manufacture method (photolithography process and etching process), with polymeric layer 152 patternings.After polymeric layer 152 patternings, can utilize baking heating, microwave heating, infrared ray to heat one of them mode and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 152 that hardens.
Continue to see also shown in Figure 10 c, utilize sputter, the mode of plating or chemical vapour deposition (CVD) forms a first metal layer 156 on polymeric layer 152, the material of this first metal layer 156 is to be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them, then utilize sputter equally, the mode of plating or chemical vapour deposition (CVD) forms a Seed Layer 158 on the first metal layer 156, this Seed Layer 158 helps the setting of subsequent metal layer, therefore the material of Seed Layer 158 can change to some extent with follow-up metal level material, for example when on the Seed Layer 158 being the metal level of the golden material of plating formation, the material of Seed Layer 158 is with Jin Weijia; In the time will electroplating the metal level that forms silver-colored material, the material of Seed Layer 158 is to be good with silver; When being when electroplate forming the metal level of copper material on the Seed Layer 158, the material of Seed Layer 158 is to be good with copper; In the time will electroplating the metal level that forms the palladium material, the material of Seed Layer 158 is to be good with palladium; In the time will electroplating the metal level that forms platinum product matter, the material of Seed Layer 158 is to be good with platinum; In the time will electroplating the metal level that forms the rhodium material, the material of Seed Layer 158 is to be good with rhodium; In the time will electroplating the metal level that forms the ruthenium material, the material of Seed Layer 158 is to be good with ruthenium; In the time will electroplating the metal level that forms the rhenium material, the material of Seed Layer 158 is to be good with rhenium; In the time will electroplating the metal level that forms the nickel material, the material of Seed Layer 158 is to be good with nickel.
Continue to see also shown in Figure 10 d, utilize the mode of spin coating (spin-coating) to form a photoresist layer 160 on Seed Layer 158, the pattern of this photoresist layer 160 is to be positive photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Then see also shown in Figure 10 e, this photoresist layer 160 of patterning is to form opening 162 and expose the Seed Layer 158 that is positioned on the copper connection pad 32 and to be positioned at Seed Layer 158 on the other part polymeric layer 152 of copper connection pad 32, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening 162, then when photoresist layer 160 is the sensitization material, then such as utilizing little shadow manufacture method (photolithographyprocess), photoresist layer 160 patternings are formed opening 162, and when photoresist layer 160 is non-sensitization material, then, photoresist layer 160 patternings are formed opening 162 such as utilizing lithography manufacture method (photolithography process and etching process).
In addition, forming on photoresist layer 160 and the opening 162 thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 160, if wherein form photoresist layer 160 in the screen painting mode, then can directly in photoresist layer 160, form opening 162 and expose Seed Layer 158, if so form photoresist layer 160 in hot pressing dry film mode, then can be after forming photoresist layer 160, form opening 162 again and expose Seed Layer 158, but also can be directly in photoresist layer 160, form opening 162 and expose Seed Layer 158.
See also again shown in Figure 10 f, with electroplate or the mode of electroless-plating form thickness greater than 1 micron one second metal level 164 on the Seed Layer 158 that opening 162 is exposed, these second metal level, 164 preferable thickness are between 2 microns to 30 microns, and this second metal level 164 is such as being gold, copper, silver, palladium, platinum, rhodium, the single-layer metal layer structure of ruthenium or rhenium, or the composite bed of forming by above-mentioned metal material, only second metal level 164 also can use solder material to replace except the above-mentioned metal material of carrying, and this solder material is to be the leypewter layer, the sn-ag alloy layer, the SAC alloy-layer, the lead-free solder layer.If this second metal level 164 is the scolder material, then the preferred thickness of second metal level 164 is between 3 microns to 150 microns.
See also shown in Figure 10 g, remove photoresist layer 160 and not Seed Layer under second metal level 164 158 and the first metal layer 156 at last, and on the mode of removing the first metal layer 156 and Seed Layer 158, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under second metal level 164 158 and the first metal layer 156, and when carrying out Wet-type etching if Seed Layer 158 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 156 is titanium-tungsten, then can use hydrogen peroxide to remove.
Therefore, form a metallic circuit 166 by the second left metal level 164, Seed Layer 158 with 156 of the first metal layers, a that is reconfiguration line layer, noticeable characteristics be this embodiment mainly be formed on metallic circuit 166 on the opening 154 and extend to the part polymeric layer 152 on, be not simplex on opening 154, the metallic circuit 166 that is extended then helps the setting of follow-up circuit.
Come again, see also shown in Figure 10 h, form a polymeric layer 168 on metallic circuit 166 and polymeric layer 152, wherein this polymeric layer 168 has insulation function, its material is such as being thermoplastics, thermoset plastics, polyimide (polyimide, PI), benzyl ring butylene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy resin, the Parylene family macromolecule, the weldering cover material, elastomeric material or porousness dielectric material, this polymeric layer 168 mainly is to utilize the spin coating mode to be provided with in addition, so also can utilize hot pressing dry film or screen painting mode to carry out.
Continue to see also shown in Figure 10 i, utilize etching mode that this polymeric layer 168 is carried out patterning, to form second metal level 164 that most openings 170 expose metallic circuit 166, wherein when polymeric layer 168 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with polymeric layer 168 patternings; When polymeric layer 168 is non-sensitization material, then such as utilizing lithography manufacture method (photolithography process and etching process), with polymeric layer 168 patternings.After polymeric layer 168 patternings, can utilize baking heating, microwave heating, infrared ray to heat one of them mode and be heated between the temperature between 200 degree Celsius and 320 degree Celsius or be heated to temperature between 320 degree Celsius are spent with Celsius 450, with (curing) polymeric layer 168 that hardens.In addition, second metal level, 164 end faces of the metallic circuit 166 that is exposed by opening 170 are promptly as a pair of outer connection pad, this external connection pad sees through metallic circuit 166 and is connected to copper connection pad 32, sees it from birds-eye perspective in addition, and the position of this external connection pad is the position that is different from copper connection pad 32.
See also Figure 10 j, carry out cutting semiconductor substrate 10 at last and form most semiconductor subassemblies 52, and form routing lead 172 on external connection pad by the routing manufacture method, make semiconductor subassembly 52 be electrically connected to external circuitry, when wherein serving as gold layer, platinum layer or palladium layer, be for carrying out the preferable material of routing manufacture method with second metal level 164.
The thought present embodiment forms the mode of reshuffling circuit (RDL) and also can be applicable on second embodiment to the, six embodiment,, does not only narrate in detail once more with explanation this spy.
The tenth embodiment
This embodiment is similar to the 9th embodiment, and difference is that external connection pad is to be used for connecting height greater than one of 8 microns golden projections.See also shown in Figure 11 a, after finishing the structure shown in Figure 10 i, then utilize sputter, the mode of plating or chemical vapour deposition (CVD) forms a first metal layer 174 on polymeric layer 168 and second metal level, 164 end faces as external connection pad, the material of this first metal layer 174 is to be selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium-tungsten, vanadium, chromium, chrome copper, copper, tantalum and tantalum nitride one of them or the group that formed at least one of them, then utilize sputter equally, the mode of plating or chemical vapour deposition (CVD) forms a Seed Layer 176 on the first metal layer 174, this Seed Layer 176 helps the setting of subsequent metal layer, therefore the material of Seed Layer 176 can change to some extent with follow-up metal level material, for example when on the Seed Layer 176 being the metal level of the golden material of plating formation, the material of Seed Layer 176 is with Jin Weijia; In the time will electroplating the metal level that forms silver-colored material, the material of Seed Layer 176 is to be good with silver; When being when electroplate forming the metal level of copper material on the Seed Layer 176, the material of Seed Layer 176 is to be good with copper; In the time will electroplating the metal level that forms the palladium material, the material of Seed Layer 176 is to be good with palladium; In the time will electroplating the metal level that forms platinum product matter, the material of Seed Layer 176 is to be good with platinum; In the time will electroplating the metal level that forms the rhodium material, the material of Seed Layer 176 is to be good with rhodium; In the time will electroplating the metal level that forms the ruthenium material, the material of Seed Layer 176 is to be good with ruthenium; In the time will electroplating the metal level that forms the rhenium material, the material of Seed Layer 176 is to be good with rhenium; In the time will electroplating the metal level that forms the nickel material, the material of Seed Layer 176 is to be good with nickel.
Come again, see also shown in Figure 11 b, utilize the mode of spin coating (spin-coating) to form a photoresist layer 178 on Seed Layer 176, the pattern of this photoresist layer 178 is to be positive photoresistance pattern, its material can be the sensing optical activity material of nonionic (nonionic) or ester class (ester-type), perhaps is non-sensing optical activity material.Continue to see also shown in Figure 11 c, this photoresist layer 178 of patterning exposes the Seed Layer 176 that is positioned on the external connection pad to form opening 180, wherein be that stepping exposure machine (steppers) or scanning machine (scanners) with 1 times (1X) carries out exposure imaging in forming the process of opening 180, then when photoresist layer 178 is the sensitization material, then such as utilizing little shadow manufacture method (photolithography process), with photoresist layer 178 patternings, and when photoresist layer 178 is non-sensitization material, then such as utilizing lithography manufacture method (photolithography process andetching process), with photoresist layer 178 patternings.
In addition, forming on photoresist layer 178 and the opening 180 thereof, the present invention also can utilize the mode of screen painting or hot pressing dry film to form photoresist layer 178, if wherein forming 178 of photoresist layers in the screen painting mode can directly form opening 180 and expose Seed Layer 176 in photoresist layer 178, if so form photoresist layer 178 in hot pressing dry film mode, then can be after forming photoresist layer 178, form opening 180 again and expose Seed Layer 176, but also can be directly in photoresist layer 178, form opening 180 and expose Seed Layer 176.
Then see also shown in Figure 11 d, with the mode of electroplating form height greater than one of 8 microns metal couplings 182 on the Seed Layer 176 that opening 180 is exposed, this metal coupling 182 is such as the single-layer metal layer structure that is gold, copper, silver, palladium, platinum, rhodium, ruthenium or rhenium, or the composite bed of being made up of above-mentioned metal material.
At last, shown in Figure 11 e, remove photoresist layer 178 and not Seed Layer under metal coupling 182 176 and the first metal layer 174, and on the mode of removing the first metal layer 174 and Seed Layer 176, can be divided into dry-etching and Wet-type etching, wherein dry-etching is to use the high pressure argon gas to splash etching and removes not Seed Layer under metal coupling 182 176 and the first metal layer 174, and when carrying out Wet-type etching if Seed Layer 176 during for the Seed Layer of gold, then can use liquor kalii iodide to remove, if when the first metal layer 174 is titanium-tungsten, then can use hydrogen peroxide to remove.Other, metal coupling 182 can utilize the routing joint, the technology such as the automatic joint of band, film compound crystal joint or glass compound crystal joint of pasting are bonded on the extraneous substrate.Therefore, copper connection pad 32 can see through metallic circuit 166 and connect external connection pad, and utilizes the metal coupling of external electrical connection height greater than 8 microns, and then electrically connects extraneous substrate.
In addition, if the structure shown in Figure 11 e is to form height in the mode of electroplating to contain tin projection 184 on external connection pad greater than one of 10 microns, and afterwards, contains tin projection 184 and be the shape shown in Figure 11 f and be connected with external connection pad through reflow (re-flow).
The 11 embodiment
See also shown in Figure 12 b to Figure 12 i, its be form Figure 12 a structure in each step of process corresponding structural profile show view.
At first, see also shown in Figure 12 b, semiconductor substrate 10 is provided, include plural circuit unit 12 on this semiconductor-based end 10, as: transistor, internal memory and/or logic module, plural thin dielectric film 16 and plural thin film wire curb layer 18, these a little wiring thin film layers 18 can see through plural vias 24 in the thin dielectric film 16 and be communicated with the wiring thin film layer 18 between the adjacent two layers or be connected on the corresponding electronic building brick 12.In addition, a plurality of copper connection pads 324,326,328 are formed on the top surface at the semiconductor-based end 10, and these a little copper connection pads the 324,326, the 328th are the some of wiring thin film layer 18 top surface at the semiconductor-based end 10, can be respectively electrically connect, and similarly the lower surface and the sidewall of these a little copper connection pads 324,326,328 all are coated with barrier layer 26 and Seed Layer 28 with the integrated circuit of bottom.
One protective layer 34 is the top surfaces that cover the inorganic protective layer 20 at the semiconductor-based end 10, and copper connection pad the 324,326, the 328th, respectively by the opening on the protective layer 34 340,342,344 with outside partly being exposed to.Generally speaking, the maximum transverse size of opening 340,342,344 is approximately between 0.5 to 15 micron, and in other enforcement aspect, the maximum transverse size of opening 340,342,344 also can be between 15 to 300 microns.
Forming a first metal layer 186 covers on the copper connection pad 324,326,328 that protective layer 34 top surfaces and opening 340,342,344 exposed; the profile of this first metal layer 186 is to meet with the top surface of protective layer 34 and the profile phase of opening 340,342,344 in addition, and more with 340,342,344 sealings of above-mentioned plurality of openings.Wherein, the preferred thickness of the first metal layer 186 is between 0.1 to 10 micron.
According to present embodiment, the material that can be used for the first metal layer 186 comprises: titanium, tungsten, cobalt, nickel, titanium nitride, tungsten nitride, vanadium, chromium, copper, chromium-copper, tantalum, tantalum nitride, the formed alloy of above-mentioned material, or the composite bed that combines of above-mentioned material.Subsequently, a Seed Layer (seed layer) the 188th optionally is formed on this first metal layer 186 tops.
Continue, please refer to shown in Figure 12 c, one patterning photoresist layer 190 is formed on the Seed Layer 188, and this patterning photoresist layer 190 is to form by the manufacture method mode of general little shadow imaging (lithography), generally speaking, little shadow imaging manufacture method is to include following steps: photoresistance coating, photoresistance baking, exposure and development, wherein, above-mentioned photoresistance is the film that can be a drying.This patterning photoresist layer 190 has plurality of openings 192a, 192b, 192c, opening 192a is the top that is formed directly into copper connection pad 324 in addition, opening 192b is the top that is formed directly into copper connection pad 326, it is to reshuffle the required irrigation canals and ditches position of circuit (RDL) in order to define to form, and opening 192c then is the top that is formed directly into copper connection pad 328.
Come again, see also Figure 12 d, on opening 192a, 192b, 192c, form the second metal level 194a, 194b, 194c respectively with the manufacture method of electroplating, for example electroplate and form a bronze medal layer, and the thickness of this second metal level 194a, 194b, 194c is between 0.1 to 10 micron, and in other enforcement aspect, the second above-mentioned metal level 194a, the thickness of 194b, 194c can be between 10 to 250 microns.Subsequently, once electroplate manufacture method again on the second metal level 194a, 194b, 194c, to form the 3rd metal level 196a, 196b, 196c respectively, for example electroplate and form a nickel dam, and this 3rd metal level 196a, 196b, 196c be the second metal level 194a that can avoid its below, the surface of 194b, 194c the situation of oxidation takes place, simultaneously, also can provide a powerful function that blocks.Carry out so far, above-mentioned patterning photoresist layer 190 can be removed it.
Continue to see also shown in Figure 12 e, form another patterning photoresist layer 198 at Seed Layer 188 and the 3rd metal level 196a, 196b, on the 196c, and above copper connection pad 324, this patterning photoresist layer 198 is formed with an opening 200a, yet, be positioned at the not direct top of opening 200b of this patterned light blockage layer 198 in alignment with copper connection pad 326, wherein, by opening 200a is to allow the top surface of the 3rd metal level 196a manufacture method of exposing, opening 200b then be can be on the 3rd metal level 196b the preselected manufacture method of exposing in the zone of reshuffling.Then see also Figure 12 f, electroless-plating the 4th metal level 202a, 202b are respectively formed among opening 200a, the 200b, this the 4th metal level 202a, 202b be such as the material that is gold, silver, palladium, platinum, rhodium, ruthenium, rhenium, yet the formation of this electroless plating the 4th metal level 202a, 202b is for optionally.Subsequently, electroplating the 5th metal level 204a, 204b is respectively formed on the 4th metal level 202a, the 202b.Carry out so far, above-mentioned patterning photoresist layer 198 can be removed it.
Then please refer to shown in Figure 12 g, form a photoresist layer 206 on Seed Layer 188, part the 3rd metal level 196b, the 3rd metal level 196c and the 5th metal level 204a, 204b, see also Figure 12 h again, this photoresist layer 206 of patterning exposes the 3rd metal level 196c to form opening 208, wherein this opening 208 is the tops that are formed at copper connection pad 328, and makes the manufacture method of can exposing on the top surface of the 3rd metal level 196c.Then see also Figure 12 i, in opening 208, a metal coupling 210 is formed on the 3rd metal level 196c top of having exposed, and wherein this material that belongs to projection 210 is leypewter, sn-ag alloy, SAC alloy.Carry out so far, above-mentioned patterning photoresist layer 206 can be removed it, and last not Seed Layer under the second metal level 194a, 194b, 194c 188 and the first metal layer 186 removals more promptly form the structure shown in 12a figure.
In addition, relevant the first metal layer 186, Seed Layer 188, the photoresist layer 190,198,206 of forming in the present embodiment, and patterning photoresist layer 190,198,206 with remove that the Seed Layer 188 under the second metal level 194a, 194b, 194c is all not identical with the various embodiments described above with the mode of the first metal layer 186, do not narrate in detail once more at this.
The present invention on the copper connection pad of the semiconductor-based end (wafer) by electroplating or the mode of electroless-plating, produced the multiple layer metal layer structure of many different kenels, and form the external contact point structure of various differences, such as forming connection pad (pad), projection (bump) etc., this connection pad and projection all can see through routing or anisotropic conductive is electrically connected on the external circuitry, makes the application of semiconductor subassembly have more the diversification connected mode.In addition, the narration of relevant above-mentioned various embodiment also can be applicable on the aluminium connection pad except can being applied in the copper connection pad,, but does not set forth in detail once more with explanation this spy.
In sum; by embodiment characteristics of the present invention are described; its purpose makes the common those skilled in the art that are familiar with this field separate content of the present invention and enforcement according to this by Liao; and the claim protection range of non-limiting patent of the present invention; so; all other do not break away from equivalence modification or the modification that disclosed spirit is finished, and must be included in the claim scope of the following stated.

Claims (30)

1. a circuit assembly structure is characterized in that, comprising:
The semiconductor substrate;
At least one copper connection pad was positioned on this semiconductor-based end;
One protective layer was positioned on this semiconductor-based end, and at least one opening that is positioned at this protective layer exposes this copper connection pad; And
One gold medal layer is positioned on this copper connection pad, and thickness that should the gold layer is greater than 1.6 microns.
2. according to circuit assembly structure as claimed in claim 1, it is characterized in that, comprise that also complex dielectric constant value (k) is between 1.5 to 3 thin dielectric film and plural wiring thin film layer, be positioned on this semiconductor-based end, those wiring thin film layers and see through those wiring thin film layers of the plural via connection adjacent two layers be positioned at those thin dielectric films between those thin dielectric films.
3. according to circuit assembly structure as claimed in claim 1, it is characterized in that, also comprise containing lower surface and the sidewall that one of tantalum metal level coats this copper connection pad.
4. according to circuit assembly structure as claimed in claim 1; it is characterized in that; this protective layer comprises one first nitrogen silicon compound layer, one of be positioned on this first nitrogen silicon compound layer the oxygen silicon compound layer and be positioned at one second nitrogen silicon compound layer on this oxygen silicon compound layer, and wherein the thickness of this first nitrogen silicon compound layer, this oxygen silicon compound layer and this second nitrogen silicon compound layer is between 0.2 micron to 1.2 microns.
5. according to circuit assembly structure as claimed in claim 1, it is characterized in that this protective layer comprises the nitrogen silicon compound layer of thickness between 0.2 micron to 1.2 microns.
6. according to circuit assembly structure as claimed in claim 1, it is characterized in that this protective layer comprises the nitrogen-oxygen-silicon compound layer of thickness between 0.05 micron to 0.15 micron.
7. according to circuit assembly structure as claimed in claim 1; it is characterized in that this protective layer comprises a nitrogen-oxygen-silicon compound layer, be positioned at one first oxygen silicon compound layer on this nitrogen-oxygen-silicon compound layer, be positioned at the nitrogen silicon compound layer on this first oxygen silicon compound layer and one of be positioned on this nitrogen silicon compound layer the second oxygen silicon compound layer.
8. according to circuit assembly structure as claimed in claim 1, it is characterized in that, comprise that also thickness is the nickel dam between 0.1 micron to 10 microns, between this gold layer and this copper connection pad.
9. according to circuit assembly structure as claimed in claim 1, it is characterized in that, comprise that also thickness is the bronze medal layer between 0.1 micron to 10 microns, between this gold layer and this copper connection pad.
10. according to circuit assembly structure as claimed in claim 1, it is characterized in that, also comprise a titanium layer, titanium nitride layer, a titanium-tungsten layer, a chrome copper layer, a tantalum layer or tantalum nitride layer one of them, between this gold layer and this copper connection pad.
11. a circuit assembly structure is characterized in that, comprising:
The semiconductor substrate;
One first bronze medal connection pad was positioned on this semiconductor-based end;
One protective layer was positioned on this semiconductor-based end, and was positioned at one of this protective layer first opening and exposes this first bronze medal connection pad; And
One metallic circuit is positioned on this protective layer, and this metallic circuit comprises a gold medal layer.
12. according to circuit assembly structure as claimed in claim 11, it is characterized in that, comprise that also complex dielectric constant value (k) is between 1.5 to 3 thin dielectric film and plural wiring thin film layer, be positioned on this semiconductor-based end, those wiring thin film layers and see through those wiring thin film layers of the plural via connection adjacent two layers be positioned at those thin dielectric films between those thin dielectric films.
13. according to circuit assembly structure as claimed in claim 11, it is characterized in that, also comprise containing lower surface and the sidewall that one of tantalum metal level coats this copper connection pad.
14. according to circuit assembly structure as claimed in claim 11; it is characterized in that; this protective layer comprises one first nitrogen silicon compound layer, one of be positioned on this first nitrogen silicon compound layer the oxygen silicon compound layer and be positioned at one second nitrogen silicon compound layer on this oxygen silicon compound layer, and wherein the thickness of this first nitrogen silicon compound layer, this oxygen silicon compound layer and this second nitrogen silicon compound layer is between 0.2 micron to 1.2 microns.
15., it is characterized in that this protective layer comprises the nitrogen-oxygen-silicon compound layer of thickness between 0.05 micron to 0.15 micron according to circuit assembly structure as claimed in claim 11.
16. according to circuit assembly structure as claimed in claim 11; it is characterized in that this protective layer comprises a nitrogen-oxygen-silicon compound layer, be positioned at one first oxygen silicon compound layer on this nitrogen-oxygen-silicon compound layer, be positioned at the nitrogen silicon compound layer on this first oxygen silicon compound layer and one of be positioned on this nitrogen silicon compound layer the second oxygen silicon compound layer.
17. according to circuit assembly structure as claimed in claim 11; it is characterized in that; comprise that also one second bronze medal connection pad and contains second metal level of tantalum; this second metal level that contains tantalum coats the lower surface and the sidewall of this second bronze medal connection pad; be positioned at one of this protective layer second opening and expose this second bronze medal connection pad, wherein this metallic circuit connects this first bronze medal connection pad and this second bronze medal connection pad.
18., it is characterized in that this metallic circuit comprises that a coiled type partly according to circuit assembly structure as claimed in claim 11.
19., it is characterized in that according to circuit assembly structure as claimed in claim 11, also comprise a pair of outer connection pad, see through this metallic circuit and be connected to this first bronze medal connection pad, the position of this external connection pad is the position that is different from this first bronze medal connection pad.
20. according to circuit assembly structure as claimed in claim 11, it is characterized in that, this metallic circuit more comprise a titanium layer, titanium nitride layer, a titanium-tungsten layer, a chrome copper layer, a tantalum layer or tantalum nitride layer one of them, between this gold layer and this copper connection pad.
21. a circuitry component fabricating method is characterized in that, its step comprises:
Semiconductor substrate, at least one copper connection pad and a protective layer are provided, and wherein this protective layer and this copper connection pad were positioned on this semiconductor-based end, and at least one first opening that is positioned at this protective layer exposes this copper connection pad;
Form a metal level on this copper connection pad and this protective layer;
Form a patterning photoresist layer on this metal level, and at least one second opening that is positioned at this patterning photoresist layer exposes this metal level;
Form a gold medal layer on this metal level that this second opening is exposed;
Remove this patterning photoresist layer; And
Remove not this metal level under this gold layer.
22. according to circuitry component fabricating method as claimed in claim 21, it is characterized in that, comprise that also a metal level that contains tantalum coats the lower surface and the sidewall of this copper connection pad.
23. according to circuitry component fabricating method as claimed in claim 21; it is characterized in that this protective layer comprises one first nitrogen silicon compound layer, one of be positioned on this first nitrogen silicon compound layer the oxygen silicon compound layer and be positioned at one second nitrogen silicon compound layer on this oxygen silicon compound layer.
24., it is characterized in that this protective layer comprises the nitrogen silicon compound layer of thickness between 0.2 micron to 1.2 microns according to circuitry component fabricating method as claimed in claim 21.
25., it is characterized in that this protective layer comprises the oxygen silicon compound layer of thickness between 0.2 micron to 1.2 microns according to circuitry component fabricating method as claimed in claim 21.
26. according to circuitry component fabricating method as claimed in claim 21; it is characterized in that this protective layer comprises a nitrogen-oxygen-silicon compound layer, be positioned at one first oxygen silicon compound layer on this nitrogen-oxygen-silicon compound layer, be positioned at the nitrogen silicon compound layer on this first oxygen silicon compound layer and one of be positioned on this nitrogen silicon compound layer the second oxygen silicon compound layer.
27., it is characterized in that this step that forms this metal level comprises that a metal level of sputter titaniferous is on this copper connection pad and on this protective layer according to circuitry component fabricating method as claimed in claim 21.
28., it is characterized in that this step that forms this metal level comprises that sputter tantalum nitride layer is on this copper connection pad and on this protective layer according to circuitry component fabricating method as claimed in claim 21.
29., it is characterized in that also comprise and electroplate a nickel dam on this metal level that this second opening is exposed, wherein this gold layer of this formation is to be positioned on this nickel dam of this second opening according to circuitry component fabricating method as claimed in claim 21.
30., it is characterized in that this thickness that forms this gold layer is greater than 1.6 microns according to circuitry component fabricating method as claimed in claim 21.
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US9024431B2 (en) * 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US9607936B2 (en) * 2009-10-29 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Copper bump joint structures with improved crack resistance
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CN103839908B (en) * 2012-11-27 2017-07-14 中芯国际集成电路制造(上海)有限公司 Welding pad structure and preparation method thereof
US10283462B1 (en) 2017-11-13 2019-05-07 Micron Technology, Inc. Semiconductor devices with post-probe configurability
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US10867991B2 (en) 2018-12-27 2020-12-15 Micron Technology, Inc. Semiconductor devices with package-level configurability

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