CN1905178B - Circuit assembly structure and method for making the same - Google Patents

Circuit assembly structure and method for making the same Download PDF

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CN1905178B
CN1905178B CN 200610099176 CN200610099176A CN1905178B CN 1905178 B CN1905178 B CN 1905178B CN 200610099176 CN200610099176 CN 200610099176 CN 200610099176 A CN200610099176 A CN 200610099176A CN 1905178 B CN1905178 B CN 1905178B
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layer
copper
metal
metal layer
material
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CN 200610099176
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CN1905178A (en )
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周健康
周秋明
林茂雄
罗心荣
陈科宏
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米辑电子股份有限公司
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
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Abstract

The invention relates a circuitry component and a producing method thereof. At least a pad is over the top of the semiconductor substrate; A passivation layer is loaded on the top of the semiconductor substrate, and at least an opening in said passivation layer exposing the pad; and a metalic layer is stacked on the pad.

Description

线路组件结构及其制作方法 Line assembly structure and method of manufacturing

技术领域 FIELD

[0001] 本发明涉及一种半导体组件的制作及其结构,特别涉及一种在半导体基底上形成金属层的制作方法及其结构,其是更可与打线接合、贴带自动接合(TAB)、薄膜复晶接合(C0F)或玻璃复晶接合(COG)等制造方法相互匹配。 [0001] The present invention relates to a semiconductor structure fabrication and assembly, and more particularly to a method of forming on a semiconductor substrate manufacturing method and structure of the metal layer, which is further engageable with the wire, paste tape automated bonding (TAB) , bonded polycrystalline film (C0F) or polycrystalline bonded glass (COG) method and the like for producing matched to each other.

背景技术 Background technique

[0002] 在现今的半导体技术中,若欲降低半导体组件的尺寸,势必使得组件中单一集成电路芯片的封装密度呈现戏剧性地提高,然而,当半导体组件的尺寸缩小时,组件封装密度将提高,而集成电路芯片上用以提供电性连接的金属内连接层的层数亦必须增加,以有效地连接基底上相互分离的结构,举例而言,此领域中习知的单一集成电路芯片是具有二至六层的金属内连接层结构。 [0002] In today's semiconductor technology, reducing the size of the semiconductor Ruoyu assembly, such that the packing density of bound single integrated circuit chip assembly exhibits dramatically improved, however, when the size of the semiconductor components is reduced, to increase the packing density component, and the upper layers of the integrated circuit chip to provide a metal electrically connected to the connection layer also must be increased in order to connect the base structure effectively separated from each other, for example, in the conventional art in this single integrated circuit chip having metal connection layer structure of two to six.

[0003] 在成长完多层的金属内连接层结构后,金属接垫是形成于此金属内连接层结构的顶部,用以提供芯片或是晶粒做为对外的电性连接;接着,形成一保护层以避免芯片遭受到湿度与污染物的影响,而保护层的材料是可为氧化硅(Si02)、氮化硅(Si3N4)、氮氧化硅(silicon oxy-nitride)或是上述材料的组合;而在成长保护层之后,具有多个电路图案的晶粒则可连接至一封装基底上,且此封装基底是可具有多个封脚(Pin)以将其上的电路连接至外部的印刷电路板上。 [0003] After the growth of the metal connection layer is a multilayer structure, the metal pads are formed connected thereto a top layer metal structure, to provide a chip or die as the external electrical connection; Next, a protective layer to avoid chip contamination and subjected to the influence of humidity, the protective layer material is silicon oxide (Si02), silicon nitride (of Si3N4), silicon oxynitride (silicon oxy-nitride), or the above material combinations thereof; and after the growth of the protective layer, crystal grains having a plurality of circuit patterns on a package can be connected to the substrate and this substrate is the package may have a plurality of sealing pins (pin) to a circuit which is connected to the outside a printed circuit board.

[0004] 习知用以电性连接晶粒与封装基底的其中一种方法是利用打线技术,其中,一组相对应的接垫是位于封装基底上,一连接线(connection wire)是利用打线将每一个金属接垫连接至封装基底上相对应的接垫上,其中打线的方法是超音波打线的方式;接着,在完成打线后,封装结构是可进行封装(encapsulated)并密封。 [0004] One conventional method for electrically connecting the die to the package substrate using wire bonding technique, in which a set of corresponding pad is located on the package substrate, a connecting cable (connection wire) using each wire is connected to a metal contact pad on the package substrate corresponding to the pads, wherein the method is the manner in wire ultrasonic wire bonding; Next, after the completion of wire bonding, the package structure is encapsulated (encapsulated) and seal.

[0005] 实际上,打线接合制造方法的可靠度是为一关键的议题,因为打线接合制造方法是为整个生产流程的后段制造方法之一,所使用的晶粒是已封装且经过测试与筛选(sorted),因此,在打线接合制造方法中所产生的错误是直接损坏到良好的晶粒。 [0005] In fact, the reliability of wire bonding is a method of manufacturing a key issue, because a wire bonding method is provided for producing one-stage method for producing the entire production process, the grain is used after encapsulated and and screening test (the sorted), thus producing an error in a wire bonding process is generated directly to the fine grain damage. 而为了提升打线接合的可靠度,用在打线接合的金属接垫必须由可与接合制造方法相互匹配的金属所组成,而一般在打线接合制造方法中,较常用以做为金属接垫的金属是为铝与铝合金。 In order to improve the reliability of wire bonding, the metal wire bonding pads consisting of a metal can be matched to each other and joining the manufacturing method, the wire bonding and the general manufacturing method, more commonly used as a bonding metal to metal pad for aluminum and aluminum alloys.

[0006] 为了避免在打线接合制造方法中的注入塑料步骤或是延展接合金属线步骤发生位移的问题,接合的金属接垫必须先形成于芯片的周围,此外,用以连接组件与金属接垫之间的导电线路层(conductive trace)亦必须增加其长度。 [0006] In order to avoid the production method of injection of the plastic in the wire bonding step or the step of ductile metal wire joining problems of displacement, engage metal pads must be formed around the chip, in addition to the metal ground connector assembly wiring layer (conductive trace) between the pads must also increase its length. 且,随着芯片逐渐朝向具有更快速、更高兼容性的发展趋势,输入/输出连接(1/0 connetions)的数目便极速地增加,然而,金属接垫与接合金属线之间产生的电感将会阻碍芯片的高速操作。 And, as the chips progressively toward a more rapid and higher compatibility with the trend, the number of input / output connections (1/0 connetions) the speed will increase, however, the metal pad between the inductance and the wire bonding metal It will hinder high-speed operation of the chip.

[0007] 有鉴于此,本发明是针对上述的问题,提出一种在半导体基底上形成金属层的制作方法及其结构,以解决现有技术中所遭遇的困难。 [0007] Accordingly, the present invention is directed to the above-described problem, a production method and structure of forming a metal layer on the semiconductor substrate, in order to solve the difficulties encountered in the prior art.

发明内容 SUMMARY

[0008] 本发明的目的在于提供一种多层结构的金属层,其是直接与半导体基底上的接垫接合,且此金属层是适用于打线接合、贴带自动接合、薄膜复晶接合或玻璃复晶接合等制造方法中。 [0008] The object of the present invention is to provide a multi-layer structure of a metal layer, which is bonded directly to pads on the semiconductor substrate and the metal layer is applied to wire bonding, tape automated bonding paste, bonded polycrystalline thin film A method for producing a glass or the like bonded polycrystalline.

[0009] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;一铜层,位于该铜接垫上;以及一钯层,位于该铜层上。 [0009] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located exposing at least one opening in the copper pad; a copper layer located on the copper contact pad; and a palladium layer on the copper layer.

[0010] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;以及一钯层,位于该铜接垫上,且该钯层的厚度大于1.6微米。 [0010] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located at least one opening in the copper pad is exposed; and a palladium layer, the copper contact pads positioned, and the thickness of the palladium layer is greater than 1.6 microns.

[0011] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;一镍层,位于该铜接垫上,且该镍层的厚度是大于1.6微米;以及一钯层,位于该镍层上。 [0011] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located exposing at least one opening in the copper pad; a nickel layer located on the copper contact pad, and the thickness of the nickel layer is more than 1.6 m; and a palladium layer on the nickel layer.

[0012] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;一铜层,位于该铜接垫上;以及一钼层,位于该铜层上。 [0012] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located exposing at least one opening in the copper pad; a copper layer located on the copper contact pad; and a molybdenum layer on the copper layer.

[0013] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;以及一钼层,位于该铜接垫上,且该钼层的厚度大于1.6微米。 [0013] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located at least one opening in the copper pad is exposed; and a molybdenum layer, the pads located copper, molybdenum and the thickness of the layer is greater than 1.6 microns.

[0014] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;一镍层,位于该铜接垫上,且该镍层的厚度是大于1.6微米;以及一钼层,位于该镍层上。 [0014] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located exposing at least one opening in the copper pad; a nickel layer located on the copper contact pad, and the thickness of the nickel layer is more than 1.6 m; and a molybdenum layer on the nickel layer.

[0015] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一开口暴露出该铜接垫;以及一铑层,位于该开口所暴露出的该铜接垫上。 [0015] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located an opening of the copper pad is exposed; and a rhodium layer, the copper is located in the opening exposed by the pads.

[0016] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一开口暴露出该接垫;以及一钌层,位于该开口所暴露出的该接垫上。 [0016] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer an opening exposing the pad; and a layer of ruthenium, in the opening exposed by the contact pad.

[0017] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一开口暴露出该接垫;以及一铼层,位于该开口所暴露出的该接垫上。 [0017] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer an opening exposing the pad; and a rhenium layer in the opening exposed by the contact pad.

[0018] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫;一铜层,位于该开口所暴露出的该接垫上;一镍层,位于该铜层上;一钼层,位于该镍层上;以及一打线导线,位于该钼层上。 [0018] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer at least one opening exposing the pad; a copper layer, in the opening exposed by the contact pad; a nickel layer located on the copper layer; a molybdenum layer on the nickel layer; and a conductor wire , disposed on the molybdenum layer.

[0019] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫;一铜层,位于该开口所暴露出的该接垫上;一镍层,位于该铜层上;一钯层,位于该镍层上;以及一打线导线,位于该钯层上。 [0019] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer at least one opening exposing the pad; a copper layer, in the opening exposed by the contact pad; a nickel layer located on the copper layer; a palladium layer on the nickel layer; and a conductor wire , located on the palladium layer. [0020] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫;一铜层,位于该开口所暴露出的该接垫上;一镍层,位于该铜层上;一铑层,位于该镍层上;以及一打线导线,位于该铑层上。 [0020] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer at least one opening exposing the pad; a copper layer, in the opening exposed by the contact pad; a nickel layer located on the copper layer; a rhodium layer on the nickel layer; and a conductor wire , located on the rhodium layer.

[0021] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫;一铜层,位于该开口所暴露出的该接垫上;一镍层,位于该铜层上;一钌层,位于该镍层上;以及一打线导线,位于该钌层上。 [0021] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer at least one opening exposing the pad; a copper layer, in the opening exposed by the contact pad; a nickel layer located on the copper layer; a ruthenium layer on the nickel layer; and a conductor wire , located on the ruthenium layer.

[0022] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫;以及一金属线路,位于该保护层上,且该金属线路包括一铜层。 [0022] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective located a first opening exposing the first pad in the copper layer; and a metallic line disposed on the protective layer, and the metal line comprises a copper layer.

[0023] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫;以及一金属线路,位于该保护层上,且该金属线路包括一钯层。 [0023] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective located a first opening exposing the first pad in the copper layer; and a metallic line disposed on the protective layer, and the metal line comprises a palladium layer.

[0024] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫;以及一金属线路,位于该保护层上,且该金属线路包括一钼层。 [0024] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective located a first opening exposing the first pad in the copper layer; and a metallic line disposed on the protective layer, and the metal line comprises a molybdenum layer.

[0025] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫;以及一金属线路,位于该保护层上,且该金属线路包括一铑层。 [0025] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective located a first opening exposing the first pad in the copper layer; and a metallic line disposed on the protective layer, and the metal wiring layer comprises a rhodium.

[0026] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一接垫;以及一金属线路,位于该保护层上,该金属线路包括一钌层。 [0026] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located within a first opening exposing the first pad; and a metallic line disposed on the protective layer, the circuit comprising a layer of ruthenium metal.

[0027] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一接垫;以及一金属线路,位于该保护层上,且该金属线路包括一铼层。 [0027] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located within a first opening exposing the first pad; and a metallic line disposed on the protective layer, and the metal wiring layer comprises a rhenium.

[0028] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该保护层及该铜接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一金属层在该铜接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一钯层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该钯层下的该金属层。 [0028] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the protective layer and the copper pad located on the semiconductor substrate on and within the protective layer is at least a first opening to expose the copper pad; forming a metal layer on the protective pad and the copper layer; forming a patterned photoresist layer on the metal layer, and located within the patterned photoresist layer, at least a second opening exposing the metal layer; forming a palladium layer on the metal layer exposed by the second openings; removing the patterned photoresist layer; and removing is not the metal layer under the palladium layer.

[0029] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该保护层及该铜接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一金属层在该铜接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一钼层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该钼层下的该金属层。 [0029] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the protective layer and the copper pad located on the semiconductor substrate on and within the protective layer is at least a first opening to expose the copper pad; forming a metal layer on the protective pad and the copper layer; forming a patterned photoresist layer on the metal layer, and located within the patterned photoresist layer exposing at least one opening of the second metal layer; forming a molybdenum layer on the metal layer exposed by the second openings; removing the patterned photoresist layer; and removing is not the metal layer in the molybdenum layer.

[0030] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该保护层及该铜接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一金属层在该铜接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一铑层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该铑层下的该金属层。 [0030] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the protective layer and the copper pad located on the semiconductor substrate on and within the protective layer is at least a first opening to expose the copper pad; forming a metal layer on the protective pad and the copper layer; forming a patterned photoresist layer on the metal layer, and located within the patterned photoresist layer exposing at least one opening of the second metal layer; forming a layer of rhodium on the metal layer exposed by the second openings; removing the patterned photoresist layer; and removing is not the metal layer under the rhodium layer.

[0031] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一接垫及一保护层,其中该保护层及该接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该接垫;形成一金属层在该接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一钌层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该钌层下的该金属层。 [0031] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one pad and a protective layer, wherein the protective layer and the pad disposed on the semiconductor substrate, and within the protective layer is at least one opening exposing the first pad; forming a metal layer on the pad and on the protective layer; forming a patterned photoresist layer on the metal layer and the patterned located a second opening exposing the metal layer at least in the photoresist layer; forming a ruthenium layer on the metal layer exposed by the second openings; removing the patterned photoresist layer; and removing the layer of ruthenium is not in the metallic layer.

[0032] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一接垫及一保护层,其中该保护层及该接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该接垫;形成一金属层在该接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一铼层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该铼层下的该金属层。 [0032] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one pad and a protective layer, wherein the protective layer and the pad disposed on the semiconductor substrate, and within the protective layer is at least one opening exposing the first pad; forming a metal layer on the pad and on the protective layer; forming a patterned photoresist layer on the metal layer and the patterned located a second opening exposing the metal layer at least in the photoresist layer; forming in a Re layer on the metal layer exposed by the second openings; removing the patterned photoresist layer; and removing the layer of Re is not in the metallic layer.

[0033] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一接垫及一保护层,其中该保护层及该接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该接垫;形成一金属层在该接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一铜层在该第二开口所暴露出的该金属层上;形成一镍层在该铜层上;形成一钼层在该镍层上;去除该图案化光阻层;去除未在该钼层下的该金属层;切割该半导体基底形成多个半导体组件;以及利用一打线制造方法形成一打线导线在该半导体组件的该钼层上,并经由该打线导线电性连接至一外界电路。 [0033] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one pad and a protective layer, wherein the protective layer and the pad disposed on the semiconductor substrate, and within the protective layer is at least one opening exposing the first pad; forming a metal layer on the pad and on the protective layer; forming a patterned photoresist layer on the metal layer and the patterned located a second opening exposing the metal layer at least in the photoresist layer; forming a copper layer on the metal layer exposed by the second opening; forming a nickel layer on the copper layer; forming a molybdenum layer in the on the nickel layer; removing the patterned photoresist layer; removing the metal layer is not at the molybdenum layer; dicing the semiconductor substrate is formed a plurality of semiconductor elements; and using a wire bonding method for manufacturing a semiconductor device forming the bonding wires in on the molybdenum layer, and connected to an external circuit via the conductor electrically hit line.

[0034] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一接垫及一保护层,其中该保护层及该接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该接垫;形成一金属层在该接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的一第二开口暴露出该金属层;形成一铜层在该第二开口所暴露出的该金属层上;形成一镍层在该铜层上;形成一钯层在该镍层上;去除该图案化光阻层;去除未在该钯层下的该金属层;切割该半导体基底形成多个半导体组件;以及利用一打线制造方法形成一打线导线在该半导体组件的该钯层上,并经由该打线导线电性连接至一外界电路。 [0034] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one pad and a protective layer, wherein the protective layer and the pad disposed on the semiconductor substrate, and within the protective layer is at least one opening exposing the first pad; forming a metal layer on the pad and on the protective layer; forming a patterned photoresist layer on the metal layer and the patterned located a second opening in the photoresist layer to expose the metal layer; forming a metal layer on the copper layer exposed by the second opening; forming a nickel layer on the copper layer; a palladium layer is formed of the nickel layer; removing the patterned photoresist layer; removing the metal layer is not at the palladium layer; dicing the semiconductor substrate is formed a plurality of semiconductor elements; and using a forming method for producing a wire bonding wires in the semiconductor element the palladium layer, and connected to an external circuit via the conductor electrically hit line.

[0035] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一接垫及一保护层,其中该保护层及该接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该接垫;形成一金属层在该接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的一第二开口暴露出该金属层;形成一铜层在该第二开口所暴露出的该金属层上;形成一镍层在该铜层上;形成一铑层在该镍层上;去除该图案化光阻层;去除未在该铑层下的该金属层;切割该半导体基底形成多个半导体组件;以及利用一打线制造方法形成一打线导线在该半导体组件的该铑层上,并经由该打线导线电性连接至一外界电路。 [0035] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one pad and a protective layer, wherein the protective layer and the pad disposed on the semiconductor substrate, and within the protective layer is at least one opening exposing the first pad; forming a metal layer on the pad and on the protective layer; forming a patterned photoresist layer on the metal layer and the patterned located a second opening in the photoresist layer to expose the metal layer; forming a copper layer on the metal layer exposed by the second opening; forming a nickel layer on the copper layer; forming a layer of the nickel and rhodium layer; removing the patterned photoresist layer; removing the metal layer is not under the rhodium layer; dicing the semiconductor substrate is formed a plurality of semiconductor elements; and using a forming method for producing a wire bonding wires in the semiconductor element the rhodium layer, and connected to an external circuit via the conductor electrically hit line.

[0036] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一接垫及一保护层,其中该保护层及该接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该接垫;形成一金属层在该接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的一第二开口暴露出该金属层;形成一铜层在该第二开口所暴露出的该金属层上;形成一镍层在该铜层上;形成一钌层在该镍层上;去除该图案化光阻层;去除未在该钌层下的该金属层;切割该半导体基底形成多个半导体组件;以及利用一打线制造方法形成一打线导线在该半导体组件的该钌层上,并经由该打线导线电性连接至一外界电路。 [0036] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one pad and a protective layer, wherein the protective layer and the pad disposed on the semiconductor substrate, and within the protective layer is at least one opening exposing the first pad; forming a metal layer on the pad and on the protective layer; forming a patterned photoresist layer on the metal layer and the patterned located a second opening in the photoresist layer to expose the metal layer; forming a metal layer on the copper layer exposed by the second opening; forming a nickel layer on the copper layer; a ruthenium layer is formed of the nickel layer; removing the patterned photoresist layer; removing the metal layer is not at the ruthenium layer; dicing the semiconductor substrate is formed a plurality of semiconductor elements; and using a forming method for producing a wire bonding wires in the semiconductor element the ruthenium layer, and connected to an external circuit via the conductor electrically hit line.

[0037] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;至少一含钽的金属层,包覆该接垫的下表面及侧壁;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫;一含钛的金属层,位于该开口所暴露出的该接垫上;以及一金层,位于该含钛的金属层上。 [0037] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a metal layer containing at least tantalum, covering the lower surface of the pad and sidewalls; a protective layer on the semiconductor substrate and located at least one opening exposing the pad in the protective layer; a titanium-containing metal layer, in the opening exposed by the contact pads; and a gold layer on the metal layer containing titanium.

[0038] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫,其中该保护层包括一第一氮硅化合物层、位于该第一氮硅化合物层上之一第一氧硅化合物层及位于该第一氧硅化合物层上的一第二氮硅化合物层;一含钛的金属层,位于该开口所暴露出的该接垫上;以及一金层,位于该含钛的金属层上。 [0038] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer the at least one opening exposing the pad, wherein the protective layer comprises a first layer of silicon nitride compound, in one of the first nitrogen compound layer of the first silicon oxide layer and a silicon compound is located in the first oxide silicon compound layer a second compound of a silicon nitride layer; a titanium-containing metal layer, in the opening exposed by the contact pads; and a gold layer, located on the titanium-containing metallic layer.

[0039] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;介电常数值(k)介于1. 5至3的多个薄膜绝缘层,位于该半导体基底上;多个薄膜线路层,位于该半导体基底上,该些薄膜线路层之间存在该些薄膜绝缘层的至少其中之一,并透过位于该些薄膜绝缘层内的多个导通孔连通相邻两层的该些薄膜线路层;至少一接垫,位于该些薄膜绝缘层上;一保护层,位于该些薄膜绝缘层上及该些薄膜线路层上,且位于该保护层内的至少一开口暴露出该接垫;一含钛的金属层,位于该开口所暴露出的该接垫上;以及一金层,位于该含钛的金属层上。 [0039] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; dielectric constant (k) insulating film between the plurality of layers is from 1.5 to 3, disposed on the semiconductor substrate; a plurality of thin-film wiring layer on the semiconductor substrate, the plurality of thin-film insulation layer is present between the plurality of thin film wiring layers wherein at least one of, adjacent to and communicating through a plurality of vias in the plurality of thin-film insulating layer these two layers of the film wire; at least one pad, the plurality of thin film located on the insulating layer; a protective layer on the insulating layer and the plurality of thin film on the plurality of wiring layers, and within at least one of the protective layer opening exposing the pad; a titanium-containing metal layer, in the opening exposed by the contact pads; and a gold layer on the metal layer containing titanium.

[0040] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一含钽的第一金属层,包覆该第一铜接垫的下表面及侧壁; 一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫;一金属线路,位于该保护层上,且该金属线路包括一金层。 [0040] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a first metal layer comprising tantalum, covering the first copper pad surface and a lower side wall; a protective layer on the semiconductor substrate and located in a first opening exposing the first pad in the copper protective layer; a metal line on the protective layer, and the metal wiring comprises a gold layer.

[0041] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫,其中该保护层包括一第一氮硅化合物层、位于该第一氮硅化合物层上的一氧硅化合物层及位于该氧硅化合物层上之一第二氮硅化合物层;一金属线路,位于该保护层上,且该金属线路包括一金层。 [0041] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective located a first opening exposing the first pad in the copper layer, wherein the protective layer comprises a first layer of silicon nitride compound, an oxide silicon compound layer positioned on the first compound layer, and a silicon nitride oxide silicon compound is located a second nitrogen compound layer is one of a silicon layer; a metal line on the protective layer, and the metal line comprises a gold layer. [0042] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;介电常数值(k)介于1. 5至3的多个薄膜绝缘层,位于该半导体基底上;多个薄膜线路层,位于该半导体基底上,并透过位于该些薄膜绝缘层内的多个导通孔连通相邻两层的该些薄膜线路层;一第一铜接垫,位于该些薄膜绝缘层上;一保护层,位于该些薄膜绝缘层上及该些薄膜线路层上,且位于该保护层内的一第一开口暴露出该第一铜接垫;以及一金属线路,位于该保护层上,且该金属线路包括一金层。 [0042] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; dielectric constant (k) insulating film between the plurality of layers is from 1.5 to 3, disposed on the semiconductor substrate; the plurality of thin film circuit layer plurality of wiring layers disposed on the semiconductor substrate, and a plurality of vias through the insulating film of the plurality of communication layers of the two adjacent layers; a first copper contact pad on the plurality insulating layer on the thin film; a protective layer on the insulating layer and the plurality of thin film on the plurality of wiring layers, and a first opening positioned within the protective layer to expose the first copper contact pads; and a metal line located on the protective layer, and the metal line comprises a gold layer.

[0043] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;一铜层,位于该铜接垫上;以及一银层,位于该铜层上。 [0043] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located exposing at least one opening in the copper pad; a copper layer located on the copper contact pad; and a silver layer on the copper layer.

[0044] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;以及一银层,位于该铜接垫上,且该银层的厚度大于1.6微米。 [0044] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located at least one opening in the copper pad is exposed; and a silver layer disposed on the pads of the copper, and the thickness of the silver layer is greater than 1.6 microns.

[0045] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该铜接垫;一镍层,位于该铜接垫上,且该镍层的厚度是大于1.6微米;以及一银层,位于该镍层上。 [0045] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least a copper pad located on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located exposing at least one opening in the copper pad; a nickel layer located on the copper contact pad, and the thickness of the nickel layer is more than 1.6 m; and a silver layer on the nickel layer.

[0046] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;至少一含钽的金属层,包覆该接垫的下表面及侧壁;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫;以及一锡银合金层,位于该开口所暴露出的该接垫上。 [0046] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a metal layer containing at least tantalum, covering the lower surface of the pad and sidewalls; a protective layer on the semiconductor substrate, and at least one opening is located in the protective layer to expose the pad; and a tin-silver alloy layer in the opening exposed by the contact pad.

[0047] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;至少一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的至少一开口暴露出该接垫,其中该保护层包括一第一氮硅化合物层、位于该第一氮硅化合物层上之一氧硅化合物层及位于该氧硅化合物层上之一第二氮硅化合物层;以及一锡银合金层, 位于该开口所暴露出的该接垫上。 [0047] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; at least one pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and located within the protective layer at least one opening exposing the pad, wherein the protective layer comprises a first layer of silicon nitride compound, in the second, and located on the oxygen-oxygen-silicon compound layer one one silicon compound layer on the first silicon nitride layer compound a silicon nitride compound layer; and a tin-silver alloy layer in the opening exposed by the contact pad.

[0048] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;介电常数值(k)介于1. 5至3的多个薄膜绝缘层,位于该半导体基底上;多个薄膜线路层,位于该半导体基底上,并透过位于该些薄膜绝缘层内的多个导通孔连通相邻两层的该些薄膜线路层;至少一接垫,位于该些薄膜绝缘层上;一保护层,位于该些薄膜绝缘层上及该些薄膜线路层上,且位于该保护层内的至少一开口暴露出该接垫;以及一锡银合金层,位于该开口所暴露出的该接垫上。 [0048] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; dielectric constant (k) insulating film between the plurality of layers is from 1.5 to 3, disposed on the semiconductor substrate; the plurality of thin film circuit layer plurality of wiring layers disposed on the semiconductor substrate, and a plurality of vias through the insulating layer of the plurality of thin film layers of adjacent communication; at least one contact pad on the plurality of insulating films layer; a protective layer on the insulating layer and the plurality of thin film on the plurality of wiring layers, and at least one opening is located in the pad is exposed in the protective layer; and a tin-silver alloy layer, is exposed in the opening out of the ground pad.

[0049] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一铜接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一铜接垫;以及一金属线路,位于该保护层上,且该金属线路包括一银层。 [0049] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first copper contact pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective located a first opening exposing the first pad in the copper layer; and a metallic line disposed on the protective layer, and the metal line comprises a silver layer.

[0050] 为了实现本发明的上述目的,提出一种线路组件结构,包括一半导体基底;一第一接垫,位于该半导体基底上;一保护层,位于该半导体基底上,且位于该保护层内的一第一开口暴露出该第一接垫;以及一金属线路,位于该保护层上,且该金属线路包括一锡银合金层。 [0050] To achieve the above object of the present invention to provide a circuit assembly structure comprising a semiconductor substrate; a first pad disposed on the semiconductor substrate; a protective layer on the semiconductor substrate, and the protective layer is located within a first opening exposing the first pad; and a metallic line disposed on the protective layer, and the metal line comprises a tin-silver alloy layer. [0051] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫、至少一含钽的金属层及一保护层,其中该保护层及该铜接垫位于该半导体基底上,该含钽的金属层包覆该铜接垫的下表面及侧壁,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一含钛的金属层在该第一开口所暴露的该铜接垫上及该保护层上;形成一图案化光阻层在该含钛的金属层上,且至少一第二开口位于该图案化光阻层内;形成一金层在该第二开口内;去除该图案化光阻层;以及去除未在该金层下的该含钛的金属层。 [0051] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least a copper pad, containing at least a metal layer and a tantalum protective layer, wherein the protective layer and the copper pad located on the semiconductor substrate, the tantalum-containing metal layer coated surface and a lower side wall of the copper pads, and is located a first opening to expose the copper pad at least in the protective layer; forming a the titanium-containing copper metal layer in the first opening and the exposed contact pads on the protective layer; forming a patterned photoresist layer on the titanium-containing metal layer, and a second opening is located at least the patterned light the barrier layer; forming a gold layer in the second opening; removing the patterned photoresist layer; and removing the titanium-containing metal layer is not under the gold layer. [0052] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该铜接垫位于该半导体基底上,该保护层包括一第一氮硅化合物层、位于该第一氮硅化合物层上之一氧硅化合物层及位于该氧硅化合物层上的一第二氮硅化合物层,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一含钛的金属层在该第一开口所暴露的该铜接垫上及该保护层上;形成一图案化光阻层在该含钛的金属层上,且至少一第二开口位于该图案化光阻层内;形成一金层在该第二开口内; 去除该图案化光阻层;以及去除未在该金层下的该含钛的金属层。 [0052] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the copper pads disposed on the semiconductor substrate, the protective a first layer comprising a silicon nitride compound layer, and positioned within at least one of the protective oxide layer on the first silicon compound layer is a silicon nitride compound layer is disposed a second nitrogen compound layer formed on the silicon oxide layer, a silicon compound, and is located a first opening exposing the copper pad; a titanium-containing metal layer is formed on the first opening of the copper exposed by the pads and the protective layer; forming a patterned photoresist layer a metal layer in the titanium-containing upper, and at least a second opening is located within the patterned photoresist layer; forming a gold layer in the second opening; removing the patterned photoresist layer; and removing the titanium-containing metal is not in the gold layer Floor.

[0053] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该半导体基底包括多个介电常数值(k)介于1.5 至3的薄膜绝缘层及多个薄膜线路层,该些薄膜线路层位于该些薄膜绝缘层之间,并透过位于该些薄膜绝缘层内的多个导通孔连通相邻两层的该些薄膜线路层,该保护层位于该些薄膜绝缘层上及该些薄膜线路层上,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一含钛的金属层在该第一开口所暴露出的该铜接垫上及该保护层上;形成一图案化光阻层在该含钛的金属层上,且至少一第二开口位于该图案化光阻层内;形成一金层在该第二开口内;去除该图案化光阻层;以及去除未在该金层下的该含钛的金属层。 [0053] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the semiconductor substrate comprises a plurality of dielectric constant (k ) interposed between the insulating film layer is 1.5 to 3 and a plurality of thin film wiring layers, the plurality of thin-film wiring layer is disposed between the plurality of thin-film insulating layer, adjacent to and communicating through a plurality of vias in the plurality of thin-film insulating layer the plurality of layers of thin film wiring layer, the protective layer on the insulating layer, and these thin film on the plurality of thin film wiring layers, and at least a first opening positioned within the protective layer to expose the copper pad; forming a titanium-containing a metal layer on the first opening of the copper exposed by the protective layer and contact pads; forming a patterned photoresist layer on the titanium-containing metal layer, and a second opening is located at least the patterned photoresist the inner layer; forming a gold layer in the second opening; removing the patterned photoresist layer; and removing the titanium-containing metal layer is not under the gold layer.

[0054] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、位于该半导体基底上的至少一铜接垫及位于该半导体基底上之一保护层,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一图案化光阻层在该保护层上,且至少一第二开口位于该图案化光阻层内;无电电镀一第一金属层在该第二开口内;以及去除该图案化光阻层。 [0054] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, a copper pad located on at least one protective layer and is located on the semiconductor substrate on the semiconductor substrate, and located in the protective layer is at least a first opening to expose the copper pad; forming a patterned photoresist layer on the protection layer, and at least a second opening is located within the patterned photoresist layer; an electroless plating a first metal layer in the second opening; and removing the patterned photoresist layer.

[0055] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底;形成一第一金属层在该半导体基底上;形成一图案化光阻层在该第一金属层上,且位于该图案化光阻层内的至少一开口暴露出该第一金属层;电镀一第二金属层在该开口所暴露出的该第一金属层上;无电电镀一第三金属层在该第二金属层上;去除该图案化光阻层;以及去除未在该第三金属层下的该第一金属层。 [0055] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate; forming a first metal layer on the semiconductor substrate; forming a patterned photoresist layer on the first on the metal layer, and within the patterned photoresist layer, at least one opening exposing the first metal layer; a second metal layer plated on the first metal layer exposed by the opening; a first electroless plating three metal layer on the second metal layer; removing the patterned photoresist layer; and removing the first metal layer not under said third metal layer.

[0056] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底;形成一第一金属层在该半导体基底上;形成一图案化光阻层在该第一金属层上,且位于该图案化光阻层内的至少一开口暴露出该第一金属层;无电电镀一第二金属层在该开口所暴露出的该第一金属层上;电镀一第三金属层在该第二金属层上;去除该图案化光阻层;以及去除未在该第三金属层下的该第一金属层。 [0056] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate; forming a first metal layer on the semiconductor substrate; forming a patterned photoresist layer on the first on the metal layer, and within the patterned photoresist layer, at least one opening exposing the first metal layer; electroless plating a second metal layer on the first metal layer exposed by the opening; a first plating three metal layer on the second metal layer; removing the patterned photoresist layer; and removing the first metal layer not under said third metal layer.

[0057] 为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该保护层及该铜接垫位于该半导体基底上,且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一金属层在该铜接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一银层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该银层下的该金属层。 [0057] To achieve the above object of the present invention, a method for manufacturing an assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the protective layer and the copper pad located on the semiconductor substrate on and within the protective layer is at least a first opening to expose the copper pad; forming a metal layer on the protective pad and the copper layer; forming a patterned photoresist layer on the metal layer, and located within the patterned photoresist layer exposing at least one opening of the second metal layer; forming a layer of silver on the metal layer exposed by the second openings; removing the patterned photoresist layer; and removing is not the metal layer under the silver layer. [0058] 实现为了实现本发明的上述目的,提出一种线路组件制作方法,其步骤包括提供一半导体基底、至少一铜接垫及一保护层,其中该保护层及该铜接垫位于该半导体基底上, 且位于该保护层内的至少一第一开口暴露出该铜接垫;形成一金属层在该铜接垫及该保护层上;形成一图案化光阻层在该金属层上,且位于该图案化光阻层内的至少一第二开口暴露出该金属层;形成一锡银合金层在该第二开口所暴露出的该金属层上;去除该图案化光阻层;以及去除未在该锡银合金层下的该金属层。 [0058] In order to achieve the object of the present invention to achieve the above, to provide a method for manufacturing assembly line, comprising the steps of providing a semiconductor substrate, at least one of copper and a pad protection layer, wherein the protective layer and the copper pad located on the semiconductor on the substrate, and the protective layer is positioned within at least a first opening to expose the copper pad; forming a metal layer on the protective pad and the copper layer; forming a patterned photoresist layer on the metal layer, and within the patterned photoresist layer exposing at least one opening of the second metal layer; forming a tin-silver alloy layer on the metal layer exposed by the second openings; removing the patterned photoresist layer; removing the metal layer in the tin-silver alloy layer is not.

[0059] 以下结合具体实施例、结合附图详加说明,当更容易了解本发明的目的、技术内容、特点及其所达成的功效。 [0059] The following embodiments in conjunction with specific embodiments, described in detail in conjunction with the accompanying drawings, when the object of the present invention more readily understood, the technical contents, features, and effects achieved.

附图说明 BRIEF DESCRIPTION

[0060] 图Ia至图Ie为本发明半导体基底、细联机结构及保护层的制造方法剖面示意图; [0060] FIGS Ia to Ie of the present invention, a semiconductor substrate, structure and manufacturing method of the fine-line cross-sectional view of the protective layer;

[0061] 图2a至图2k为本发明第一实施例的制造方法剖面示意图; The method of manufacturing a schematic sectional view of a first embodiment of the embodiment [0061] Figures 2a-2k of the present invention;

[0062] 图3a至图3g为本发明第二实施例的制造方法剖面示意图; [0062] The manufacturing method according to a second embodiment of a schematic cross-sectional Figures 3a-3g of the present invention;

[0063] 图4a至图4h为本发明第三实施例的制造方法剖面示意图; [0063] Figures 4a-4h cross-sectional schematic view of a third embodiment of the manufacturing method according to the present invention;

[0064] 图5a至图5i为本发明第四实施例的制造方法剖面示意图; The method of manufacturing a cross-sectional schematic view of a fourth embodiment [0064] Figures 5a to 5i of the present invention;

[0065] 图6a至图6k为本发明第五实施例的制造方法剖面示意图; A method for producing a cross-sectional schematic view of a fifth embodiment of the [0065] Figures 6a to 6k of the present invention;

[0066] 图7a至图7d为本发明第六实施例的制造方法剖面示意图; [0066] Figures 7a to 7d method of manufacturing a cross-sectional schematic view of a sixth embodiment of the present invention;

[0067] 图8a至图8k为本发明第七实施例的制造方法剖面示意图; [0067] Figures 8a to 8k is a sectional schematic view of a seventh embodiment of the manufacturing method according to the invention;

[0068] 图9a至图9j为本发明第八实施例的制造方法剖面示意图; The method of manufacturing a cross-sectional schematic view of an eighth embodiment [0068] Figures 9a-9j of the present invention;

[0069] 图IOa至图IOj为本发明第九实施例的制造方法剖面示意图; [0069] The method for producing a cross-sectional schematic view of a ninth embodiment of FIGS IOa IOj to the present invention;

[0070] 图Ila至图Ilf为本发明第十实施例的制造方法剖面示意图; [0070] The method for producing a cross-sectional schematic view of a tenth embodiment of FIGS Ilf Ila to the present invention;

[0071] 图12a至图12i为本发明第十一实施例的制造方法剖面示意图。 The method of manufacturing a cross-sectional schematic view of an eleventh embodiment [0071] Figures 12a to 12i of the present invention.

[0072] 附图标记说明:10半导体基底;12电子组件;14细联机结构;16薄膜绝缘层;18 薄膜线路层;20无机保护层;22沟渠;24导通孔;26阻障层;28种子层;30铜金属;32铜接垫;34保护层;36开口;38第一金属层;40种子层;42光阻层;44开口;46第二金属层; 48聚合物层;50开口;52半导体组件;54打线导线;56软性基板;58聚合物;60异方性导电胶;62玻璃基板;64软性基板;66第二金属层;68第三金属层;70第二金属层;72第三金属层;74第四金属层;76第二金属层;78第三金属层;80第四金属层;82第五金属层;84 第一金属层;86第二金属层;88光阻层;90第三金属层;92种子层;94光阻层;96开口;98 第四金属层;100间隙;102第四金属层;104第五金属层;106第六金属层;108聚合物层; 110第一开口;112第二开口;114第一金属层;116种子层;118光阻层;120开口;122第 [0072] REFERENCE NUMERALS: a semiconductor substrate 10; 12 electronic component; fine line structure 14; 16 thin insulating layer; a thin film circuit layer 18; 20 of the inorganic protective layer; trench 22; 24 via hole; barrier layer 26; 28 The seed layer; 30 copper; copper pad 32; 34 protective layer; opening 36; 38 of the first metal layer; seed layer 40; photoresist layer 42; the opening 44; 46 of the second metal layer; a polymer layer 48; openings 50 ; 52 semiconductor components; bonding wires 54; 56 of the flexible substrate; polymer 58; 60 anisotropic conductive adhesive; glass substrates 62; 64 flexible substrate; a second metal layer 66; a third metal layer 68; 70 of the second the metal layer; a third metal layer 72; the fourth metal layer 74; a second metal layer 76; 78 of the third metal layer; a fourth metal layer 80; the fifth metal layer 82; 84 of the first metal layer; a second metal layer 86 ; photoresist layer 88; a third metal layer 90; 92 of the seed layer; photoresist layer 94; the opening 96; the fourth metal layer 98; gap 100; 102 fourth metal layer; a fifth metal layer 104; 106 sixth metal layer ; polymer layer 108; a first opening 110; 112 a second opening; a first metal layer 114; 116 seed layer; photoresist layer 118; an opening 120; 122 of 金属;124金属线路;126聚合物层;128开口;130打线导线;132聚合物层;134第一金属层;136种子层;138光阻层;140开口;142第二金属层;144金属线路;146聚合物层;148 开口;150打线导线;152聚合物层;154开口;156第一金属层;158种子层;160光阻层;162开口;164第二金属层;166金属线路;168聚合物层;170开口;172打线导线;174第一金属层;176种子层;178光阻层;180开口;182金属凸块;184含锡凸块;186第一金属层;188 种子层;190图案化光阻层;192a开口; 192b开口; 192c开口; 194a第二金属层;194b第二金属层;194c第二金属层;196a第三金属层;196b第三金属层;196c第三金属层;198图案化光阻层;200a开口;200b开口;202a第四金属层;202b第四金属层;204a第五金属层; 204b第五金属层;206光阻层;208开口;210金属凸块;320第一铜接垫;322第二铜接垫; 324铜接垫 Metal; metal lines 124; polymer layer 126; an opening 128; 130 bonding wires; polymer layer 132; a first metal layer 134; 136 seed layer; photoresist layer 138; an opening 140; 142 a second metal layer; metal 144 line; polymer layer 146; an opening 148; 150 bonding wires; polymer layer 152; an opening 154; a first metal layer 156; 158 seed layer; photoresist layer 160; an opening 162; 164 a second metal layer; metal lines 166 ; polymer layer 168; an opening 170; 172 bonding wires; a first metal layer 174; 176 seed layer; photoresist layer 178; an opening 180; 182 metal bump; 184 tin bumps; a first metal layer 186; 188 The seed layer; patterned photoresist layer 190; an opening 192a; 192b opening; opening 192c; a second metal layer 194a; 194b a second metal layer; a second metal layer 194c; third metal layer 196a; a third metal layer 196b; 196c The third metal layer; patterned photoresist layer 198; an opening 200a; 200b opening; fourth metal layer 202a; 202b fourth metal layer; a fifth metal layer 204a; 204b fifth metal layer; photoresist layer 206; an opening 208; metal bump 210; 320 a first copper contact pad; second copper contact pad 322; 324 copper contact pad 326铜接垫;328铜接垫;340开口;342开口;344开口。 Copper contact pad 326; copper pad 328; 340 opening; opening 342; 344 opening. 具体实施方式 detailed description

[0073] 本发明是关于一种利用电镀制造方法或无电电镀制造方法以形成一多层结构的金属层的结构及制作方法,其是与半导体基底上的铜接垫或铝接垫接合,且此金属层是适用于打线接合、贴带自动接合、薄膜复晶接合或玻璃复晶接合等制造方法中。 [0073] The present invention relates to a method for manufacturing a plating or electroless plating method to form the structure manufactured using the metal layer and the method for manufacturing a multilayer structure, which is a semiconductor substrate with copper on an aluminum pad or pads engage, and the metal layer is applied to wire bonding, tape automated bonding paste, bonded polycrystalline thin film polycrystalline or glass bonding or the like producing process. 另外,在本发明所揭露的每一种结构及方法皆是建构在一半导体基底上,且在此半导体基底上更设有一细联机结构及一保护层,因此首先将解说有关半导体基底、细联机结构以及保护层的结构及形成方法,接着再进行本发明各种实施例的说明。 Further, in each of the structures and methods disclosed construction of the present invention are all on a semiconductor substrate, and on this semiconductor substrate is provided with a more fine-line structure and a protective layer, and thus the explanation about the first semiconductor substrate, the fine-line structure and the structure and formation method of the protective layer, and then further embodiment of the present invention, the various embodiments described.

[0074] 首先,请参阅图Ia所示,半导体基底10的形式比如是硅基底、砷化镓基底(GaAs)、 硅化锗基底、具有磊晶硅在绝缘层上(silicon-on-insulator,SOI)的基底,而在此实施例中半导体基底10是为圆形的一半导体晶圆,且此半导体基底10具有一主动表面,并透过掺杂五价或三价的离子(例如硼离子或磷离子等)在半导体基底10的主动表面形成多个电子组件12,而此电子组件12例如是金氧半导体组件(MOSdevices),ρ信道金氧半导体组件(p-channel MOS devices), η 信道金氧半导体组件(n-channel MOS devices),双载子互补式金氧半导体组件(BiCMOS devices),双载子连接晶体管(Bipolar Junction Transistor, BJT),互补金属氧化半导体(CMOS),扩散区(Diffusion area),电阻组件(resistor) Ά^^Ά^ (capacitor)等。 [0074] First, see FIG. Ia, the form of the semiconductor substrate 10 such as a silicon substrate, gallium arsenide substrate (GaAs), silicon germanium substrate having an epitaxial silicon on the insulating layer (silicon-on-insulator, SOI ) substrate, and a semiconductor substrate in example 10 in this embodiment is a circular semiconductor wafer, and the semiconductor substrate 10 having an active surface, and through doping trivalent or pentavalent ions (e.g., boron ions or phosphorus ions, etc.) a plurality of electronic components 12 on the active surface of the semiconductor substrate 10, and this electronic component 12, for example, metal-oxide-semiconductor element (MOSdevices), ρ channel metal-oxide-semiconductor element (p-channel MOS devices), η channel gold oxygen semiconductor element (n-channel MOS devices), bipolar complementary metal oxide semiconductor device (BiCMOS devices), bipolar-connected transistor (Bipolar Junction transistor, BJT), a complementary metal oxide semiconductor (CMOS), a diffusion region (diffusion area), the resistive component (resistor) Ά ^^ Ά ^ (capacitor) and the like.

[0075] 继续请参阅图Ib所示,在半导体基底10的主动表面上形成一细联机结构14,此细联机结构14是由多个厚度小于3微米(μπι)的薄膜绝缘层16及厚度小于3微米的薄膜线路层18所构成,其中薄膜线路层18是选自铜金属材质或铝金属材质,而薄膜绝缘层16 又称为介电层,一般是利用化学气相沉积的方式所形成。 [0075] Referring to FIG. Ib continued, the structure 14 is formed in a thin line on the active surface of the semiconductor substrate 10, the fine line structure 14 by a plurality of thickness less than 3 microns (μπι) thin film 16 and the insulating layer thickness of less than 3 micron film circuit layer 18 formed, wherein the thin film circuit layer 18 is a metal material selected from copper or aluminum material, the insulating layer 16 and the thin-film dielectric is also known, is typically formed by chemical vapor deposition method. 此薄膜绝缘层16比如为氧化硅、 化学气相沉积的四乙氧基硅烷(TEOS)氧化物、含硅、碳、氧与氢的化合物(例如SiwCxOyHz)、 氮硅化合物、氟化玻璃(FSG)、黑钻石薄膜(BlackDiamond)、丝印层(SiLK)、多孔性氧化硅(porous silicon oxide)或氮氧硅化合物,或是以旋涂方式形成的玻璃(SOG)、聚芳基酯(polyarylene ether)、聚苯恶唑(polybenzoxazole,ΡΒ0),或者是其它介电常数值(k)介于1.5至3的材质。 This thin insulating layer 16 such as silicon oxide, a chemical vapor deposited tetraethoxysilane (TEOS) oxide, silicon, carbon, oxygen and hydrogen compounds (e.g. SiwCxOyHz), silicon nitride compound, fluoride glass (FSG) , black diamond film (the BlackDiamond), silkscreen (siLK), porous silica (porous silicon oxide) or silicon oxynitride compound, or glass (SOG) spin coating formed of polyarylate (polyarylene ether) , polybenzoxazole (polybenzoxazole, ΡΒ0), or other dielectric constant (k) material is between 1.5 to 3 in.

[0076] 请参阅图Ic所示,就金属镶嵌制造方法而言,形成多个薄膜线路层18在半导体基底10上的方式是先利用化学气相沉积(chemical vapor deposition, CVD)沉积一无机保护层20在薄膜绝缘层16的上表面上,此无机保护层20的材质是选自氮硅化合物、氮氧硅化合物或碳硅化合物,接着形成一图案化光阻层在无机保护层20上,并利用位于图案化光阻层内的图案化开口蚀刻无机保护层20与薄膜绝缘层16而形成由沟渠22与导通孔24所组成的开口,接着利用溅镀或化学气相沉积的方式沉积一阻障层26在此开口内的下表面与侧壁上以及无机保护层20的上表面上,其中此阻障层26的材质是选自钽(Ta)、氮化钽(TaN)Ji (Co)、镍(Ni)、钨(W)、氮化钨(WN)Jjg (Nb)、硅酸铝(aluminum silicate)、氮化钛(TiN)及氮化硅钛(TiSiN)其中之一,或者是上述材料所形成的合金;再来同样利用溅镀或化学气 [0076] Referring to FIG. Ic, in terms of a damascene manufacturing method embodiment is formed on the semiconductor substrate 10, a plurality of first thin-film wiring layer 18 using a chemical vapor deposition (chemical vapor deposition, CVD) depositing an inorganic protective layer 20 on the upper surface of the insulating film layer 16, the inorganic material of this protective layer 20 is a compound selected from silicon nitride, silicon oxynitride or a carbon compound a silicon compound, followed by forming a patterned photoresist layer on the inorganic protective layer 20, and using the patterned photoresist layer in the patterned etching of the inorganic protective layer and the thin insulating layer 20 an opening 16 is formed an opening of trench 22 and via hole 24 composed, followed by sputtering or chemical vapor deposition of depositing a barrier barrier layer 26 and the sidewall of the lower surface of this opening and the upper surface 20 of the inorganic protective layer, wherein this barrier layer 26 is a material selected from tantalum (Ta), tantalum nitride (TaN) Ji (Co) , nickel (Ni), tungsten (W), tungsten nitride (WN) Jjg (Nb), aluminum (aluminum silicate), titanium nitride (TiN) and titanium silicon nitride (TiSiN) wherein one or the above-mentioned alloy material is formed; the same again by sputtering or chemical gas 沉积的方式沉积一层例如是铜材质的种子层28在阻障层26上,接着电镀一铜金属30在此种子层28上,最后利用化学机械研磨(chemical mechanical polish, CMP)的方式去除位于此开口外的铜金属30、种子层28及阻障层26,直到曝露出无机保护层20的上表面为止,为使结构简而易懂,仅绘示出细联机结构14其中一层的详细结构于图中。 Depositing a layer of deposited material, for example, a copper seed layer 28 on the barrier layer 26, and then a copper plating 30 on this seed layer 28, the final chemical mechanical polishing (chemical mechanical polish, CMP) is located in a manner removed copper outside this opening 30, the seed layer 28 and the barrier layer 26 until exposing the surface of the inorganic protective layer 20, so that the structure is simple and easy to understand, only the thin line shows the detailed structure of one of the layers 14 configuration in FIG.

[0077] 如图Ic所示,以此种方式在沟渠22内所形成的阻障层26、种子层28及铜金属30 是为薄膜线路层18,且薄膜线路层18的厚度是介于0. 1微米到2微米之间,而此些薄膜线路层18可以透过薄膜绝缘层16内的多个导通孔24连通相邻两层之间的薄膜线路层18或者是连接至电子组件12上。 [0077] As shown in FIG Ic, the barrier layer in such a manner into a channel 22 formed by 26, 28 and copper seed layer 30 is a thin film circuit layer 18, and the thickness of the thin film circuit layer 18 is between 0 . between 1 micron and 2 microns, and of such a thin film circuit layer 18 may be adjacent to the thin film circuit layer between the two layers 18 or 12 is connected to the electronic assembly communicates through a plurality of vias in the thin-film insulating layer 1624 on. 另外,请参阅图Id所示,以图Ic所述的方式在细联机结构14 最顶部所形成的薄膜线路层18是称为铜接垫32,其用以作为电子组件12对外电性连接的使用,且同样地此铜接垫32的下表面及侧壁包覆有阻障层26及种子层28。 Also, see FIG. Id illustrated in FIG. Ic thin film circuit layer at the very top in the manner of fine-line structures 14 formed of copper pad 18 is referred to as 32, which is used as an electronic component 12 is electrically connected to the external use, in the same manner and this copper pad surface and a lower side wall 32 is covered with the barrier layer 26 and the seed layer 28.

[0078] 继续请参阅图Ie所示,在曝露出细联机结构14最顶部的无机保护层20的上表面后,接着利用化学气相沉积的方式设置一保护层34在曝露出的无机保护层20的上表面以及铜接垫32上,且此保护层34开设有多个开口36曝露出多数铜接垫32,其中此些开口36 的最大横向尺寸是介于0. 5微米至15微米之间,或者是介于15微米至300微米之间。 [0078] Please continue to refer to FIG. Ie is, after the inorganic protective layer 14 on the surface of the topmost expose the fine line structure 20, followed by chemical vapor deposition of a protective layer 34 provided on the inorganic protective layer 20 expose and between the copper pad 32, and this protective layer 34 defines a plurality of openings 36 exposing the majority of the copper pad 32, wherein the opening of such maximum transverse dimension 36 is between 0.5 to 15 microns on the surface , or between 15 microns to 300 microns.

[0079] 保护层34可以保护半导体基底10内的电子组件12免于湿气与外来离子污染物(foreign ion contamination)的破坏,也就是说保护层34可以防止移动离子(mobileions)(比如是钠离子)、水气(moisture)、过渡金属(transition metal)(比如是金、银、铜)及其它杂质(impurity)穿透,而损坏保护层34下方的晶体管、多晶硅电阻组件或多晶硅_多晶硅电容组件的电子组件12或薄膜线路。 [0079] The protective layer 34 can protect the electronic components 10 within the semiconductor substrate 12 from moisture and foreign destruction of ionic contaminants (foreign ion contamination), that the protective layer 34 may prevent mobile ions (mobileions) (such as sodium ions), moisture (moisture), the transition metal (transition metal) (such as gold, silver, copper) and other impurities (impurity) penetration, damage the transistor 34 below the protective layer, a polysilicon resistor or a polysilicon _-poly capacitor assembly the electronic component assembly 12 or the film wire. 为了达到保护的目的,保护层34 通常是由氧硅化合物、磷硅玻璃、氮硅化合物以及氮氧硅化合物等所组成,且其中上述的氧硅化合物是可包括有机氧化物或是无机氧化物,而适用于铜接垫32的保护层34目前的制作方式约有四种不同方法,叙述如下。 To achieve the purpose of protection, the protection layer 34 is usually a compound of silicon oxide, phosphosilicate glass, silicon nitride and silicon oxynitride compound composed compound, oxygen and wherein said silicon compound is an oxide may include an organic or an inorganic oxide , as applied to the copper pads 34 of the current production methods of the protective layer 32 is about four different methods described below.

[0080] 第一种保护层34制作方法可以是先利用化学气相沉积的步骤形成厚度介于0. 05 至0. 15微米间的一氮氧硅化合物层,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一氧硅化合物层在此氮氧硅化合物层上,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一氮硅化合物层在此氧硅化合物层上。 [0080] The first protective layer 34 may be a manufacturing method using a first step of chemical vapor deposition of a silicon oxynitride compound layer thickness in a range from 0.05 to 0.15 microns is formed between, followed by using a chemical vapor deposition step for forming an oxide thickness between silicon compound layer between 0.2 to 1.2 micrometers on this silicon oxynitride layer compound, followed by the step of using a chemical vapor deposition to a thickness of between 0.2 to 1.2 microns is formed between the a silicon nitride compound layer on this oxide layer a silicon compound.

[0081] 第二种保护层34制作方法可以是选择性地先利用化学气相沉积的步骤形成厚度介于0. 05至0. 15微米间的一第一氮氧硅化合物层,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一氧硅化合物层在此第一氮氧硅化合物层上,接着可以选择性地利用化学气相沉积的步骤形成厚度介于0. 05至0. 15微米间的一第二氮氧硅化合物层在此氧硅化合物层上,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一氮硅化合物层在此第二氮氧硅化合物层上或在此氧硅化合物层上,接着可以选择性地利用化学气相沉积的步骤形成厚度介于0. 05至0. 15微米间的一第三氮氧硅化合物层在此氮硅化合物层上,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一氧硅化合物层在此第三氮氧硅化合物层上或在此氮硅化合物层上。 [0081] The second protective layer 34 may be a method of selectively making the first step of chemical vapor deposition using a first oxynitride silicon compound layer thickness in a range from 0.05 to 0.15 microns is formed between, followed by chemical the step of forming a vapor-deposited oxide thickness between a silicon compound layer between 0.2 to 1.2 micrometers on this silicon oxynitride first compound layer, followed by the step of selectively using chemical vapor deposition with a thickness of between 0 a second silicon oxynitride interlayer compound is from 05 to 0.15 micrometers on this silicon oxide compound layer, followed by the use of a chemical vapor deposition step for forming a silicon nitride thickness of between 0.2 to 1.2 microns between step compound layer on this second oxynitride layer or a silicon compound on this oxide layer, a silicon compound, may then be selectively formed by chemical vapor deposition of a third thickness from nitrogen 0.05 to 0.15 microns between a silicon oxide compound layer on this layer of silicon nitride compound, followed by the step formed by chemical vapor deposition of silicon oxide thickness between an intermetallic compound layer is 0.2 to 1.2 microns in this third oxynitride layer or a silicon compound on this silicon nitride compound layer.

[0082] 第三种保护层34制作方法可以是先利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一第一氮硅化合物层,接着再利用化学气相沉积的步骤形成厚度介于0. 2 至1. 2微米间的一氧硅化合物层在此第一氮硅化合物层上,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一第二氮硅化合物层在此氧硅化合物层上。 [0082] A third method of manufacturing the protective layer 34 may be a first step of chemical vapor deposition using a first silicon nitride compound layer thickness between 0.2 to 1.2 microns is formed between, followed by the step of using a chemical vapor deposition forming an oxide thickness between the silicon compound layer is 0.2 to 1.2 micrometers on this silicon compound layer is a first nitrogen, followed by the step of using a chemical vapor deposition to a thickness of between 0.2 to 1.2 microns between a second nitrogen compound layer formed on this silicon oxide layer of a silicon compound.

[0083] 第四种保护层34制作方法可以是先利用化学气相沉积的步骤形成厚度介于0. 05 至0. 15微米间的一氮氧硅化合物层,接着利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一第一氧硅化合物层在此氮氧硅化合物层上,再来利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一氮硅化合物层在此第一氧硅化合物层上,接着再利用化学气相沉积的步骤形成厚度介于0. 2至1. 2微米间的一第二氧硅化合物层在此氮硅化合物层上。 [0083] A fourth manufacturing method of the protective layer 34 may be a first step using a chemical vapor deposition silicon oxynitride compound layer thickness in a range from 0.05 to 0.15 microns is formed between, then the step is formed by chemical vapor deposition of a thickness between a first oxide silicon compound layer between 0.2 to 1.2 micrometers on this silicon compound layer oxynitride, by chemical vapor deposition step is again formed of a thickness of between 0.2 to 1.2 microns a silicon nitride compound layer on this first oxide layer is a silicon compound, followed by using a chemical vapor deposition step of forming a second oxide thickness between the silicon compound layer is 0.2 to 1.2 micrometers on this silicon nitride layer compound .

[0084] 其中在半导体基底10上的保护层34的厚度一般是大于0. 35微米,在较佳的情况下,氮硅化合物层的厚度通常大于0. 3微米。 [0084] wherein a thickness on the semiconductor substrate 10 of the protective layer 34 is generally greater than 0.35 microns, in the preferred case, the thickness of the silicon nitride compound layer is typically greater than 0.3 micrometers.

[0085] 至此完成半导体基底10、细联机结构14及保护层34的解说,底下将以半导体基底10上具有铜接垫32而依序分别说明本发明的各个实施例。 [0085] This completes the semiconductor substrate 10, illustrating the fine line structure 14 and the protective layer 34, the bottom will having a copper pad 32 on a semiconductor substrate 10 and sequentially illustrate various embodiments of the present invention.

[0086] 第一实施例 [0086] First embodiment

[0087] 第一实施例是以在铜接垫32上形成金属层为说明标的。 [0087] In the first embodiment is a copper pad 32 is formed on the underlying metal layer is described. 请参阅图2a所示,首先利用溅镀、电镀或化学气相沉积的方式形成一第一金属层38在铜接垫32及保护层34上, 此第一金属层38的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、钒、铬、铬铜合金、铜、钽及氮化钽其中之一或所组成的群组的至少其中之一,接着同样利用溅镀、电镀或化学气相沉积的方式形成一种子层40在第一金属层38上,此种子层40有利于后续金属层的设置,因此种子层40的材质会随后续的金属层材质有所变化,例如当种子层40上是电镀形成金材质的金属层时,种子层40的材料是以金为佳;当要电镀形成银材质的金属层时,种子层40 的材料是以银为佳;当种子层40上是电镀形成铜材质的金属层时,种子层40的材料是以铜为佳;当要电镀形成钯材质的金属层时,种子层40的材料是以钯为佳;当要电镀形成钼材质的金属层时,种子层40的材料是 Referring to FIG 2a, is first formed by sputtering, electroplating or chemical vapor deposition a first embodiment the copper metal layer 38 on the pad 32 and a protective layer 34, a first material of this metal layer 38 is selected from titanium, wherein at least one of tungsten, cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, chromium-copper alloy, tantalum one of copper, tantalum nitride, and the group consisting of or wherein, followed similarly by sputtering, plating or chemical vapor deposition of a seed layer 40 is formed on the first metal layer 38, the seed layer 40 disposed facilitate subsequent metal layer, the seed layer material will thus continue the subsequent metal layer 40 of material vary, e.g. when a metal layer is formed by plating gold material on the seed layer 40, the material of the seed layer 40 is preferably gold; when the silver layer is to be formed by plating a metal material, the seed layer material 40 is preferably of silver; when seed 40 is a plating layer formed on the metal layer made of copper, the material of the seed layer 40 is preferably copper; when a palladium metal layer is formed to be plated material, the material of the seed layer 40 is preferably palladium; to be plated is formed when when the metal layer of molybdenum material, the seed layer material 40 is 以钼为佳;当要电镀形成铑材质的金属层时,种子层40 的材料是以铑为佳;当要电镀形成钌材质的金属层时,种子层40的材料是以钌为佳;当要电镀形成铼材质的金属层时,种子层40的材料是以铼为佳;当要电镀形成镍材质的金属层时,种子层40的材料是以镍为佳。 Preferably molybdenum; when forming the metal layer to be plated rhodium material, the material of the seed layer 40 is preferably rhodium; when the ruthenium metal layer is formed to be plated material, the material of the seed layer 40 preferably is ruthenium; when to rhenium plated metal layer is formed of a material, the material of the seed layer 40 is preferably rhenium; when a nickel layer is to be formed by plating a metal material, the material of the seed layer 40 is preferably of nickel.

[0088] 再来,请参阅图2b所示,利用旋涂(spin-coating)的方式形成一光阻层42在种子层40上,此光阻层42的型式是为正光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0088] again, see FIG. 2b, a photoresist layer 42 is formed on the seed layer 40, this type resist layer 42 is positive type photoresist by a spin coating (spin-coating) manner, the material can be nonionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 继续请参阅图2c所示,图案化此光阻层42以形成多数开口44暴露出种子层40,其中在形成开口44的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层42为感光材质时,则比如可以利用微影制造方法(photolithography process),将光阻层42图案化而形成多数开口44,而当光阻层42为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process), ^lfjfePlM 42 MM^WMM^MJf □ 44。 Referring to FIG. 2c continued, this photoresist layer 42 is patterned to form a plurality of openings 44 expose the seed layer 40, wherein during the formation of the opening 44 is 1 times (IX) of the stepper (steppers) or scanner (scanners) exposing and developing the photoresist layer 42 and then when the photosensitive material, it can be such a method for producing lithography (photolithography process) by using the photoresist layer 42 is patterned to form a plurality of openings 44, and when the photoresist when a non-photosensitive material layer 42, it may be utilized such as the method for producing a lithography (photolithography process and etching process), ^ lfjfePlM 42 MM ^ WMM ^ MJf □ 44.

[0089] 另,在形成光阻层42及其开口44上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层42,其中若是以网版印刷方式形成光阻层42则可直接在光阻层42内形成多数开口44而暴露出种子层40,然若是以热压合干膜方式形成光阻层42,则可在形成光阻层42之后,再形成多数开口44暴露出种子层40,但也可直接在光阻层42内形成多数开口44 而暴露出种子层40。 [0089] Also, a photoresist layer 42 is formed on its opening 44, a photoresist layer 42 of the present invention can take advantage of a screen printing manner or thermocompression bonding dry film, screen printing wherein if the photoresist layer is formed after most of the opening 42 may be 44 to expose the seed layer 40 is formed directly in the photoresist layer 42, and then thermocompression bonding if a dry film resist layer 42 is formed, a photoresist layer 42 may be formed, then forming a plurality of openings 44 expose the seed layer 40, but a plurality of openings 44 to expose the seed layer 40 may be formed directly in the photoresist layer 42.

[0090] 接着请参阅图2d所示,以电镀或无电电镀的方式形成厚度大于1. 6微米或是大于2微米的一第二金属层46在开口44所曝露出的种子层40上,此第二金属层46较佳的厚度是介于2微米至10微米之间,且此第二金属层46比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第二金属层46除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0090] Next, please refer to Figure 2d, electroplating or electroless plating is formed on the seed layer 40 a thickness greater than 1.6 microns, or a second metal layer is greater than 46 microns 2 in the opening 44 exposing, the preferred thickness of this second metal layer 46 is between 2 to 10 microns, and this second metal layer 46 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium or rhenium single-layer metal layer structure, or a composite layer composed of the metal material consisting of, but the second metal layer 46 in addition to the above-mentioned metal material may be substituted using the solder material, this material is a solder alloy layer is a tin-lead, tin-silver alloy layer, tin-silver-copper alloy layer, a lead-free solder layer. 若此第二金属层46为焊料材质,则第二金属层46的较佳厚度是介于3微米至150微米之间。 If this second metal layer 46 is a solder material, the preferred thickness of the second metal layer 46 is between 3 microns to 150 microns.

[0091] 最后,如图2e所示,去除光阻层42以及未在第二金属层46下的种子层40与第一金属层38,而在去除第一金属层38与种子层40的方式上,可分为干式蚀刻及湿式蚀刻,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层46下的种子层40与第一金属层38,而进行湿式蚀刻时若种子层40为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层38为钛钨合金时,则可使用双氧水进行去除。 [0091] Finally, shown in Figure 2e, the photoresist layer 42 is removed and not in the seed layer 40 and the first metal layer a second metal layer 46 at 38, and the metal layer 38 of the first embodiment is removed and the seed layer 40 on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etching attack is not removed in the seed layer 40 and the second metal layer 46 of the first metal layer 38, wet etching is performed If the seed layer 40 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 38 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0092] 以图2e所示的结构,本发明可透过曝露于外界的第二金属层46,与打线接合、贴带自动接合(Tape Automated Bonding,TAB)、玻璃复晶接合(Chip-on-glass,COG)或薄膜复晶接合(chip on film,C0F)等制造方法相互匹配。 [0092] In the structure shown in Figure 2e, the present invention may be 46, and wire bonded through the second metal layer exposed to the outside, attached to tape automated bonding (Tape Automated Bonding, TAB), a glass engaging polycrystalline (ChIP- on-glass, COG) or polycrystalline film bonded (chip on film, C0F) match each other manufacturing methods. 例如请参阅图2f至图2h所示,其是为本实施例应用于打线接合的制造方法步骤的剖面示意图,首先请参阅图2f所示,在完成图2e所示的结构后,接着形成一聚合物层48在保护层34与第二金属层46上,其中此聚合物层48具有絶缘功能,其材质比如为热塑性塑料、热固性塑料、聚醯亚胺(p0lyimide,PI)、 苯基环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料,另外此聚合物层48主要是利用旋涂方式设置,然亦可利用热压合干膜或网版印刷方式进行。 See e.g. Figure 2f to 2h, the present embodiment which is an embodiment for producing a cross-sectional schematic view of the method steps is applied to wire bonding, see Figure 2f is first shown, after the completion of the structure shown in FIG. 2E, is then formed a polymer layer 48 on the protective layer 34 and the second metal layer 46, wherein the polymer layer 48 having an insulating function, the material such as a thermoplastic, thermosetting plastic, polyimide (p0lyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy, parylene-based polymer, solder-mask material, elastic material, or porous dielectric material, this additional polymer layer 48 is mainly provided by spin coating, and then thermocompression bonding can take advantage of a dry film or screen printing manner.

[0093] 继续请参阅图2g所示,利用蚀刻方式对此聚合物层48进行图案化,以形成多数开口50曝露出第二金属层46,其中,当聚合物层48为感光材质时,则比如可以利用微影制造方法(photolithography process),将聚合物层48图案化;当聚合物层48为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process andetching process),将聚合物层48图案化。 [0093] Please continue to refer to Figure 2g, this embodiment by etching the polymer layer 48 is patterned to form an opening 50 exposing the majority of the second metal layer 46, wherein, when the polymer layer 48 is a photosensitive material, then the method can be used for example for producing lithography (photolithography process), the patterning of the polymer layer 48; the polymer layer 48 when the non-photosensitive material, such as the lithography method can be used for producing (photolithography process andetching process), the polymer layer 48 is patterned. 将聚合物层48图案化之后,可利用烘烤加热、微波加热、 红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)聚合物层48。 After the patterning of the polymer layer 48 may be utilized bake heating, microwave heating, infrared heating manner wherein one is heated to a temperature of 200 ° C or with heating between 320 degrees Celsius to between 320 degrees Celsius and C a temperature between 450 degrees to harden (curing) polymer layer 48.

[0094] 接着请参阅图2h,进行切割半导体基底10形成多数半导体组件52,并且藉由打线制造方法形成打线导线54在所曝露出的第二金属层46顶面上,使半导体组件52电连接至外界电路,其中以第二金属层46为金层、钼层或钯层时,是为进行打线制造方法的较佳材质。 [0094] Next, please refer to FIG. 2h, dicing of the semiconductor substrate 10 forming a plurality of semiconductor elements 52, and by a method for producing wire bonding wires 54 are formed 46 exposes the surface of the second metal layer of the semiconductor element 52 when electrically connected to the outside circuit, wherein the second metal layer 46 is a gold layer, a palladium layer, or molybdenum layer, a material is preferred to perform the method of manufacturing a wire.

[0095] 另,亦可如图2i所示,在完成图2e所形成的结构后,进行切割半导体基底10形成多数半导体组件52,并藉由卷带自动接合制造方法,使半导体组件52上的第二金属层46接合在一软性基板56上,接着再以一聚合物58包覆软性基板56及第二金属层46的接合处; 此外,请参阅图2j所示,也可藉由玻璃覆晶封装技术,利用异方性导电胶(ACF)60将半导体组件52上的第二金属层46电性连接位于一玻璃基板62上的一接垫;请参阅如图2k所示,同样也可藉由薄膜复晶技术,利用异方性导电胶60将半导体组件52上的第二金属层46电性连接位于软性基板64上的一接垫,接着再以一聚合物58包覆软性基板64及第二金属层46的接合处。 [0095] Also, as shown also in FIG. 2i, after completion of the structure of FIG. 2e formed, dicing of the semiconductor substrate 10 forming a plurality of semiconductor elements 52, and by tape automated bonding method for manufacturing the semiconductor assembly 52 the second metal layer 46 is bonded on a flexible substrate 56, followed by coating with a flexible polymer substrate 58 and the second metal layer 56 at the junction 46; in addition, see FIG. 2j shown, may be by chip on glass technology, using anisotropic conductive adhesive (ACF) 60 of the second metal layer 46 is electrically connected to the semiconductor element 52 is located at a pad on a glass substrate 62; see FIG. 2k, the same also by thin-film polycrystalline technology, using anisotropic conductive adhesive 60 on the second metal layer of the semiconductor device 5246 is electrically connected to a pad located on the flexible substrate 64, followed by coating with a polymer 58 the flexible substrate 64 and the second joint metal layer 46.

[0096] 第二实施例 [0096] Second Embodiment

[0097] 此实施例与第一实施例相似,不同点在于开口44所曝露出的种子层40上形成两层金属层。 [0097] Example of embodiment of this embodiment is similar to the first embodiment, except that the two metal layers 40 formed on the opening 44 exposing the seed layer. 请参阅图3a所示,在完成图2c所示的结构后,接着以电镀的方式形成一第二金属层66在开口44所曝露出的种子层40上,而此第二金属层66的厚度可以是厚度大于1. 6 微米或是介于2微米至10微米之间,又此第二金属层66比如是厚度介于0. 1微米至10微米之间的铜(较佳厚度是介于0. 5微米至5微米之间),或者是厚度介于0. 1微米至10微米之间的镍(较佳厚度是介于0. 5微米至3微米之间)的单层金属层结构。 See FIG. 3a, after completion of the structure shown in to Figure 2c, followed by plating is formed in a second metal layer 66 exposing the opening 44 on the seed layer 40, the thickness of this second metal layer 66 may be a thickness greater than 1.6 microns, or between 2 to 10 microns, and this second metal layer 66 such as copper having a thickness of between (preferably a thickness of between 0.1 to 10 micrometers is between between 0.5 microns to 5 microns), or between the nickel thickness between 0.1 to 10 micrometers (preferably a thickness of between 0.5 to 3 microns) of single-layer metal layer structure .

[0098] 继续请参阅图3b所示,以电镀或无电电镀的方式形成一第三金属层68在第二金属层66上,而此第三金属层68的厚度可以是大于1. 6微米、大于2微米或是介于2微米至10微米之间,又此第三金属层68比如是金、铜、银、钯、钼、铑、钌、铼或镍的单层金属层结构,或由上述金属材质所组成的复合层,惟第三金属层68除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0098] Please refer to FIG. 3b continue, electroplating or electroless plating is formed a third metal layer 68 on the second metal layer 66, the thickness of this third metal layer 68 can be greater than 1.6 micrometers , greater than 2 microns, or between 2 to 10 microns, and this is the third metal layer 68 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium, rhenium single layer structure of metal or nickel, or layer composed of the composite material consisting of a metal, but the third metal layer 68 in addition to the above-mentioned metal material may be substituted using the solder material, the solder material is a tin-lead alloy layer, a tin-silver alloy layer, tin-silver-copper alloy layer, a lead-free solder layer. 若此第三金属层68为焊料材质,则第三金属层68的较佳厚度是介于3微米至150微米之间。 If this third metal layer 68 is a solder material, the preferred thickness of the third metal layer 68 is between 3 microns to 150 microns.

[0099] 最后,如图3c所示,去除光阻层42以及未在第三金属层68下的种子层40与第一金属层38,而在去除第一金属层38与种子层40的方式上,可分为干式蚀刻及湿式蚀刻,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层42下的种子层40与第一金属层38,而进行湿式蚀刻时若种子层40为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层38为钛钨合金时,则可使用双氧水进行去除。 [0099] Finally, shown in Figure 3c, photoresist layer 42 is removed and not the seed layer 68 in the third metal layer 40 and the first metal layer 38, in a manner removing the first metal layer 38 and the seed layer 40 on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etching attack is not removed in the seed layer 40 and the second metal layer 42 of the first metal layer 38, wet etching is performed If the seed layer 40 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 38 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0100] 另外,请参阅图3d至图3g所示,在完成图3c所示的结构后,接着切割此半导体基底10形成多数半导体组件52,而每一半导体组件52皆可使用打线制造方法、卷带自动接合制造方法、玻璃覆晶封装技术及薄膜复晶接合技术连接至外界电路上,其中接合的过程已在第一实施例中解说,在此就不重复说明。 [0100] Further, see Figure 3d to 3g shown, after the completion of the structure shown in to Figure 3c, followed by dicing the semiconductor substrate 10 forming a plurality of semiconductor elements 52, 52 and each semiconductor element manufacturing method of use of either wire , tape automated bonding process for producing a method, chip on glass technology and thin film polycrystalline connected to the outside bonding techniques circuit, wherein the engagement has been illustrated in the first embodiment, the description is not repeated here.

[0101] 第三实施例 [0101] Third embodiment

[0102] 此实施例与第一实施例相似,不同点在于开口44所曝露出的种子层40上形成三层金属层。 [0102] Example of embodiment of this embodiment is similar to the first embodiment, except that the three metal layers 40 formed on the opening 44 exposing the seed layer. 请参阅图4a所示,在完成图2c所示的结构后,接着以电镀的方式形成厚度介于0. 1微米至10微米之间的一第二金属层70在开口44所曝露出的种子层40上,例如电镀一铜层在开口44所曝露出的种子层40上,而此铜层较佳的厚度是介于0. 5微米至5微米之间。 See FIG. 4a, after the completion of the structure shown in to Figure 2c, followed by plating thickness is formed between a second seed metal layer between 0.1 micron to 10 microns 70 to expose the opening 44 layer 40, for example, a copper plating layer on the seed layer 44 exposing the opening 40 of, and this copper layer is preferably a thickness of between 0.5 micrometers to 5 micrometers.

[0103] 接着请参阅图4b所示,以电镀或无电电镀的方式形成厚度介于0. 1微米至10微米之间的一第三金属层72在第二金属层70上,例如电镀一镍层在第二金属层70上,而此镍层较佳的厚度是介于0. 5微米至3微米之间,又例如无电电镀一材质为金、银、钼、钯、铑、 钌、铼的金属在第二金属层70上。 [0103] Next, please refer to FIG. 4b, electroplating or electroless plating is formed in a third metal layer thickness of between 0.1 between 72 and 10 microns on the second metal layer 70, such as electroplating a a nickel layer on the second metal layer 70, while the nickel layer is preferably a thickness of between 0.5 to 3 micrometers, and for example, a material for the electroless plating of gold, silver, molybdenum, palladium, rhodium, ruthenium rhenium metal on the second metal layer 70.

[0104] 再来请参阅图4c所示,以电镀或无电电镀的方式形成一第四金属层74在第三金属层72上,而此第二金属层46的厚度可以是大于1. 6微米、大于2微米、介于2微米至10 微米之间或介于2微米至30微米之间,又此第四金属层74比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第四金属层74除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0104] Please refer to FIG. 4c again, electroplating or electroless plating a fourth metal layer is formed on the third metal layer 74 at 72, the thickness of this second metal layer 46 can be greater than 1.6 micrometers , greater than 2 microns, between 2 to 30 microns between 2 to 10 microns or between, and this is the fourth metal layer 74 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium or rhenium single metal layer structure, or a composite layer composed of the metal material consisting of, but the fourth metal layer 74 in addition to the above-mentioned metal material may be substituted using the solder material, this material is a solder layer of tin-lead alloy, tin-silver alloy layer, a tin-silver-copper alloy layer, a lead-free solder layer. 若此第四金属层74为焊料材质,则第四金属层74的较佳厚度是介于3微米至150微米之间。 If this fourth metal layer 74 is a solder material, the preferred thickness of the fourth metal layer 74 is between 3 microns to 150 microns.

[0105] 最后请参阅图4d所示,去除光阻层42以及未在第四金属层74下的种子层40与第一金属层38,而在去除第一金属层38与种子层40的方式上,可分为干式蚀刻及湿式蚀刻, 其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层42下的种子层40与第一金属层38,而进行湿式蚀刻时若种子层40为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层38为钛钨合金时,则可使用双氧水进行去除。 [0105] Referring to FIG. 4d Finally, the photoresist layer 42 is removed and not the seed layer 74 in the fourth metal layer 40 and the first metal layer 38, in a manner removing the first metal layer 38 and the seed layer 40 on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etching attack is not removed in the seed layer 40 and the second metal layer 42 of the first metal layer 38, wet etching is performed If the seed layer 40 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 38 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide. [0106] 另外,请参阅图4e至图4h所示,在完成图4d所示的结构后,接着切割此半导体基底10形成多数半导体组件52,而每一半导体组件52皆可使用打线制造方法、卷带自动接合制造方法、玻璃覆晶封装技术及薄膜复晶接合技术连接至外界电路上,其中接合的过程已在第一实施例中解说,在此就不重复说明。 [0106] In addition, please refer to Figure 4e shown in FIG. 4h, after completion of the structure shown in FIG. 4d, followed by dicing the semiconductor substrate 10 forming a plurality of semiconductor elements 52, 52 and each semiconductor element manufacturing method of use of either wire , tape automated bonding process for producing a method, chip on glass technology and thin film polycrystalline connected to the outside bonding techniques circuit, wherein the engagement has been illustrated in the first embodiment, the description is not repeated here.

[0107] 第四实施例 [0107] Fourth embodiment

[0108] 此实施例与第一实施例相似,不同点在于开口44所曝露出的种子层40上先电镀形成两层金属层后,再以无电电镀形成两层金属。 After [0108] This embodiment is similar to the first embodiment, except that the 40 first plated metal layer is formed of two openings 44 expose the seed layer, and then electroless plating to form two layers of metal. 请参阅图5a所示,在完成图2c所示的结构后,接着以电镀的方式形成厚度介于0. 1微米至10微米之间的一第二金属层76在开口44所曝露出的种子层40上,例如电镀一铜层在开口44所曝露出的种子层40上,而此铜层较佳的厚度是介于0. 5微米至5微米之间。 Please refer to FIG. 5a, after completion of the structure shown in to Figure 2c, followed by plating thickness is formed between a second seed metal layer between 0.1 micron to 10 microns 76 to expose the opening 44 layer 40, for example, a copper plating layer on the seed layer 44 exposing the opening 40 of, and this copper layer is preferably a thickness of between 0.5 micrometers to 5 micrometers.

[0109] 继续请参阅图5b所示,以电镀的方式形成厚度介于0. 1微米至10微米之间的一第三金属层78在第二金属层76上,例如电镀一镍层在第二金属层76上,而此镍层较佳的厚度是介于0. 5微米至3微米之间。 [0109] Please continue to refer to Figure 5b, is formed by electroplating of a first thickness between the third metal layer between 0.1 micron to 10 microns 78 on the second metal layer 76, a plated nickel layer e.g. on the titanium metal layer 76, while the nickel layer is preferably a thickness of between 0.5 to 3 micrometers.

[0110] 接着请参阅图5c所示,以无电电镀的方式形成厚度介于0. 001微米至2微米之间的一第四金属层80在第三金属层78上,此第四金属层80比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构。 [0110] Next, please refer to FIG. 5c, electroless plating to a thickness between 80 is formed on the third metal layer 78, the fourth metal layer a fourth metal layer is between 0.001 to 2 microns 80 is for example gold, copper, silver, palladium, molybdenum, rhodium, ruthenium single layer structure or a metallic rhenium.

[0111] 再来请参阅图5d所示,以无电电镀的方式形成厚度介于2微米至30微米之间的一第五金属层82在第四金属层80上,此第五金属层82比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构。 [0111] Referring to FIG. 5d again, electroless plating to a thickness of between 82 is formed on the fourth metal layer 80, the fifth metal layer between a fifth metal layer 2, such as 82 to 30 microns gold, copper, silver, palladium, molybdenum, rhodium, ruthenium single layer structure or a metallic rhenium.

[0112] 最后请参阅图5e所示,去除光阻层42以及未在第五金属层82下的种子层40与第一金属层38,而在去除第一金属层38与种子层40的方式上,可分为干式蚀刻及湿式蚀刻, 其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层42下的种子层40与第一金属层38,而进行湿式蚀刻时若种子层40为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层38为钛钨合金时,则可使用双氧水进行去除。 [0112] Finally, please refer to FIG. 5e, the photoresist layer 42 is removed and not in the seed layer 40 and the first metal layer of the fifth metal layer 82 at 38, and the metal layer 38 of the first embodiment is removed and the seed layer 40 on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etching attack is not removed in the seed layer 40 and the second metal layer 42 of the first metal layer 38, wet etching is performed If the seed layer 40 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 38 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0113] 另外,请参阅图5f至图5i所示,在完成图5e所示的结构后,接着切割此半导体基底10形成多数半导体组件52,而每一半导体组件52皆可使用打线制造方法、卷带自动接合制造方法、玻璃覆晶封装技术及薄膜复晶接合技术连接至外界电路上,其中接合的过程己在第一实施例中解说,在此就不重复说明。 [0113] Further, see Fig. 5f to 5i shown, after the completion of the structure shown in FIG. 5E, followed by dicing the semiconductor substrate 10 forming a plurality of semiconductor elements 52, 52 and each semiconductor element manufacturing method of use of either wire , tape automated bonding process for producing a method, chip on glass technology and thin film polycrystalline connected to the outside bonding techniques circuit, which is already engaged in a first embodiment illustrated embodiment, this description is not repeated.

[0114] 第五实施例 [0114] Fifth Example

[0115] 此实施例是由图Ie所发展而来,请参阅图6a所示,首先利用溅镀、电镀或化学气相沉积的方式形成一第一金属层84在铜接垫32及保护层34上,此第一金属层84的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、钒、铬、铬铜合金、铜、钽及氮化钽其中之一或所组成的群组的至少其中之一。 [0115] This embodiment is developed from the FIG. Ie is, see FIG. 6a, first by sputtering, electroplating or chemical vapor deposition of a first metal layer is formed on the copper pad 84 and a protective layer 34 32 on this first metal layer 84 material is selected from titanium, tantalum one of tungsten, cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, chromium-copper alloy, copper, tantalum nitride, and wherein the composition or at least one of the group.

[0116] 继续请参阅图6b所示,利用溅镀、电镀或化学气相沉积的方式形成一第二金属层86在第一金属层84上,此第二金属层86的材质是选自铝、金、银、钯、钼、铑、钌、铼、锡铅合金及锡银合金其中之一或所组成的群组的至少其中之一。 [0116] Please continue to refer to Figure 6b, by sputtering, electroplating or chemical vapor deposition is formed a second metal layer 86 on the first metal layer 84, metal layer 86 of this second material is selected from aluminum, gold, silver, palladium, molybdenum, rhodium, at least one of ruthenium, rhenium, tin-lead alloy, and tin-silver alloy wherein one or the group consisting of.

[0117] 接着,请参阅图6c所示,利用旋涂(spin-coating)的方式形成一光阻层88在第二金属层86上,此光阻层88的型式是为负光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0117] Next, please refer to FIG. 6C, by spin coating (spin-coating) of a photoresist layer 88 is formed on the second metal layer 86, the photoresist layer 88 of this type is a negative type photoresist, the material may be non-ionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 继续请参阅图6d所示,图案化此光阻层88以形成多数开口暴露出第二金属层86,其中在形成开口的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层88为感光材质时,则比如可以利用微影制造方法(photolithography process),将光阻层88图案化而形成多数开口,而当光阻层88为非感光材质时,则比如可以利用微影蚀刻制造方法 Referring to FIG. 6d shown continued, this photoresist layer 88 is patterned to form a plurality of openings expose the second metal layer 86, which is 1-fold (IX) in the process of forming stepper openings (steppers) or scanner (scanners) exposing and developing the photoresist layer 88 is then when the photosensitive material, it can be such a method for producing lithography (photolithography process) using the resist layer 88 is patterned to form a plurality of openings, and when the photoresist layer when a non-photosensitive material 88, such as the photolithography method can be used for producing

(photolithography process and etching process),光阻层88 图案化而形成多数开□。 (Photolithography process and etching process), a photoresist layer 88 is patterned to form the most open □.

[0118] 另,在形成光阻层88及其开口上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层88,其中若是以网版印刷方式形成光阻层88则可直接在光阻层88内形成多数开口而暴露出第二金属层86,然若是以热压合干膜方式形成光阻层88,则可在形成光阻层88之后,再形成多数开口暴露出第二金属层86,但也可直接在光阻层88内形成多数开口而 [0118] Also, a photoresist layer 88 is formed on its opening, the present invention also by screen printing or thermocompression bonding a dry film resist layer 88 is formed, in which the screen printing manner if the photoresist layer 88 is formed can be formed directly in the photoresist layer 88 after the plurality of openings to expose the second metal layer 86, and then thermocompression bonding if a dry film resist layer 88 is formed, it may be formed in the photoresist layer 88, then forming a plurality of openings the second metal layer 86 is exposed, but the plurality of openings may be formed directly in the photoresist layer 88

暴露出第二金属层86。 The second metal layer 86 is exposed.

[0119] 再来,请参阅图6e所示,首先去除未在光阻层88下的第二金属层86与第一金属层84,接着再去除光阻层88。 [0119] again, see FIG. 6E, first removing the second metal layer 86 and the first metal layer 84 is not in the photoresist layer 88, photoresist layer 88 is then removed again. 请参阅图6f所示,在完成图6e所示的结构后,利用溅镀、电镀或化学气相沉积的方式形成一第三金属层90在第二金属层86及保护层34上,此第三金属层90的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、钒、铬、铬铜合金、铜、钽及氮化钽其中之一或所组成的群组的至少其中之一。 Referring to FIG. 6f, after the completion of the structure shown in FIG. 6E, by sputtering, electroplating or chemical vapor deposition 90 is formed on the second metal layer 86 and a protective layer 34, a third metal layer of this third material of the metal layer 90 is selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, chromium-copper alloy, tantalum one of copper, tantalum nitride, and wherein the group consisting of or at least one of them. 接着同样利用溅镀、电镀或化学气相沉积的方式形成一种子层92在第三金属层90上,此种子层92有利于后续金属层的设置,因此种子层92的材质会随后续的金属层材质有所变化,例如当种子层92上是电镀形成金材质的金属层时,种子层92的材料是以金为佳;当要电镀形成银材质的金属层时,种子层92的材料是以银为佳;当种子层92上是电镀形成铜材质的金属层时,种子层92的材料是以铜为佳;当要电镀形成钯材质的金属层时,种子层92的材料是以钯为佳;当要电镀形成钼材质的金属层时,种子层92的材料是以钼为佳;当要电镀形成铑材质的金属层时,种子层92的材料是以铑为佳;当要电镀形成钌材质的金属层时,种子层92的材料是以钌为佳;当要电镀形成铼材质的金属层时,种子层92的材料是以铼为佳;当要电镀形成镍材质的金属层时,种子层92的材料是以 Then using the same sputtering, electroplating or chemical vapor deposition of a seed layer 92 is formed on the third metal layer 90, the seed layer 92 disposed facilitate subsequent metal layer, the seed layer material will thus as subsequent layers of metal 92 material vary, for example, when the seed layer is formed by plating a metal layer on the gold material 92, the material of the seed layer 92 is preferably gold; when the silver layer is to be formed by plating a metal material, the seed layer material 92 is silver is preferred; when plated on the seed layer 92 is formed of a metal layer made of copper, a copper seed layer material is preferably 92; to be plated when the material forming the metal layer of palladium, the palladium seed layer 92 material is of good; when the plated metal layer is formed to be a molybdenum material, the material of the seed layer 92 preferably is molybdenum; when forming the metal layer to be plated rhodium material, the material of the seed layer 92 is preferably rhodium; to be plated is formed when when the metal layer of ruthenium material, the material of the seed layer 92 preferably is ruthenium; when plated metal layer is formed to be made of rhenium, the seed layer material 92 is preferably rhenium; when a nickel layer is to be formed by plating a metal material , the seed layer material is 92 为佳。 Better.

[0120] 继续请参阅图6g所示,利用旋涂(spin-coating)的方式形成一光阻层94在种子层92上,此光阻层94的型式是为正光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0120] Referring to FIG. 6g continues, the photoresist layer 94 is formed on a seed layer 92, this type resist layer 94 is positive type photoresist by a spin coating manner (spin-coating), which may be made of nonionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 接着请参阅图6h所示,图案化此光阻层94以形成多数开口96暴露出种子层92,其中在形成开口96的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层94为感光材质时,则比如可以利用微影制造方法(photolithography process),将光阻层94图案化而形成多数开口96,而当光阻层94为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process), 光阻层94 图案化而形成多数开口96。 Next, please refer to FIG. 6h, the pattern of this resist layer 94 to form a plurality of openings 96 expose the seed layer 92, wherein during the formation of the opening 96 is 1 times (IX) of the stepper (steppers) or scanner (scanners) exposing and developing the photoresist layer 94 and then when the photosensitive material, it can be such a method for producing lithography (photolithography process) by using the photoresist layer 94 is patterned to form a plurality of openings 96, and when the photoresist when a non-photosensitive material layer 94, may be utilized such as the method of manufacturing a lithography (photolithography process and etching process), a photoresist layer 94 is patterned to form a plurality of openings 96.

[0121] 另,在形成光阻层94及其开口96上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层94,其中若是以网版印刷方式形成光阻层94则可直接在光阻层94内形成多数开口96而暴露出种子层92,然若是以热压合干膜方式形成光阻层94,则可在形成光阻层94之后,再形成多数开口96暴露出种子层92,但也可直接在光阻层94内形成多数开口96 而暴露出种子层92。 [0121] Also, a photoresist layer is formed on the openings 96 and 94, the present invention also by screen printing or thermocompression bonding a dry film photoresist layer 94 is formed, if the screen printing which is formed a photoresist layer after most of the opening 94 to expose the seed layer 96 and 92 may be formed directly in the photoresist layer 94, and then thermocompression bonding if a dry film resist layer 94 is formed, may be formed in the photoresist layer 94, then forming a plurality of openings 96 expose the seed layer 92, but may be a plurality of openings 96 to expose the seed layer 92 is formed directly in the photoresist layer 94.

[0122] 接着请参阅图6i所示,以电镀或无电电镀的方式形成厚度介于0. 1微米至10微米之间的一第四金属层98在开口96所曝露出的种子层92上,此第四金属层98比如是金、 铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第四金属层98除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0122] Next, please refer to FIG. 6i, the electroplating or electroless plating is formed in a thickness between the fourth metal layer between 0.1 to 10 micrometers at the opening 98 expose the seed layer 96 92 this fourth metal layer 98 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium single layer structure of metal or rhenium, or a composite layer composed of the metal material consisting of, but in addition to the fourth metal layer 98 an outer metallic material of the mentioned substituents may also be used solder material, the solder material is a tin-lead alloy layer, a tin-silver alloy layer, a tin-silver-copper alloy layer, a lead-free solder layer. 若此第四金属层98为焊料材质,则第四金属层98的较佳厚度是介于3微米至150微米之间。 If this fourth metal layer 98 is a solder material, the preferred thickness of the fourth metal layer 98 is between 3 microns to 150 microns.

[0123] 最后,如图6j所示,去除光阻层94以及未在第四金属层98下的种子层92与第一金属层90,而在去除第一金属层90与种子层92的方式上,可分为干式蚀刻及湿式蚀刻,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第四金属层98下的种子层92与第一金属层90,而进行湿式蚀刻时若种子层92为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层90为钛钨合金时,则可使用双氧水进行去除。 [0123] Finally, as shown in FIG. 6j, photoresist layer 94 is removed and not in the seed layer 92 and the first metal layer of the fourth metal layers 98 and 90, in a first embodiment the metal layer 90 and the seed layer 92 is removed on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputtering strike is not removed by etching the seed layer 92 and the first metal layer 98 in the fourth metal layer 90, wet etching is performed If the seed layer seed layer 92 is gold, may be used when removing the potassium iodide solution, if the first metal layer 90 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0124] 此外,当保护层34的顶层是为氧硅化合物层时,若使用干式蚀刻去除未在第四金属层98下的种子层92与第一金属层90则会如图6k所示,保护层34顶层的氧硅化合物层亦会被蚀刻,而在保护层34与第一金属层84之间形成一间隙100。 [0124] Further, when the top layer is a protective layer 34 is a silicon oxide compound layer, if not removed using a dry etch the seed layer 92 in FIG. 6k of the first metal layer and the fourth metal layer 98 will be as shown at 90 , a silicon oxide compound layer is the top layer 34 will also be etched in the protective layer, and between the protective layer 34 and the first metal layer 84 a gap 100 is formed.

[0125] 另,在完成图6j所示的结构后,接着切割此半导体基底10形成多数半导体组件, 而每一半导体组件皆可使用打线制造方法、卷带自动接合制造方法、玻璃覆晶封装技术及薄膜复晶接合技术连接至外界电路上,其中接合的过程已在第一实施例中解说,在此就不重复说明。 [0125] Also, after completion of the structure shown in FIG. 6J, followed by dicing the semiconductor substrate 10 is formed the majority of semiconductor elements and each semiconductor element manufacturing method of use of either wire bonding, tape automated bonding method for producing chip on glass process technology and polycrystalline thin films connected to the outside bonding techniques circuit, wherein the engagement has been illustrated in the first embodiment, the description is not repeated here.

[0126] 第六实施例 [0126] Sixth Example

[0127] 此实施例与第五实施例相似,不同点在于开口96所曝露出的种子层92上形成三金属层。 [0127] Example of the fifth embodiment of this embodiment is similar, except that the tri-metal layer 92 is formed an opening 96 exposing the seed layer. 请参阅图7a所示,在完成图6h所示的结构后,接着以电镀的方式形成厚度介于0. 1微米至10微米之间的一第四金属层102在开口96所曝露出的种子层92上,例如电镀一铜金属在开口96所曝露出的种子层92上。 Please refer to FIG. 7a, after completion of the structure shown in FIG. 6h, followed by plating is formed between a fourth metal layer thickness between 0.1 to 10 micrometers at the opening 102 exposing the seeds 96 layer 92, for example, a copper plated in the openings 96 expose the seed layer 92. 再来请参阅图7b所示,同样以电镀的方式形成厚度介于0. 1微米至10微米之间的一第五金属层104在第四金属层102上,例如电镀一镍金属在第四金属层102上。 See again FIG. 7b, in the same manner as the plating thickness is formed between a fifth metal layer 104 is between 0.1 and 10 microns on the fourth metal layer 102, for example, a nickel plated metal in the fourth layer 102. 继续请参阅图7c所示,以电镀或无电电镀的方式形成厚度介于0. 1微米至10微米之间的一第六金属层106在第五金属层104上,此第六金属层106 比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第六金属层106除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 Please refer to FIG. 7c continued to electroplating or electroless plating is formed between a sixth metal layer thickness between 0.1 to 10 micrometers 106 on the fifth metal layer 104, the sixth metal layer 106 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium single layer structure of metal or rhenium, or a composite layer composed of the metal material consisting of, but in addition to the metal material of the metal layer 106 mentioned sixth substituted solder material may also be used, as this material is a tin-lead solder alloy layer, a tin-silver alloy layer, a tin-silver-copper alloy layer, a lead-free solder layer. 若此第六金属层106为焊料材质, 则第六金属层106的较佳厚度是介于3微米至150微米之间。 If this sixth metal layer 106 is a solder material, the preferred thickness of the sixth metal layer 106 is between 3 microns to 150 microns. [0128] 最后,如图7d所示,去除光阻层94以及未在第六金属层106下的种子层92与第一金属层90,而在去除第一金属层90与种子层92的方式上,可分为干式蚀刻及湿式蚀刻, 其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第六金属层106下的种子层92与第一金属层90,而进行湿式蚀刻时若种子层92为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层90为钛钨合金时,则可使用双氧水进行去除。 [0128] Finally, shown in Figure 7d, the photoresist layer is removed and the seed layer 94 not under the sixth metallic layer 106 of the first metal layer 90 and 92, and in the embodiment 90 with the seed layer a first metal layer 92 is removed on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputtering strike is not removed by etching the seed layer 92 and the first metal layer 90 under the sixth metallic layer 106, wet etching is performed If the seed layer seed layer 92 is gold, may be used when removing the potassium iodide solution, if the first metal layer 90 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0129] 此外,在完成图7d所示的结构后,接着切割此半导体基底10形成多数半导体组件,而每一半导体组件皆可使用打线制造方法、卷带自动接合制造方法、玻璃覆晶封装技术及薄膜复晶接合技术连接至外界电路上,其中接合的过程已在第一实施例中解说,在此就不重复说明。 [0129] Further, after completion of the structure shown in FIG. 7d, followed by dicing the semiconductor substrate 10 is formed the majority of semiconductor elements and each semiconductor element manufacturing method of use of either wire bonding, tape automated bonding method for producing chip on glass process technology and polycrystalline thin films connected to the outside bonding techniques circuit, wherein the engagement has been illustrated in the first embodiment, the description is not repeated here.

[0130] 第七实施例 [0130] Seventh embodiment

[0131] 此实施例是为第一实施例在连接线路(interconnection)上的应用,然为使结构简而易懂,仅绘示出两个铜接垫32利用一金属线路连接在一起的示意图,并以此做下列说明,但并不能以此限定本发明。 [0131] This embodiment is an application example in the connecting line (Interconnection) a first embodiment, and then to make the structure simple and easy to understand, only shows a schematic view of two copper pads 32 using a metal wiring connected together , and thus make the following description, but this does not limit the present invention.

[0132] 请参阅图8a所示,一半导体基底10上的细联机结构14具有二铜接垫32, 分别为第一铜接垫320与第二铜接垫322。 [0132] Referring to FIG 8a, the fine line structure 10 on a semiconductor substrate 14 having two copper pads 32, respectively, a first and a second copper contact pad 320 copper contact pad 322. 接着请参阅图8b所示,形成一聚合物层108在保护层34、第一铜接垫320及第二铜接垫322上,其中此聚合物层108具有絶缘功能,其材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide,PI)、苯基环丁烯(benzo-cyclo-butene, BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料,另外此聚合物层108主要是利用旋涂方式设置,然亦可利用热压合干膜或网版印刷方式进行。 Next, please refer to FIG. 8b, a polymer layer 108 is formed on the protective layer 34, a first copper pad 320 and the second copper contact pad 322, wherein the polymer layer 108 has an insulating function, such as a thermoplastic material which plastic, thermosetting plastic, polyimide (polyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy, parylene-based polymer, solder cover materials, elastomeric material, or porous dielectric material, this additional polymer layer 108 is mainly provided by spin coating, and then thermocompression bonding can take advantage of a dry film or screen printing manner.

[0133] 继续请参阅图8c所示,利用蚀刻方式对此聚合物层108进行图案化,以形成多数第一开口110与第二开口112而分别曝露出第一铜接垫320与第二铜接垫322,其中,当聚合物层108为感光材质时,则比如可以利用微影制造方法(photolithographyprocess),将聚合物层108图案化;当聚合物层108为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process),聚合物层108 图案化。 [0133] Please refer to FIG. 8c continued by this etching the polymer layer 108 is patterned to form a first copper contact pad 320 and the second copper majority of the first opening and the second opening 112 and 110 respectively exposing pad 322, wherein, when the polymer layer 108 is a photosensitive material, such as the lithography method can be used for producing (photolithographyprocess), the polymer layer 108 is patterned; polymer layer 108 when the non-photosensitive material, it can be for example etch process using lithography (photolithography process and etching process), the polymer layer 108 is patterned. 聚合物层108图案化之后,可利用烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度, 以硬化(curing)聚合物层108。 After the patterned polymer layer 108, may be utilized bake heating, microwave heating, infrared heating manner wherein one is heated to a temperature of 200 ° C or with heating between 320 degrees Celsius to between 450320 degrees Celsius and C temperature between degrees to harden (curing) polymer layer 108.

[0134] 再来请参阅图8d所示,利用溅镀、电镀或化学气相沉积的方式形成一第一金属层114在第一铜接垫320、第二铜接垫322及聚合物层108上(或包括部份保护层34上),此第一金属层114的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、钒、铬、铬铜合金、铜、钽及氮化钽其中之一或所组成的群组的至少其中之一,接着同样利用溅镀、电镀或化学气相沉积的方式形成一种子层116在第一金属层114上,此种子层116有利于后续金属层的设置, 因此种子层116的材质会随后续的金属层材质有所变化,例如当种子层116上是电镀形成金材质的金属层时,种子层116的材料是以金为佳;当要电镀形成银材质的金属层时,种子层116的材料是以银为佳;当种子层116上是电镀形成铜材质的金属层时,种子层116的材料是以铜为佳;当要电镀形成钯材质的金属层时,种子层116的材料 [0134] Referring to FIG. 8d again, by sputtering, electroplating or chemical vapor deposition is formed of a first metal layer 114 in the first copper pad 320, the second copper contact pad 322 and a polymer layer 108 ( or the protective layer includes an upper portion 34), a first material of this metal layer 114 is selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, chromium-copper alloy, copper, tantalum, and nitrogen wherein one of the at least one of tantalum or the group consisting of wherein, followed similarly by sputtering, electroplating or chemical vapor deposition a seed layer 116 is formed on the first metal layer 114, the seed layer 116 facilitates the subsequent a metal layer, the seed layer material 116 so as subsequent metal layer will vary material, for example, when the seed layer 116 is formed by plating a metal layer made of gold, the material of the seed layer 116 is preferably gold; when to plated metal layer is formed of silver material, the seed layer 116 material is preferably silver; and when a metal layer is formed by electroplating a copper layer 116 on the seed material, the seed material layer 116 is preferably copper; to be plated when forming a metal layer made of palladium, the material of the seed layer 116 以钯为佳;当要电镀形成钼材质的金属层时,种子层116的材料是以钼为佳;当要电镀形成铑材质的金属层时, 种子层116的材料是以铑为佳;当要电镀形成钌材质的金属层时,种子层116的材料是以钌 Preferably palladium; when plated metal layer is formed to be a molybdenum material, the material of the seed layer 116 is preferably molybdenum; when forming the metal layer to be plated rhodium material, the material of the seed layer 116 is preferably rhodium; when to a ruthenium metal layer is formed by plating a material, the material of the seed layer 116 is ruthenium

21为佳;当要电镀形成铼材质的金属层时,种子层116的材料是以铼为佳;当要电镀形成镍材质的金属层时,种子层116的材料是以镍为佳。 Preferably 21; to be plated when the metal layer is formed of rhenium material, the material of the seed layer 116 is preferably rhenium; when a nickel layer is to be formed by plating a metal material, the material of the seed layer 116 is preferably of nickel.

[0135] 再来,请参阅图8e所示,利用旋涂(spin-coating)的方式形成一光阻层118在种子层116上,此光阻层118的型式是为正光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0135] again, see FIG. 8E, a photoresist layer 118 is formed on the seed layer 116, this type photoresist layer 118 is a positive photoresist pattern by spin coating (spin-coating) manner, the material can be nonionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 继续请参阅图8f所示,图案化此光阻层118以形成开口120暴露出位于第一铜接垫320上、第二铜接垫322上以及第一铜接垫320与第二铜接垫322之间的种子层116,其中在形成开口120的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层118为感光材质时,则比如可以利用微影制造方法(photolithographyprocess),将光阻层118图案化而形成多数开口120,而当光阻层118为非感光材质时,则比如可以利用微影蚀刻制造卞法(photolithography process and etching process),^TfePlM 118 MM^WMM^ 数开口120。 Referring to FIG. 8f shown continued, this photoresist layer 118 is patterned to form an opening 120 exposing the copper pad located on the first 320, the second copper contact pad 322 and a first copper pad 320 and the second copper contact pad 116 between the seed layer 322, wherein during the formation of the opening 120 is doubled (IX) of the stepper (steppers) or a scanner (scanners) exposing and developing the photoresist layer 118 is then when the photosensitive material when, for example the method can be used for producing lithography (photolithographyprocess), the patterned photoresist layer 118 to form a plurality of openings 120, whereas when the photoresist layer 118 is non-photosensitive material, it can be utilized such as a lithography method for producing Bian ( photolithography process and etching process), ^ TfePlM 118 MM ^ WMM ^ number of openings 120.

[0136] 另,在形成光阻层118及其开口120上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层118,其中若是以网版印刷方式形成光阻层118则可直接在光阻层118内形成多数开口120而暴露出种子层116,然若是以热压合干膜方式形成光阻层118,则可在形成光阻层118之后,再形成多数开口120暴露出种子层116,但也可直接在光阻层118内形成多数开口120而暴露出种子层116。 [0136] Also, a photoresist layer is formed on the opening 118 and 120, the present invention also by screen printing or thermocompression bonding a dry film resist layer 118 is formed, if the screen printing which is formed a photoresist layer after 118 can be formed directly in the photoresist layer 118 a plurality of openings 120 expose the seed layer 116, and then thermocompression bonding if a dry film is formed in photoresist layer 118, photoresist layer 118 may be formed, then forming a plurality of openings 120 exposes the seed layer 116, but may also be a plurality of openings 120 expose the seed layer 116 is formed directly in the photoresist layer 118.

[0137] 接着请参阅图8g所示,以电镀或无电电镀的方式形成一第二金属122在开口120 所曝露出的种子层116上,此第二金属层122较佳的厚度是介于2微米至10微米之间,且此第二金属层122比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第二金属层122除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0137] Next, please refer to FIG. 8g, the electroplating or electroless plating a second metal 122 is formed on the opening 120 exposes the seed layer 116, the preferred thickness of this second metal layer 122 is interposed between 2 microns to 10 microns, and this second metal layer 122 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium single layer structure of metal or rhenium, or a composite layer composed of the metal material consisting of , but the second metal layer 122 in addition to the above-mentioned metal material may be substituted using the solder material, this material is a solder alloy layer is a tin-lead, tin-silver alloy layer, a tin-silver-copper alloy layer, a lead-free solder layer. 若此第二金属层122为焊料材质,则第二金属层122的较佳厚度是介于3微米至150微米之间。 If this second metal layer 122 is a solder material, the preferred thickness of the second metal layer 122 is between 3 microns to 150 microns.

[0138] 继续请参阅图8h所示,去除光阻层118以及未在第二金属层122下的种子层116 与第一金属层114,而在去除第一金属层114与种子层116的方式上,可分为干式蚀刻及湿式蚀刻,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层122下的种子层116与第一金属层114,而进行湿式蚀刻时若种子层116为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层114为钛钨合金时,则可使用双氧水进行去除。 [0138] Referring to FIG. 8h continued, the photoresist layer 118 is removed and the seed layer 116 not under the second metal layer 122 and the first metal layer 114, is removed in a first embodiment the seed layer 114 and the metal layer 116 on, can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etched to remove not attack the seed layer 116 under the second metal layer 122 and the first metal layer 114, wet etching is performed If the seed layer 116 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 114 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0139] 因此,如图8h所示,由所留下的第一金属层114、种子层116及第二金属层122形成的金属线路124连接第一铜接垫320及第二铜接垫322,使第一铜接垫320与第二铜接垫322电性连接。 [0139] Thus, as shown by the left first metal layer 114, seed layer 116 and the metal line 124 formed of the second metal layer 122 is connected to a first copper pads 8h 320 and the second copper pad 322 the first copper contact pad 320 and the second copper contact pad 322 is electrically connected.

[0140] 另,请参阅图8i,形成一聚合物层126在金属线路124及聚合物层108上, 其中此聚合物层126具有絶缘功能,其材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide, PI)、苯基环丁烯(benzo-cyclo-butene, BCB)、聚氨月旨(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料,另外此聚合物层126 主要是利用旋涂方式设置,然亦可利用热压合干膜或网版印刷方式进行。 [0140] Also, see Figure 8i, a polymer layer 126 is formed over the metal line 124 and a polymer layer 108, wherein the polymer layer 126 having an insulating function, the material such as a thermoplastic, thermoset, Juxi imine (polyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB), polyurethane month purpose (Polyurethane), epoxy, parylene-based polymer, solder-mask material, elastic material, or The porous dielectric material, this additional polymer layer 126 is mainly provided by spin coating, and then thermocompression bonding can take advantage of a dry film or screen printing manner.

[0141] 继续请参阅图8j所示,利用蚀刻方式对此聚合物层126进行图案化,以形成多数开口128曝露出金属线路124的第二金属层122,其中,当聚合物层126为感光材质时,则比如可以利用微影制造方法(photolithography process),将聚合物层126图案化;当聚合物层126为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process),将聚合物层126图案化。 [0141] Referring to FIG. 8j continued, the etching process using this patterned polymer layer 126, a second metal layer 122 to form a plurality of openings 128 exposing the metal trace 124, wherein, when the polymer is a photosensitive layer 126 when the material, such as the lithography method can be used for producing (photolithography process), the polymer layer 126 is patterned; when the polymer layer 126 is a non-photosensitive material, it can be used such as a method for producing a lithography (photolithography process and etching process ), the polymer layer 126 is patterned. 将聚合物层126图案化之后,可利用烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)聚合物层126。 After the patterning of the polymer layer 126, may be utilized bake heating, microwave heating, infrared heating manner wherein one is heated to a temperature of 200 ° C or with heating between 320 degrees Celsius to between 320 degrees Celsius and C a temperature between 450 degrees to harden (curing) polymer layer 126.

[0142] 最后请参阅图8k,进行切割半导体基底10形成多数半导体组件52,并且藉由打线制造方法形成打线导线130在所曝露出金属线路124的第二金属层122的顶面上,使半导体组件52电连接至外界电路,其中以第二金属层122为金层、钼层或钯层时,是为进行打线制造方法的较佳材质。 [0142] Referring to FIG. 8K Finally, dicing of the semiconductor substrate 10 forming a plurality of semiconductor elements 52, and bonding wires formed by wire bonding method for manufacturing a surface 130 in the second metal layer 124 exposing the metal lines 122, the semiconductor assembly 52 is electrically connected to the outside circuit, wherein the second metal layer 122 is a gold layer, a molybdenum layer, or when the palladium layer, a material is preferred to perform the method of manufacturing a wire.

[0143] 本实施例形成连接线路(interconnection)的方式亦可应用在第二实施例至第六实施例上,在此特以说明,惟并不再次详加叙述。 Embodiment [0143] of the present embodiment is formed connecting lines (Interconnection) may also be used in the second embodiment to the sixth embodiment to be described in this special, but not described in detail again.

[0144] 第八实施例 [0144] Eighth Example

[0145] 此实施例是以在半导体基底10上形成被动组件为说明标的,其中此被动组件例如是电感(线圈)组件、电阻组件、电容组件等,且此半导体基底10上具有铜接垫32。 [0145] This embodiment is a passive component is formed on the semiconductor substrate 10 is a target, wherein said passive components such as inductance (coil) assembly, resistive element, capacitors and other components, and on this semiconductor substrate 10 having a copper pad 32 . 请参阅图9a所示,利用旋涂(spin-coating)方式形成一聚合物层132在保护层34上,此聚合物层132具有絶缘功能,且此聚合物层132的材质是选自材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide,PI)、苯基环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料其中之一。 Referring to FIG. 9a, by spin coating (spin-coating) a polymer layer 132 is formed on the protective layer 34, the polymer layer 132 having an insulating function, and the polymer material layer 132 is a material selected from such as thermoplastics, thermosetting plastics, polyimide (polyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB), polyurethane (polyurethane), epoxy resin, polyethylene-based high paraxylene molecule, solder-mask material, elastic material, or wherein one of the porous dielectric material. 另外,此聚合物层132除了利用旋涂(spin-coating)方式也可以利用热压合干膜方式、网版印刷方式进行,此聚合物层132的厚度是介于2微米至50微米之间。 Further, in addition to the polymer layer 132 by spin coating (spin-coating) embodiment can also use a dry film thermocompression bonding manner, screen printing manner, the thickness of the polymer layer 132 is between 2 to 50 microns .

[0146] 接着将聚合物层132以烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)聚合物层132。 [0146] Next, the polymer layer 132 to bake heating, microwave heating, infrared heating manner wherein one or heated to a temperature between 200 ° C and heated 320 ° C to between 320 degrees Celsius and 450 degrees Celsius temperature between degrees to harden (curing) polymer layer 132.

[0147] 请参阅图9b所示,再来利用溅镀、电镀或化学气相沉积的方式形成一第一金属层134在聚合物层132上,此第一金属层134的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、 钒、铬、铬铜合金、铜、钽及氮化钽其中之一或所组成的群组的至少其中之一,接着同样利用溅镀、电镀或化学气相沉积的方式形成一种子层136在第一金属层134上,此种子层136有利于后续金属层的设置,因此种子层136的材质会随后续的金属层材质有所变化,例如当种子层136上是电镀形成金材质的金属层时,种子层136的材料是以金为佳;当要电镀形成银材质的金属层时,种子层136的材料是以银为佳;当种子层136上是电镀形成铜材质的金属层时,种子层136的材料是以铜为佳;当要电镀形成钯材质的金属层时,种子层136的材料是以钯为佳;当要电镀形成钼材质的金属层时,种子层136的 [0147] Please refer to FIG. 9b, again by sputtering, electroplating or chemical vapor deposition is formed in a first metal layer 134 on the polymer layer 132, the first metal layer 134 is a material selected from titanium, tungsten , at least one of cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, copper-chromium alloy, one of copper, tantalum and tantalum nitride or the group consisting of wherein, followed similarly by sputtering, plating or chemical vapor deposition of a seed layer 136 is formed on the first metal layer 134, the seed layer 136 disposed facilitate subsequent metal layer, a seed material layer 136 so as subsequent metal layer will vary material, for example, when is electroplated on the seed layer 136 is a metal layer made of gold, the material of the seed layer 136 is preferably gold; when the silver layer is to be formed by plating a metal material, the seed layer 136 material is preferably silver; and when the seed layer is formed on the metal layer 136 is electroplated copper material, the material of the seed layer 136 is preferably copper; when a palladium metal layer is formed to be plated material, material of the seed layer 136 is preferably palladium; when plated to form a molybdenum when the metal material layer, the seed layer 136 材料是以钼为佳;当要电镀形成铑材质的金属层时,种子层136的材料是以铑为佳;当要电镀形成钌材质的金属层时, 种子层136的材料是以钌为佳;当要电镀形成铼材质的金属层时,种子层136的材料是以铼为佳;当要电镀形成镍材质的金属层时,种子层136的材料是以镍为佳。 Material is preferably molybdenum; when forming the metal layer to be plated rhodium material, material of the seed layer 136 is preferably rhodium; when the ruthenium metal layer is formed to be plated material, the material of the seed layer 136 is preferably Ru ; when the rhenium metal layer is formed to be plated material, material of the seed layer 136 is preferably rhenium; when a nickel layer is to be formed by plating a metal material, the material of the seed layer 136 is preferably of nickel.

[0148] 继续请参阅图9c所示,利用旋涂(spin-coating)的方式形成一光阻层138在种子层136上,此光阻层138的型式是为正光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0148] Referring to FIG. 9c continued, a photoresist layer 138 is formed on the seed layer 136, this type photoresist layer 138 is a positive photoresist pattern by spin-coating mode (spin-coating), which may be made of nonionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 接着请参阅图9d所示,图案化此光阻层138以形成一线圈形状的开口140暴露出种子层136,其中在形成开口140的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层138为感光材质时,则比如可以利用微影制造方法(photolithography process),将光阻层138图案化而形成线圈形状的开口140,而当光阻层138为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithographyprocess and etching process),将光阻层138图案化而形成线圈形状的开口140。 Next opening 140 exposes the seed layer 9d shown in FIG. See, this photoresist layer 138 is patterned to form a shape of the coil 136, wherein the process is an opening 140 in the fold (IX) is formed stepper ( opening 140 steppers) or a scanner (scanners) exposing and developing the photoresist layer and then when the photosensitive material 138, such as the method can be manufactured by lithography (photolithography process), a photoresist layer 138 is patterned to form a coil shape, , when the photoresist layer 138 and a non-photosensitive material, it can be utilized such as a lithography method for producing (photolithographyprocess and etching process), a photoresist layer 138 is patterned to form a coil-shaped opening 140.

[0149] 另,在形成光阻层138及其线圈形状的开口140上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层138,其中若是以网版印刷方式形成光阻层138,则可直接在光阻层138内形成线圈形状的开口140而暴露出种子层136,然若是以热压合干膜方式形成光阻层138,则可在形成光阻层138之后,再形成线圈形状的开口140暴露出种子层136,但也可直接在光阻层138内形成线圈形状的开口140而暴露出种子层136。 [0149] Also, an opening is formed in the shape of a coil 138 and photoresist layer 140, the present invention also by screen printing or thermocompression bonding a dry film resist layer 138 is formed, in which if formed by screen printing photoresist layer 138, a coil shape may be formed directly in the opening of the photoresist layer 138 exposes the seed layer 140 and 136, then if the photoresist layer 138 is formed to a dry film thermocompression bonding embodiment, photoresist layer 138 may be formed Thereafter, an opening formed in a coil shape and then 140 exposes the seed layer 136, but the shape of the opening 140 of the coil to expose the seed layer 136 may be formed directly in the photoresist layer 138.

[0150] 接着请参阅图9e所示,以电镀或无电电镀的方式形成厚度大于1微米的一第二金属层142在开口140所曝露出的种子层136上,此第二金属层142较佳的厚度是介于2微米至30微米之间,且此第二金属层142比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第二金属层142除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0150] Next, please refer to Figure 9e, the electroplating or electroless plating is formed a second metal layer 142 of a thickness greater than 1 micrometer opening 140 exposing the seed layer 136, the second metal layer 142 more good thickness is between 2 to 30 microns, and this is the second metal layer 142 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium, rhenium or a single metal layer structure, or by the metal composite layer consisting of a material, but the second metal layer 142 in addition to the above-mentioned metal material may be substituted using the solder material, this material is a solder alloy layer is a tin-lead, tin-silver alloy layer, a tin-silver-copper alloy layer, no lead solder layer. 若此第二金属层142为焊料材质,则第二金属层142的较佳厚度是介于3微米至150 微米之间。 If this second metal layer 142 is a solder material, the preferred thickness of the second metal layer 142 is between 3 microns to 150 microns.

[0151] 请参阅图9f所示,最后去除光阻层138以及未在第二金属层142下的种子层136 与第一金属层134,而在去除第一金属层134与种子层136的方式上,可分为干式蚀刻及湿式蚀刻,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层142下的种子层136与第一金属层134,而进行湿式蚀刻时若种子层136为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层134为钛钨合金时,则可使用双氧水进行去除。 [0151] Referring to FIG. 9f, the photoresist layer 138 is removed, and finally the seed layer is not under the second metal layer 136 and 142 of the first metal layer 134, and removing the first embodiment in the metal layer 134 and the seed layer 136 on, it can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etching attack is not removed in a second metal layer 142 of the first seed layer 136 and the metal layer 134, wet etching is performed If the seed layer 136 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 134 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0152] 因此,所留下的第二金属层142、种子层136与第一金属层134即形成一呈线圈形状的金属线路144,如第9g图所示,此线圈形状的金属线路144可作被动组件中的电感,当此线圈形状的金属线路144通过电流时,即产生感应电动势,使保护层34下方的薄膜线路层18感应。 [0152] Thus, the remaining second metal layer 142, the first seed layer 136 and a metal layer 134 that is formed as a coil-shaped metal lines 144, as shown on FIG. 9g, the coil-shaped metal line 144 may be for passive inductive components, when the coil-shaped metal line 144 by the current, i.e., the induced electromotive force, so that the protective layer 18 below the sensing circuit layer 34 film. 另外,在此说明此线圈形状的金属线路144在使用时(通入电流),会产生大量的静电,大约为1500伏特(V),因为聚合物层132必须有一定程度的厚度,才能防止薄膜线路层18及薄膜绝缘层16损坏。 Further, described herein the metal lines 144 of the coil-shape when in use (current is applied), a large amount of static electricity, approximately 1500 volts (V), because the polymer layer 132 must have a certain degree of thickness in order to prevent the film a thin film circuit layer 18 and the insulating layer 16 is damaged.

[0153] 再来,如图9h所示,形成一聚合物层146在金属线路144及聚合物层132上, 其中此聚合物层146具有絶缘功能,其材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide, PI)、苯基环丁烯(benzo-cyclo-butene, BCB)、聚氨月旨(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料,另外此聚合物层146 主要是利用旋涂方式设置,然亦可利用热压合干膜或网版印刷方式进行。 [0153] again, as shown in FIG. 9h, a polymer layer 146 is formed over the metal line 144 and a polymer layer 132, wherein the polymer layer 146 having an insulating function, the material such as a thermoplastic, thermosetting plastic, polyethylene (PEI) (polyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB), polyurethane month purpose (Polyurethane), epoxy, parylene-based polymer, solder-mask material, elastic material, or a porous dielectric material, further the polymer layer 146 is mainly provided by spin coating, and then thermocompression bonding can take advantage of a dry film or screen printing manner.

[0154] 继续请参阅图9i所示,利用蚀刻方式对此聚合物层146进行图案化,以形成多数开口148曝露出金属线路144的第二金属层142,其中,当聚合物层146为感光材质时,则比如可以利用微影制造方法(photolithography process),将聚合物层146图案化;当聚合物层146为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process),将聚合物层146图案化。 [0154] Referring to FIG. 9i continued, the etching process using this patterned polymer layer 146, a second metal layer 142 to form a plurality of openings 148 exposing the metal trace 144, wherein, when the polymer is a photosensitive layer 146 when the material, such as the lithography method can be used for producing (photolithography process), the polymer layer 146 is patterned; when the polymer is non-photosensitive material layer 146, may be utilized such as the method for producing a lithography (photolithography process and etching process ), the polymer layer 146 is patterned. 将聚合物层146图案化之后,可利用烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)聚合物层146。 After the patterning of the polymer layer 146, may be utilized bake heating, microwave heating, infrared heating manner wherein one is heated to a temperature of 200 ° C or with heating between 320 degrees Celsius to between 320 degrees Celsius and C a temperature between 450 degrees to harden (curing) polymer layer 146. [0155] 最后请参阅图9j,进行切割半导体基底10形成多数半导体组件52,并且藉由打线制造方法形成打线导线150在所曝露出金属线路144的第二金属层142的顶面上,使半导体组件52电连接至外界电路,其中以第二金属层142为金层、钼层或钯层时,是为进行打线制造方法的较佳材质。 [0155] Referring to FIG. 9j Finally, dicing of the semiconductor substrate 10 forming a plurality of semiconductor elements 52, and bonding wires formed by wire bonding method for manufacturing a surface 150 in a second metal layer 144 exposing the metal lines 142, the semiconductor assembly 52 is electrically connected to the outside circuit, wherein the second metal layer 142 is a gold layer, a molybdenum layer, or when the palladium layer, a material is preferred to perform the method of manufacturing a wire.

[0156] 惟本实施例形成线圈状的金属线路的方式亦可应用在第二实施例至第六实施例上,在此特以说明,惟并不再次详加叙述。 Metal lines embodiment [0156] However the present embodiment is formed in a coil shape can also be applied in the second embodiment to the sixth embodiment to be described in this special, but not described in detail again.

[0157] 第九实施例 [0157] Ninth Example

[0158] 此实施例是为第一实施例在重配置线路(RDL)上的应用,然为使结构简而易懂, 仅绘示出一铜接垫利用一金属线路连接至一对外接垫的示意图,并以此做下列说明。 [0158] This embodiment is an application example for the reconfiguration in the line (RDL) in a first embodiment, and then to make the structure simple and easy to understand, only a schematic illustrating the use of a copper pad metal line is connected to a pair of external pads schematic, and use it to do the following instructions.

[0159] 请参阅图IOa所示,在形成保护层34后,接着形成厚度介于3微米至50微米之间的一聚合物层152在此保护层34及铜接垫32上,此聚合物层152具有絶缘功能,且此聚合物层152的材质是选自材质比如为热塑性塑料、热固性塑料、聚醯亚胺(p0lyimide,PI)、苯基环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料,此外此聚合物层152主要是利用旋涂方式设置,另也可利用热压合干膜或网版印刷方式进行。 [0159] Referring to FIG IOa shown, after forming the protective layer 34 is then formed on this thickness of between 152 and copper layer 34, the protective pad 32, the polymer a polymer layer between 3 to 50 microns layer 152 having an insulating function, and the material of the polymer layer 152 is selected from a material such as a thermoplastic, thermosetting plastic, polyimide (p0lyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB ), polyurethane (polyurethane), epoxy, parylene-based polymer, solder-mask material, elastic material, or porous dielectric materials, in addition to the polymer layer 152 is mainly provided by spin coating, but also other thermocompression bonding may utilize a dry film or screen printing manner.

[0160] 接着如图IOb所示,利用蚀刻方式对此聚合物层152进行图案化,以形成多数开口154曝露出铜接垫32。 [0160] Next, as shown in FIG. IOb by this etching the polymer layer 152 is patterned to form a plurality of openings 154 expose the copper pad 32. 其中值得注意的是,当聚合物层152是为感光材质时,则比如可以利用微影制造方法(photolithography process),将聚合物层152图案化;当聚合物层152 是为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process),将聚合物层152图案化。 It is worth noting that when the polymer layer 152 is a photosensitive material, then such a method can be used for producing lithography (photolithography process), the polymer layer 152 is patterned; if the polymer layer 152 is a non-photosensitive material, the For example it may be utilized a method for producing a lithography (photolithography process and etching process), the polymer layer 152 is patterned. 将聚合物层152图案化之后,可利用烘烤加热、 微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)聚合物层152。 After the patterned polymer layer 152, may be utilized bake heating, microwave heating, infrared heating manner wherein one is heated to a temperature of 200 ° C or with heating between 320 degrees Celsius to between 320 degrees Celsius and C a temperature between 450 degrees to harden (curing) polymer layer 152.

[0161] 继续请参阅图IOc所示,利用溅镀、电镀或化学气相沉积的方式形成一第一金属层156在聚合物层152上,此第一金属层156的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、钒、铬、铬铜合金、铜、钽及氮化钽其中之一或所组成的群组的至少其中之一,接着同样利用溅镀、电镀或化学气相沉积的方式形成一种子层158在第一金属层156上,此种子层158有利于后续金属层的设置,因此种子层158的材质会随后续的金属层材质有所变化,例如当种子层158上是电镀形成金材质的金属层时,种子层158的材料是以金为佳;当要电镀形成银材质的金属层时,种子层158的材料是以银为佳;当种子层158上是电镀形成铜材质的金属层时,种子层158的材料是以铜为佳;当要电镀形成钯材质的金属层时,种子层158 的材料是以钯为佳;当要电镀形成钼材质的金属层时,种子层158 [0161] Please continue to refer to Figure IOc of, by sputtering, electroplating or chemical vapor deposition is formed of a first embodiment metal layer 156 on the polymer layer 152, the first metal layer 156 is a material selected from titanium, tungsten , at least one of cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, copper-chromium alloy, one of copper, tantalum and tantalum nitride or the group consisting of wherein, followed similarly by sputtering, plating or chemical vapor deposition of a seed layer 158 is formed on the first metal layer 156, the seed layer 158 disposed facilitate subsequent metal layer, a seed material layer 158 so as subsequent metal layer will vary material, for example, when is electroplated on the seed layer 158 is formed when the metal layer made of gold, the material of the seed layer 158 is preferably gold; when the silver layer is to be formed by plating a metal material, the seed layer 158 material is preferably silver; and when the seed layer 158 is a copper material plated metal layer is formed, the material of the seed layer 158 is preferably copper; when a palladium metal layer is formed to be plated material, the material of the seed layer 158 is preferably palladium; when plated to form a molybdenum when the metal material layer, the seed layer 158 材料是以钼为佳;当要电镀形成铑材质的金属层时,种子层158的材料是以铑为佳;当要电镀形成钌材质的金属层时,种子层158的材料是以钉为佳;当要电镀形成铼材质的金属层时,种子层158的材料是以铼为佳;当要电镀形成镍材质的金属层时,种子层158的材料是以镍为佳。 Material is preferably molybdenum; when forming the metal layer to be plated rhodium material, material of the seed layer 158 is preferably rhodium; when the ruthenium metal layer is formed to be plated material, the seed layer material is preferably a staple 158 ; when the rhenium metal layer is formed to be plated material, the material of the seed layer 158 is preferably rhenium; when a nickel layer is to be formed by plating a metal material, the material of the seed layer 158 is preferably of nickel.

[0162] 继续请参阅图IOd所示,利用旋涂(spin-coating)的方式形成一光阻层160在种子层158上,此光阻层160的型式是为正光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0162] Please continue to refer to FIG IOd, by spin coating (spin-coating) of a photoresist layer 160 is formed on the seed layer 158, this type of photoresist layer 160 is a positive photoresist pattern, which may be made of nonionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 接着请参阅图IOe所示,图案化此光阻层160以形成开口162暴露出位于铜接垫32上的种子层158以及位于铜接垫32旁的部份聚合物层152上的种子层158,其中在形成开口162的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层160为感光材质时,则比如可以利用微影制造方法(photolithography process),将光阻层160图案化而形成开口162,而当光阻层160为非感光材质时,则比如可以利用微影蚀刻制造方夕去(photolithography process and etching process),^fjfePlM 160 j^Jf Π See Subsequently, the pattern of FIG. IOe this photoresist layer 162 is exposed to form an opening 160 located on the copper pads 32 of the seed layer 158 and the copper seed layer 158 positioned on the pad portion 152 next to the polymer layer 32 process in which the opening 162 is formed in a fold (IX) of the stepper (steppers) or a scanner (scanners) exposing and developing the photoresist layer 160 and then when the photosensitive material, it can be utilized such as a micro Movies production method (photolithography process), a photoresist layer 160 is patterned to form an opening 162, when the photoresist layer 160 and a non-photosensitive material, it can be utilized such as photolithography for producing evening to (photolithography process and etching process) , ^ fjfePlM 160 j ^ Jf Π

162。 162.

[0163] 另,在形成光阻层160及其开口162上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层160,其中若是以网版印刷方式形成光阻层160,则可直接在光阻层160内形成开口162而暴露出种子层158,然若是以热压合干膜方式形成光阻层160,则可在形成光阻层160之后,再形成开口162暴露出种子层158,但也可直接在光阻层160内形成开口162而暴露出种子层158。 [0163] Also, photoresist layer 160 is formed on its opening 162, photoresist layer 160 is formed according to the present invention may also by screen printing or dry film thermocompression bonding manner, wherein if the screen printing is formed a photoresist layer 160, an opening 162 to expose the seed layer 158, a photoresist layer is formed and then if after thermocompression bonding at a dry film embodiment 160, photoresist layer 160 may be formed, and then can be directly formed within a photoresist layer 160 is formed in the opening 162 exposing the seed layer 158, but may be an opening 162 to expose the seed layer 158 is formed directly in the photoresist layer 160.

[0164] 再来请参阅图IOf所示,以电镀或无电电镀的方式形成厚度大于1微米的一第二金属层164在开口162所曝露出的种子层158上,此第二金属层164较佳的厚度是介于2 微米至30微米之间,且此第二金属层164比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层,惟第二金属层164除了上述所提的金属材质外也可使用焊料材料取代,此焊料材料是为锡铅合金层、锡银合金层、锡银铜合金层、无铅焊料层。 [0164] Referring to FIG IOf again shown to electroplating or electroless plating metal layer is formed a second thickness greater than 1 micron in the opening 164 exposes the seed layer 162 158, this second metal layer 164 more good thickness is between 2 to 30 microns, and this second metal layer 164 such as gold, copper, silver, palladium, molybdenum, rhodium, ruthenium, rhenium or a single metal layer structure, or by the metal composite layer consisting of a material, but the second metal layer 164 in addition to the above-mentioned metal material may be substituted using the solder material, this material is a solder alloy layer is a tin-lead, tin-silver alloy layer, a tin-silver-copper alloy layer, no lead solder layer. 若此第二金属层164为焊料材质,则第二金属层164的较佳厚度是介于3微米至150微米之间。 If this second metal layer 164 is a solder material, the preferred thickness of the second metal layer 164 is between 3 microns to 150 microns.

[0165] 请参阅图IOg所示,最后去除光阻层160以及未在第二金属层164下的种子层158 与第一金属层156,而在去除第一金属层156与种子层158的方式上,可分为干式蚀刻及湿式蚀刻,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在第二金属层164下的种子层158与第一金属层156,而进行湿式蚀刻时若种子层158为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层156为钛钨合金时,则可使用双氧水进行去除。 [0165] Referring to FIG IoG, and finally removing the photoresist layer 160 and the seed layer not under the second metal layer 164, first metal layer 158 and 156, and 158 in a manner to remove the first metal layer 156 and the seed layer on, can be divided into dry or wet etching, wherein the dry etching is performed using high pressure argon sputter etched to remove not attack the seed layer 164 under the second metal layer 158 and first metal layer 156, wet etching is performed If the seed layer 158 is a seed layer of gold may be removed using potassium iodide solution, if the first metal layer 156 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide.

[0166] 因此,由所留下的第二金属层164、种子层158与第一金属层156则形成一金属线路166,亦即一重配置线路层,值得注意的特点在于此实施例主要是将金属线路166形成在开口154上及延伸至部分的聚合物层152上,并不是单纯形在开口154上,而所延伸的金属线路166则有利于后续的线路的设置。 [0166] Thus, the second metal layer 164 left, the seed layer 158 and the first metal layer 156 is formed a metal line 166, i.e., a RDL, noteworthy feature in this embodiment is mainly the metal line 166 formed in the opening 154 and the polymer layer extends onto portion 152, not simply on the opening 154 formed, the metal line 166 extends is provided in favor of the subsequent line.

[0167] 再来,请参阅图IOh所示,形成一聚合物层168在金属线路166及聚合物层152 上,其中此聚合物层168具有絶缘功能,其材质比如为热塑性塑料、热固性塑料、聚醯亚胺(polyimide, PI)、苯基环丁烯(benzo-cyclo-butene, BCB)、聚氨月旨(polyurethane)、环氧树脂、聚对二甲苯类高分子、焊罩材料、弹性材料或多孔性介电材料,另外此聚合物层168 主要是利用旋涂方式设置,然亦可利用热压合干膜或网版印刷方式进行。 [0167] again, see Figure IOH, a polymer layer 168 is formed over the metal line 166 and a polymer layer 152, wherein the polymer layer 168 having an insulating function, the material such as a thermoplastic, thermosetting plastic, polyimide (polyimide, PI), phenyl cyclobutene (benzo-cyclo-butene, BCB), polyurethane month purpose (Polyurethane), epoxy, parylene-based polymer, solder-mask material, elastic a porous material or a dielectric material, further the polymer layer 168 is mainly provided by spin coating, and then thermocompression bonding can take advantage of a dry film or screen printing manner.

[0168] 继续请参阅图IOi所示,利用蚀刻方式对此聚合物层168进行图案化,以形成多数开口170曝露出金属线路166的第二金属层164,其中当聚合物层168为感光材质时,则比如可以利用微影制造方法(photolithography process),将聚合物层168图案化;当聚合物层168为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process),将聚合物层168图案化。 [0168] Referring to FIG IOi continued, the etching process using this patterned polymer layer 168, a second metal layer 164 to form a plurality of openings 170 exposing the metal trace 166, wherein when the polymer is a photosensitive material layer 168 when, for example the method can be used for producing lithography (photolithography process), the polymer layer 168 is patterned; when the polymer is non-photosensitive material layer 168, the etch process such as lithography (photolithography process and etching process) may be utilized , the polymer layer 168 is patterned. 将聚合物层168图案化之后,可利用烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)聚合物层168。 After the patterning of the polymer layer 168, may be utilized bake heating, microwave heating, infrared heating manner wherein one is heated to a temperature of 200 ° C or with heating between 320 degrees Celsius to between 320 degrees Celsius and C a temperature between 450 degrees to harden (curing) polymer layer 168. 此外,由开口170所曝露出的金属线路166的第二金属层164顶面即作为一对外接垫,此对外接垫透过金属线路166连接至铜接垫32,另从俯视透视图观之,此对外接垫的位置是不同于铜接垫32的位置。 Further, the surface of the second metal layer 164 by the opening 170 exposing the metal line 166, i.e., the external pads as a pair, the pair of the external pads through the metal line 166 is connected to the copper pad 32, and the other from a top perspective View of this position is different from the position of the external pads 32 of the copper pads.

[0169] 请参阅图10j,最后进行切割半导体基底10形成多数半导体组件52,并且藉由打线制造方法形成打线导线172在对外接垫上,使半导体组件52电连接至外界电路,其中以第二金属层164为金层、钼层或钯层时,是为进行打线制造方法的较佳材质。 [0169] Referring to FIG 10J, and finally most of the semiconductor device 52 is formed by dicing the semiconductor substrate 10, and a method of manufacturing a wire formed by bonding wires 172 to an external pad of the semiconductor component 52 is electrically connected to the outside circuit, wherein the first a second metal layer 164 is a gold layer, a molybdenum layer, or when the palladium layer, a material is preferred to perform the method of manufacturing a wire.

[0170] 惟本实施例形成重配置线路(RDL)的方式亦可应用在第二实施例至第六实施例上,在此特以说明,惟并不再次详加叙述。 Embodiment [0170] However the present embodiment is formed reconfiguration line (RDL) it can also be used in the second embodiment to the sixth embodiment to be described in this special, but not described in detail again.

[0171] 第十实施例 [0171] Tenth Example

[0172] 此实施例与第九实施例相似,不同点在于对外接垫是用来连接高度大于8微米之一金凸块。 [0172] Example of the ninth embodiment of this embodiment is similar, except that the external pads of a height greater than one is used to connect the gold bumps 8 microns. 请参阅图Ila所示,在完成图IOi所示的结构后,接着利用溅镀、电镀或化学气相沉积的方式形成一第一金属层174在聚合物层168及作为对外接垫的第二金属层164顶面上,此第一金属层174的材质是选自钛、钨、钴、镍、氮化钛、钛钨合金、钒、铬、铬铜合金、铜、 钽及氮化钽其中之一或所组成的群组的至少其中之一,接着同样利用溅镀、电镀或化学气相沉积的方式形成一种子层176在第一金属层174上,此种子层176有利于后续金属层的设置,因此种子层176的材质会随后续的金属层材质有所变化,例如当种子层176上是电镀形成金材质的金属层时,种子层176的材料是以金为佳;当要电镀形成银材质的金属层时, 种子层176的材料是以银为佳;当种子层176上是电镀形成铜材质的金属层时,种子层176 的材料是以铜为佳;当要电镀形成钯材质的金属层时,种子层176的材 See FIG Ila, after completion of the structure shown in FIG IOi, followed by sputtering, electroplating or chemical vapor deposition is formed of a first embodiment metal layer 174 and the polymer layer 168 as a second metal pad on the external surface layer 164, a first material of this metal layer 174 is selected from titanium, tungsten, cobalt, nickel, titanium nitride, titanium tungsten, vanadium, chromium, chromium-copper alloy, copper, tantalum and tantalum nitride in which the wherein at least one of a group consisting of or followed the same by sputtering, electroplating or chemical vapor deposition a seed layer 176 is formed on the first metal layer 174, the seed layer 176 disposed facilitate subsequent metal layer , the seed layer material will thus continue the subsequent metal layer of material 176 vary, for example, a gold plating layer is formed of metal material, the material of the seed layer 176 is preferably as gold on the seed layer 176; when forming a silver plating to when the material of the metal layer, the material of the seed layer 176 is preferably silver; when the seed layer 176 is formed by plating a metal layer made of copper, the material of the seed layer 176 is preferably copper; when the material to be formed by plating palladium when the metal layer, the seed layer material 176 是以钯为佳;当要电镀形成钼材质的金属层时,种子层176的材料是以钼为佳;当要电镀形成铑材质的金属层时,种子层176的材料是以铑为佳;当要电镀形成钌材质的金属层时,种子层176的材料是以钌为佳;当要电镀形成铼材质的金属层时,种子层176的材料是以铼为佳;当要电镀形成镍材质的金属层时,种子层176的材料是以镍为佳。 Is preferably palladium; when plated metal layer is formed to be a molybdenum material, the material of the seed layer 176 is preferably molybdenum; when forming the metal layer to be plated rhodium material, the material of the seed layer 176 is preferably rhodium; when the plated metal layer is formed to be a ruthenium material, the material of the seed layer 176 is preferably Ru; when the rhenium metal layer is formed to be plated material, the material of the seed layer 176 is preferably rhenium; when the material to form a nickel plated when the metal layer, the seed layer material 176 is preferably of nickel.

[0173] 再来,请参阅图lib所示,利用旋涂(spin-coating)的方式形成一光阻层178在种子层176上,此光阻层178的型式是为正光阻型式,其材质可为非离子性(nonionic)或酯类(ester-type)的感旋光性材料,或者是非感旋光性材料。 [0173] again, see FIG. Lib shown, a photoresist layer 178 is formed on the seed layer 176, this type photoresist layer 178 is a positive photoresist pattern, which material may be spin coating (spin-coating) manner nonionic (nonionic) or esters (ester-type) of the photosensitive material, or a non-photosensitive material. 继续请参阅图Ilc所示,图案化此光阻层178以形成开口180暴露出位于对外接垫上的种子层176,其中在形成开口180的过程中是以1倍(IX)的步进曝光机(steppers)或扫描机(scanners)进行曝光显影,接着当光阻层178为感光材质时,则比如可以利用微影制造方法(photolithography process),将光阻层178图案化,而当光阻层178为非感光材质时,则比如可以利用微影蚀刻制造方法(photolithography process and etching process),将光阻层178 图案化。 Please continue to refer to FIG Ilc, this patterned photoresist layer 178 to form opening 180 exposes the seed layer 176 positioned on an external pad, which is 1-fold (IX) in the process of the stepper opening 180 is formed in the (steppers) or a scanner (scanners) exposing and developing the photoresist layer 178 and then when the photosensitive material, it can be used such as a method for producing lithography (photolithography process), the patterned photoresist layer 178, whereas when the photoresist layer when a non-photosensitive material 178, such as may utilize the method for producing a lithography (photolithography process and etching process), a photoresist layer 178 is patterned.

[0174] 另,在形成光阻层178及其开口180上,本发明亦可利用网版印刷或热压合干膜的方式形成光阻层178,其中若是以网版印刷方式形成光阻层178则可直接在光阻层178内形成开口180而暴露出种子层176,然若是以热压合干膜方式形成光阻层178,则可在形成光阻层178之后,再形成开口180暴露出种子层176,但也可直接在光阻层178内形成开口180而暴露出种子层176。 [0174] Also, a photoresist layer is formed on the opening 180 and 178, the present invention is a photoresist layer 178 may be formed by screen printing or dry film thermocompression bonding manner, wherein if the screen printing is formed a photoresist layer 178 can be directly formed in the photoresist layer 178 within the opening 180 to expose the seed layer 176, a photoresist layer is formed and then if after thermocompression bonding at a dry film embodiment 178 may be formed in the photoresist layer 178, an opening 180 is formed and then exposed the seed layer 176, but may be an opening 180 to expose the seed layer 176 is formed directly in the photoresist layer 178.

[0175] 接着请参阅图Ild所示,以电镀的方式形成高度大于8微米之一金属凸块182在开口180所曝露出的种子层176上,此金属凸块182比如是金、铜、银、钯、钼、铑、钌或铼的单层金属层结构,或是由上述金属材质所组成的复合层。 [0175] Next, please refer to FIG Ild shown, are formed by electroplating one of a height greater than 8 microns metal bump 182 on the opening 180 exposes the seed layer 176, the metal bumps 182, such as gold, copper, silver, , palladium, molybdenum, rhodium, ruthenium single layer structure of metal or rhenium, or a composite layer composed of the metal material thereof.

[0176] 最后,如图lie所示,去除光阻层178以及未在金属凸块182下的种子层176与第一金属层174,而在去除第一金属层174与种子层176的方式上,可分为干式蚀刻及湿式蚀亥IJ,其中干式蚀刻是使用高压氩气进行溅击蚀刻而去除未在金属凸块182下的种子层176 与第一金属层174,而进行湿式蚀刻时若种子层176为金的种子层时,则可使用碘化钾溶液进行去除,若第一金属层174为钛钨合金时,则可使用双氧水进行去除。 [0176] Finally, as shown in FIG. Lie, photoresist layer 178 is removed and a metal bump layer 176 and the seed layer 182 under the first metal is not 174, but is removed in a first embodiment the metal layer 174 and the seed layer 176 It can be divided into wet etching and dry etching Hai IJ, wherein the dry etching is performed using high pressure argon sputtering attack the seed layer not removed by etching the first metal layer 176 and the metal bump 174 at 182, and wet etching If the seed layer 176 is a seed layer of gold may be used when removing the potassium iodide solution, if the first metal layer 174 is titanium tungsten alloy, may be used for the removal of hydrogen peroxide. 另,金属凸块182可利用打线接合、贴带自动接合、薄膜复晶接合或玻璃复晶接合等技术接合在一外界基板上。 Also, the metal bumps 182 may use wire bonding, tape automated bonding paste, bonded polycrystalline thin film polycrystalline or glass bonding or the like bonded on an outside art substrate. 因此,铜接垫32可透过金属线路166连接对外接垫,并利用对外接电连接高度大于8微米的金属凸块,进而电性连接外界基板。 Therefore, the copper pad 32 through a metal line 166 may be connected to the external pads, and electrically connected to the external use of a height greater than 8 microns metal bump, thereby electrically connecting the external substrate.

[0177] 此外,若图lie所示的结构是以电镀的方式形成高度大于10微米之一含锡凸块184在对外接垫上,并在经过回焊(re-flow)之后,含锡凸块184呈如图Ilf所示的形状而与对外接垫连接。 [0177] Further, if the configuration shown in FIG. Lie plating is formed it is one of a height greater than 10 m in a tin-containing bumps 184 to the external pad, and after reflow (re-flow), tin bumps 184 in the shape shown in FIG Ilf with the external connection pad.

[0178] 第十一实施例 [0178] Example XI

[0179] 请参阅图12b至图12i所示,其是形成图12a的结构所经过的每一步骤中相对应的结构剖面示视图。 [0179] See FIG. 12b to 12i, which are formed in each step of the structure of FIG 12a through which a structure corresponding to a cross-sectional view illustrating.

[0180] 首先,请参阅图12b所示,提供一半导体基底10,此半导体基底10上包括有多个电路组件12,如:晶体管、内存以及/或是逻辑组件、多个薄膜绝缘层16与多个薄膜线路缘层18,此些薄膜线路层18可以透过薄膜绝缘层16内的多个导通孔24连通相邻两层之间的薄膜线路层18或者是连接至相对应的电子组件12上。 [0180] First, referring to FIG. 12b, a semiconductor substrate 10, the semiconductor substrate comprises a plurality of circuit assembly 1012, such as: a transistor, memory, and / or logical components, a plurality of thin-film insulation layer 16 a plurality of thin film wiring layers 18 edge, the thin film of such a thin film circuit layer 18 may be between the two layers of wiring layer 18 is connected to the electronic components or the corresponding adjacent communication through a plurality of vias in the thin-film insulating layer 1624 12. 另外,多个铜接垫324、326、328形成在半导体基底10的顶部表面上,而此些铜接垫324、326、328是为半导体基底10上的薄膜线路层18顶部表面的一部份,可分别与底层的集成电路电性连接,且同样地此些铜接垫324、326、328的下表面及侧壁均包覆有阻障层26及种子层28。 Further, a plurality of copper pads 324, 326 are formed on the top surface of the semiconductor substrate 10, and copper pads 324, 326 of such a part of the top surface 18 of the thin film semiconductor circuit layer 10 on the substrate , may be electrically connected to the integrated circuit underlying the same manner and of such a copper surface and the sidewall of the lower pads 324, 326 are coated with a barrier layer 26 and the seed layer 28.

[0181] 一保护层34是覆盖在半导体基底10上的无机保护层20的顶部表面,并且铜接垫324、326、328是分别藉由保护层34上的开口340、342、344以部分地暴露在外。 [0181] 34 is covered with a protective layer on the top surface of the inorganic protective layer on the semiconductor substrate 1020, and the copper pads 324, 326, respectively, by an opening 34 in the protective layer 340,342, 344 to partially exposed. 一般而言, 开口340、342、344的最大横向尺寸约介于0. 5至15微米之间,而在其它的实施态样中,开口340、342、344的最大横向尺寸亦可介于15至300微米之间。 In general, the maximum transverse dimension of the openings 340,342, 344 between about 0.5 to 15 microns, and in other aspects of the embodiment, the openings 340,342, 344 may also be the maximum transverse dimension of between 15 to between 300 microns.

[0182] 形成一第一金属层186覆盖在保护层34顶部表面以及开口340、342、344所暴露出的铜接垫324、326、328上,另外此第一金属层186的轮廓是与保护层34的顶部表面及开口340、342、344的轮廓相符合,并且更将上述的多个开口340、342、344密封。 [0182] forming a first metal layer 186 covers the top surface of the protective layer 34 and exposed by the openings 340,342, 344 copper contact pad 324, 326, this additional contour of the first metal layer 186 is protected the top surface layer 34 and the opening contour conform 340,342, 344, and the above-mentioned plurality of openings more seals 340,342, 344. 其中,第一金属层186的较佳厚度是介于0. 1至10微米之间。 Wherein the preferred thickness of the first metal layer 186 is between 0.1 to 10 microns.

[0183] 根据本实施例,可用于第一金属层186的材料包括:钛、钨、钴、镍、氮化钛、氮化钨、钒、铬、铜、铬铜、钽、氮化钽、上述材料所形成的合金,或是上述材料组合而成的复合层。 [0183] According to the present embodiment, the material for the first metal layer 186 include: titanium, tungsten, cobalt, nickel, titanium nitride, tungsten nitride, vanadium, chromium, copper, chromium, copper, tantalum, tantalum nitride, an alloy material formed of the above, or a composite layer of the above materials are combined. 随后,一种子层(seed layer) 188是可选择性地形成在此第一金属层186上方。 Subsequently, a seed layer (seed layer) 188 is selectively formed over the first metal layer 186 here.

[0184] 接续,请参考图12c所示,一图案化光阻层190是形成在种子层188上,且此图案化光阻层190是可藉由一般微影成像(lithography)的制造方法方式形成,一般而言,微影成像制造方法是包括有以下步骤:光阻涂布、光阻烘烤、曝光以及显影,其中,上述的光阻是可为一干燥的薄膜。 [0184] connection, as shown in reference to FIG. 12c, a patterned photoresist layer 190 is formed on the seed layer 188, and this is patterned photoresist layer 190 may be manufactured by the general method described lithography imaging (Lithography) of It is formed, in general, a method for producing a lithography imaging comprising the steps of: applying the resist, baking the resist, exposure and development, wherein the resist is a dry film may be. 此图案化光阻层190具有多个开口192a、192b、192c,此外开口192a 是直接形成在铜接垫324的上方,开口192b是直接形成在铜接垫326的上方,其是用以定义出形成重配置线路(RDL)所需的沟渠位置,而开口192c则是直接形成在铜接垫328的上方。 This patterned photoresist layer 190 having a plurality of openings 192a, 192b, 192c, furthermore the opening 192a is formed directly on top of the copper pad 324, the opening 192b is formed directly above the copper pad 326, which is used to define position to form the desired trench reconfiguration line (RDL), and the opening 192c is formed directly above the copper pad 328.

[0185] 再来,请参阅图12d,以电镀的制造方法在开口192a、192b、192c上分别形成第二金属层194a、194b、194c,例如电镀形成一铜层,且此第二金属层194a、194b、194c的厚度是介于0. 1至10微米之间,而在其它的实施态样中,上述的第二金属层194a、194b、194c的厚度可介于10至250微米之间。 [0185] again, see FIG. 12 d, to the method of manufacturing electroplating in the opening 192a, 192b, 192c are formed on the second metal layer 194a, 194b, 194c, for example, a copper plating layer is formed, and this second metal layer 194a, 194b, 194c of the thickness is between 0.1 to 10 microns, and in other aspects of the embodiment, the above-mentioned second metal layer 194a, 194b, 194c thickness may be between 10 to 250 microns. 随后,再进行一次电镀制造方法以在第二金属层194a、 194b、194c上分别形成第三金属层196a、196b、196c,例如电镀形成一镍层,而此第三金属层196a、196b、196c是可避免其下方的第二金属层194a、194b、194c的表面发生氧化的情形,同时,亦可提供一强而有力的阻绝功能。 Subsequently, a plating method then produced in the second metal layer 194a, 194b, 194c are formed respectively on the third metal layer 196a, 196b, 196c, such as electroplating a nickel layer is formed, and this third metal layer 196a, 196b, 196c It can be avoided 194a, 194b, 194c of the case where the surface oxidation of the second metal layer beneath it, while also providing a strong block the function. 进行至此,上述图案化光阻层190可将其进行去除。 Thus for the patterned photoresist layer 190 may be removal.

[0186] 继续请参阅图12e所示,形成另一图案化光阻层198在种子层188以及第三金属层196a、196b、196c上,且在铜接垫324的上方,此图案化光阻层198形成有一开口200a,然而,位于此图案化的光阻层198内的开口200b并未直接对准于铜接垫326的上方,其中,藉由开口200a是可让第三金属层196a的顶部表面进行曝光制造方法,而开口200b则是可在第三金属层196b上的预选择重配置区域中进行曝光制造方法。 [0186] Referring to FIG continue 12e shown forming another photoresist layer 198 patterned on the seed layer 188 and the third metal layer 196a, 196b, 196c, and over the copper contact pad 324, the patterned photoresist layer 198 is formed with an opening 200a, however, is not directly aligned with the opening 200b above the copper pad 326 is located within 198 of this patterned photoresist layer, wherein, by opening 200a is that it allows the third metal layer 196a the method for manufacturing the top surface is exposed, and the opening may be pre-200b is selected on the third metal layer 196b is exposed in the area reconfiguration manufacturing method. 接着请参阅图12f,无电电镀第四金属层202a、202b分别形成在开口200a、200b中,此第四金属层202a、202b比如是金、银、钯、钼、铑、钌、铼的材质,然而此无电镀第四金属层202a、202b的形成是为可选择性的。 Referring to FIG. 12f Next, electroless plating a fourth metal layers 202a, 202b, respectively, in the openings 200a, 200b in this fourth metal layer 202a, 202b such as gold, silver, palladium, molybdenum, rhodium, ruthenium, rhenium forming material However, this form fourth metal layer electroless 202a, 202b that is optional. 随后,电镀第五金属层204a、204b分别形成在第四金属层202a、202b上。 Subsequently, plating fifth metal layer 204a, 204b are respectively formed on the fourth metal layer 202a, 202b. 进行至此,上述图案化光阻层198可将其进行去除。 Thus for the patterned photoresist layer 198 may be removal.

[0187] 接着请参考图12g所示,形成一光阻层206在种子层188、部份第三金属层196b、 第三金属层196c以及第五金属层204a、204b上,再来请参阅图12h,图案化此光阻层206以形成开口208暴露出第三金属层196c,其中此开口208是形成于铜接垫328的上方,并使第三金属层196c的顶部表面上可以进行曝光制造方法。 [0187] Please refer to FIG 12g shown, is formed in 188 206, the third metal layer portion 196b seed layer, the third metal layer 196c and the fifth photoresist layer a metal layer 204a, the 204b, again see FIG. 12h , this patterned photoresist layer 206 to form openings 208 to expose the third metal layer 196c, wherein this opening 208 is formed over the copper pad 328, and the third metal layer may be exposed on the top surface of the manufacturing method of 196c . 接着请参阅图12i,在开口208中, 一金属凸块210形成在已曝光的第三金属层196c上方,其中此属凸块210的材质为锡铅合金、锡银合金、锡银铜合金。 Referring to FIG. 12i Next, in the opening 208, a metal bump 210 is formed over the exposed third metal layer 196c, the case where this bump 210 is made of tin-lead alloy, tin silver alloy, tin-silver-copper alloy. 进行至此,上述图案化光阻层206可将其进行去除,最后再将未在第二金属层194a、194b、194c下的种子层188与第一金属层186去除,即形成如第12a图所示的结构。 Thus for the patterned photoresist layer 206 may be removed to the last 186 is not removed then the second metal layer 194a, 194b, 194c seed layer 188 under the first metal layer, i.e., it is formed as first to FIG 12a configuration shown.

[0188] 另,有关在本实施例中形成第一金属层186、种子层188、光阻层190、198、206,以及图案化光阻层190、198、206和去除未在第二金属层194a、194b、194c下的种子层188与第一金属层186的方式均与上述各实施例相同,在此并不再次详加叙述。 [0188] Also, relating to a first metal layer 186, the seed layer 188, 190,198,206 photoresist layer, and a patterned photoresist layer in the present embodiment, 190,198,206 and the second metal layer is not removed 194a, 194b, 188 with the first metal layer 186 under the seed layer 194c are the same as with the above embodiments, this is not described in detail again.

[0189] 本发明在半导体基底(晶圆)的铜接垫上藉由电镀或无电电镀的方式,产生了许多不同型态的多层金属层结构,而形成各种不同对外的接点结构,比如形成接垫(pad)、凸块(bump)等,此接垫及凸块皆可透过打线或异方性导电胶电连接至外界电路上,使半导体组件的应用更具多元化连接方式。 [0189] The present invention is a copper semiconductor substrate (wafer) on the pads by electroplating or electroless plating manner, produces a number of different multilayer structure of the metal layer patterns to form the external contacts of different configuration, such as application of forming pad (pAD), bumps (bump) and the like, this pad and the bump objects can connect to the external circuit through a wire or anisotropic electrically conductive adhesive, the semiconductor connection component is more diversified . 另外,有关上述各种实施例的叙述除了可以应用在铜接垫之外,亦可应用在铝接垫上,在此特以说明,但并不再次详加阐述。 Further, on the above description of the various embodiments may be applied in addition to the copper pad outside, it can also be applied in the aluminum contact pads, to be described in this special, but not explained in detail again.

[0190] 综上所述,藉由实施例说明本发明的特点,其目的在使熟悉该领域的普通一般技术人员能暸解本发明的内容并据以实施,而非限定本发明专利的权利要求保护范围,故,凡其它未脱离本发明所揭示的精神所完成的等效修饰或修改,仍应包含在以下所述的权利要求范围中。 [0190] In summary, by examples illustrate features of the invention, an object of the present invention can understand that the skilled in the art and one of ordinary skill in the art according to the general embodiment, the present invention is not defined in the patent claims the scope of protection, so, where the other without departing from the spirit of the invention disclosed modifications or equivalents completed modification, the following should still be included in the scope of the claims.

Claims (21)

  1. 一种线路组件结构,其特征在于,包括:一半导体基底;一介电层,位于该半导体基底之上;一线路层,位于该介电层之上,且该线路层包括铜金属;一无机保护层,位于该介电层上方以及位于该线路层上方;一铜接垫,位于该线路层上方,且该无机保护层位于该铜接垫旁;一阻障层,包覆该铜接垫的下表面及侧壁,且该阻障层的材质为钽、氮化钽或氮化钛;一氮硅化合物层,位于该无机保护层的上表面之上以及位于该铜接垫的部分上表面之上,且该铜接垫位于该氮硅化合物层内的一开口下;一第一金属层,位于该铜接垫上以及位于该开口内,且该第一金属层的材质为钛、氮化钛或钛钨合金;一第二金属层,位于该第一金属层上,且该第二金属层的材质为铝;一第三金属层,位于该第二金属层上,且该第三金属层的材质为钛、氮化钛、钛钨合金、 A circuit assembly structure comprising: a semiconductor substrate; a dielectric layer located above the semiconductor substrate; a wiring layer located over the dielectric layer, and the wiring metal layer comprises copper; an inorganic protective layer over the dielectric layer, and the upper wiring layer; a copper pad located in the upper wiring layer, and the inorganic protective layer is positioned next to the copper pad; a barrier layer covering the copper pad the lower surface and sidewalls, and a material of the barrier layer is tantalum, tantalum nitride or titanium nitride; a silicon nitride compound layer on the inorganic protective layer located above the upper surface and located on the portion of copper pads over the surface, and the copper pad located in an opening in the silicon nitrogen compound layer; a first metal layer on the copper contact pad, and located within the opening, and the material of the first metal layer is titanium, nitrogen titanium or a titanium-tungsten alloy; a second metal layer on the first metal layer, and the material of the second metal layer is aluminum; a third metal layer on the second metal layer, and the third material of the metal layer is titanium, titanium nitride, titanium tungsten, 铜合金、钽或氮化钽;以及一铜层,位于该第三金属层上,该铜层接触该第三金属层,且该铜层经由该第三金属层、该第二金属层及该第一金属层连接该铜接垫。 Copper alloys, tantalum or tantalum nitride; and a copper layer on the third metal layer, the copper layer contacting the third metal layer and the copper layer through the third metal layer, the metal layer and the second a first metal layer connected to the copper pad.
  2. 2.根据如权利要求1所述的线路组件结构,其特征在于,该介电层包括介电常数值(k) 介于1.5至3之间的材质。 The structure of the assembly line as claimed in claim 1, wherein the dielectric layer comprises a dielectric constant (k) material is interposed between 1.5 and 3.
  3. 3.根据如权利要求1所述的线路组件结构,其特征在于,该半导体基底为硅基底。 The structure of the assembly line as claimed in claim 1, wherein the semiconductor substrate is a silicon substrate.
  4. 4.根据如权利要求1所述的线路组件结构,其特征在于,该无机保护层的材质为氮硅化合物。 The structure of the assembly line as claimed in claim 1, wherein the inorganic material of the protective layer is a silicon nitride compound.
  5. 5.根据如权利要求1所述的线路组件结构,其特征在于,还包括厚度介于0. 1微米至10微米之间的一金层,该金层位于该铜层上方但未接触该铜层,且该金层经由该铜层连接该铜接垫。 The structure of the assembly line as claimed in claim 1, characterized in that, further comprising a gold layer thickness between between 0.1 to 10 microns, the gold layer over the copper layer, but not in contact with the copper layer, and the gold layer connected to the copper layer through the copper pad.
  6. 6.根据如权利要求1所述的线路组件结构,其特征在于,还包括一金氧半导体组件,该半导体基底承载该金氧半导体组件。 The structure of the assembly line as claimed in claim 1, characterized in that, further comprising a metal-oxide-semiconductor device, the semiconductor substrate carrying the metal-oxide-semiconductor element.
  7. 7. 一种线路组件结构,其特征在于,包括: 一半导体基底;一介电层,位于该半导体基底之上; 一线路层,位于该介电层之上,且该线路层包括铜金属; 一无机保护层,位于该介电层上方以及位于该线路层上方; 一铜接垫,位于该线路层上方,且该无机保护层位于该铜接垫旁; 一阻障层,包覆该铜接垫的下表面及侧壁,且该阻障层的材质为钽、氮化钽或氮化钛; 一氧硅化合物层,位于该无机保护层的上表面之上以及位于该铜接垫的部分上表面之上,且该铜接垫位于该氧硅化合物层内的一开口下;一第一金属层,位于该铜接垫上以及位于该开口内,且该第一金属层的材质为钛、氮化钛或钛钨合金;一第二金属层,位于该第一金属层上,且该第二金属层的材质为铝;一第三金属层,位于该第二金属层上,且该第三金属层的材质为钛、氮化钛、钛钨 A line assembly structure comprising: a semiconductor substrate; a dielectric layer located above the semiconductor substrate; a wiring layer located over the dielectric layer, and the wiring metal layer comprises copper; an inorganic protective layer over the dielectric layer, and the upper wiring layer; a copper pad located in the upper wiring layer, and the inorganic protective layer is positioned next to the copper pad; a barrier layer covering the copper bonding a lower surface and sidewalls of the pad, and the barrier layer is made of tantalum, tantalum nitride, or titanium nitride; a silicon oxide compound layer positioned on the upper surface of the inorganic protective layer, and the copper pads located above the upper part of the surface, and the copper pad located in an opening in the oxide silicon compound layer; a first metal layer on the copper contact pad, and located within the opening, and the material of the first metal layer is titanium , titanium nitride or titanium tungsten; a second metal layer on the first metal layer, and the material of the second metal layer is aluminum; a third metal layer on the second metal layer, and the the third metal layer is made of titanium, titanium nitride, titanium tungsten 金、铬铜合金、钽或氮化钽;以及一铜层,位于该第三金属层上,该铜层接触该第三金属层,且该铜层经由该第三金属层、该第二金属层及该第一金属层连接该铜接垫。 Gold, copper alloy, chromium, tantalum, or tantalum nitride; and a copper layer on the third metal layer, the copper layer contacting the third metal layer and the copper layer through the third metal layer, the second metal a first metal layer and the copper layer connected to the pad.
  8. 8.根据如权利要求7所述的线路组件结构,其特征在于,该介电层包括介电常数值(k) 介于1.5至3之间的材质。 The structure of the assembly line as claimed in claim 7, wherein the dielectric layer comprises a dielectric constant (k) material is interposed between 1.5 and 3.
  9. 9.根据如权利要求7所述的线路组件结构,其特征在于,该半导体基底为硅基底。 9. The structure of the circuit assembly as claimed in claim 7, wherein the semiconductor substrate is a silicon substrate.
  10. 10.根据如权利要求7所述的线路组件结构,其特征在于,该无机保护层的材质为氮硅化合物。 10. The structure of the circuit assembly as claimed in claim 7, wherein the inorganic material of the protective layer is a silicon nitride compound.
  11. 11.根据如权利要求7所述的线路组件结构,其特征在于,还包括厚度介于0. 1微米至10微米之间的一金层,该金层位于该铜层上方但未接触该铜层,且该金层经由该铜层连接该铜接垫。 11. The structure of the circuit assembly as claimed in claim 7, characterized in that, further comprising a gold layer thickness between between 0.1 to 10 microns, the gold layer over the copper layer, but not in contact with the copper layer, and the gold layer connected to the copper layer through the copper pad.
  12. 12.根据如权利要求7所述的线路组件结构,其特征在于,还包括一金氧半导体组件, 该半导体基底承载该金氧半导体组件。 12. The structure of the circuit assembly as claimed in claim 7, characterized in that, further comprising a metal-oxide-semiconductor device, the semiconductor substrate carrying the metal-oxide-semiconductor element.
  13. 13. —种线路组件结构,其特征在于,包括: 一金氧半导体组件;一半导体基底,承载该金氧半导体组件; 一介电层,位于该半导体基底之上; 一线路层,位于该介电层之上,且该线路层包括铜金属; 一无机保护层,位于该介电层上方以及位于该线路层上方; 一铜接垫,位于该线路层上方,且该无机保护层位于该铜接垫旁; 一阻障层,包覆该铜接垫的下表面及侧壁,且该阻障层的材质为钽、氮化钽或氮化钛; 一保护层,位于该无机保护层的上表面上以及位于该铜接垫的部分上表面上,该保护层接触该铜接垫的部分上表面以及接触该无机保护层的上表面,且该铜接垫位于该保护层内的一开口下;一第一金属层,位于该铜接垫上以及位于该开口内,且该第一金属层的材质为钛、氮化钛或钛钨合金;一第二金属层,位于该第一金属层上,且该第二金 13. - Species line assembly structure comprising: a metal-oxide-semiconductor element; a semiconductor substrate, carrying the metal-oxide-semiconductor element; a dielectric layer located above the semiconductor substrate; a wiring layer on the dielectric top layer, and the wiring metal layer comprises copper; an inorganic protective layer located over the dielectric layer, and the upper wiring layer; a copper pad located in the upper wiring layer, and the inorganic protective layer disposed Cu pad beside; a barrier layer, coating a lower surface and a sidewall of the copper pads, and the material of the barrier layer is tantalum, tantalum nitride, or titanium nitride; a protective layer, the inorganic protective layer is located the upper surface of the upper and located on the copper pad part of the surface, the protective layer is in contact with the copper pads on the portion of the surface and the upper surface contacts the inorganic protective layer, and the copper pad located in the protective layer is an opening under; a first metal layer on the copper contact pad, and located within the opening, and the material of the first metal layer is titanium, titanium nitride, or titanium tungsten; a second metal layer, the first metal layer located on, and the second metal 层的材质为铝;以及一铜层,位于该第二金属层上方但未接触该第二金属层,且该铜层经由该第二金属层及该第一金属层连接该铜接垫。 Layer is made of aluminum; and a copper layer disposed over the second metal layer but not in contact with the second metal layer and the copper layer connected to the copper pad via the second metal layer and the first metal layer.
  14. 14.根据如权利要求13所述的线路组件结构,其特征在于,该无机保护层的材质为氮硅化合物。 14. The circuit device structure according to claim 13, wherein the inorganic material of the protective layer is a silicon nitride compound.
  15. 15.根据如权利要求13所述的线路组件结构,其特征在于,该铜层的厚度介于0. 1微米至10微米之间。 15. The circuit device structure according to claim 13, wherein the thickness of the copper layer is between 0.1 to 10 microns.
  16. 16.根据如权利要求13所述的线路组件结构,其特征在于,该保护层包括一氮硅化合物层。 16. The circuit device structure according to claim 13, wherein the protective layer comprises a silicon nitride compound layer.
  17. 17.根据如权利要求13所述的线路组件结构,其特征在于,该保护层包括一氧硅化合物层。 17. The circuit device structure according to claim 13, wherein the protective layer comprises a silicon oxide compound layer.
  18. 18.根据如权利要求13所述的线路组件结构,其特征在于,还包括厚度介于0.1微米至10微米之间的一金层,该金层位于该铜层上方但未接触该铜层,且该金层经由该铜层连接该铜接垫。 18. The circuit device structure according to claim 13, characterized in that, further comprising a gold layer thickness between between 0.1 to 10 microns, the gold layer over the copper layer, but not in contact with the copper layer, connected to the gold layer and the copper layer through the copper pad.
  19. 19.根据如权利要求13所述的线路组件结构,其特征在于,还包括位于该第二金属层上的一第三金属层,该铜层位于该第三金属层上方,且该第三金属层的材质为钛、氮化钛、 钛钨合金、铬铜合金、钽或氮化钽。 19. The circuit device structure according to claim 13, characterized in that, further comprising a third metal layer on the second metal layer, the copper layer located above the third metal layer, and the third metal layer is made of titanium, titanium nitride, titanium-tungsten alloy, copper alloy, chromium, tantalum or tantalum nitride.
  20. 20.根据如权利要求13所述的线路组件结构,其特征在于,还包括厚度介于0. 1微米至10微米之间的一镍层,且该镍层位于该铜层上并接触该铜层。 20. The circuit device structure according to claim 13, characterized in that, further comprising a nickel layer interposed between a thickness of 0.1 to 10 microns, and the nickel layer on the copper layer and positioned in contact with the copper Floor.
  21. 21.根据如权利要求13所述的线路组件结构,其特征在于,该开口的最大横向尺寸介于0.5微米至15微米之间。 21. The circuit device structure according to claim 13, wherein the maximum transverse dimension of the opening is between 0.5 to 15 microns.
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US6197688B1 (en) 1998-02-12 2001-03-06 Motorola Inc. Interconnect structure in a semiconductor device and method of formation

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