CN1889001A - Low-pressure drop stabilizer with common-mode negative feedback - Google Patents
Low-pressure drop stabilizer with common-mode negative feedback Download PDFInfo
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- CN1889001A CN1889001A CN 200510080154 CN200510080154A CN1889001A CN 1889001 A CN1889001 A CN 1889001A CN 200510080154 CN200510080154 CN 200510080154 CN 200510080154 A CN200510080154 A CN 200510080154A CN 1889001 A CN1889001 A CN 1889001A
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Abstract
The invention provides a low pressure loss voltage regulator circuit with the common-mode negative feedback. The circuit has an error amplifier with the common-mode negative feedback unit, the drive element and a compensation circuit. The signal from the drive element is provided to the error amplifier and compared with another inputting signal to make a difference signal which is amplified and provided to the driving element. The capacitance in the compensation unit provides the frequency compensation for the low pressure loss voltage regulator. The common-mode negative feedback unit is in the error amplifier, so it can improve the transferring speed of the driving element grid voltage.
Description
Technical field
The present invention relates to voltage stabilizer, relate to the low dropout voltage regulator of low-power consumption more specifically.
Background technology
Current demand to the high-performance feed circuit makes the sustainable development of voltage stabilizer equipment.Many low voltage products such as equipment such as mobile phone, pager, kneetop computer, video camera and other employing mobile batteries, need to use low pressure drop (LDO) voltage stabilizer.These portable electronics are used needs low pressure drop and little quiescent current to increase battery effect and battery life usually.
Usually, the LDO voltage stabilizer provides specific DC burning voltage, and the voltage difference between the input of this voltage and output is less.The LDO voltage stabilizer is usually used in providing required power supply to circuit.The LDO voltage stabilizer has error amplifier, driving element (pass element) (for example transistor) usually.Above-mentioned two element connected in series connect.Error amplifier is connected to an input end of LDO voltage stabilizer, and driving element is connected to an output terminal of LDO voltage stabilizer.Thereby driving element can drive external loading.
Usually also provide feedback circuit to the LDO voltage stabilizer, will feed back to error amplifier through the output voltage of dividing potential drop by voltage divider.The LDO voltage stabilizer also includes compensating circuit, thereby this compensating circuit provides miller compensation to improve the stability of LDO voltage stabilizer.
Driving element is returned the LDO voltage stabilizer and is introduced a big grid stray capacitance.The transient response characteristic of LDO voltage stabilizer is subjected to stray capacitance to discharge and recharge the restriction of speed (being defined as switching rate) to a great extent.In addition, exist big stray capacitance can make the frequency response of error amplifier produce an influential limit, this just makes error amplifier more difficult stable.As mentioned above, the big stray capacitance in the driving element also need dispose an impact damper usually, and for example source follower or unity gain buffer are kept apart the high impedance and the big stray capacitance of error amplifier gain stage.
Traditionally, thus insert dynamic bias circuit at the limits node and improve transient response performance.Yet, insert the complicacy that dynamic bias circuit can increase the LDO voltage stabilizer, thereby increase the frequency compensated difficulty of LDO, make the design of LDO voltage stabilizer become more complicated.
Therefore, need a kind of equipment and method, stable output voltage and higher switching rate and simple structure are provided when the load capacitance variation range is big, have low quiescent dissipation, stronger driving force and stability simultaneously.The present invention aims to provide such equipment and method.
Summary of the invention
In one embodiment, the invention provides a kind of degenerative LDO voltage regulator circuit of common mode that has.The LDO voltage regulator circuit comprises that an error amplifier that has a common mode negative feedback unit is used to produce a fault in enlargement, one output voltage driving element, a feedback circuit and compensating circuit that affords redress with the output voltage dividing potential drop to drive at least one outer member is provided.Error amplifier has one to receive the first input end of reference voltage, second input end, the 3rd input end and an output terminal that receives feedback voltage.Driving element has an input end and an output terminal, and the input end of driving element is connected to the output terminal of error amplifier.Feedback circuit has one first end and one second end.First end of feedback circuit is connected to the output terminal of driving element, and second end of feedback circuit is connected to second input end of error amplifier.Compensating circuit has one first end and one second end.First end of compensating circuit is connected to the output terminal of driving element, and second end of compensation equipment is connected to the 3rd end of error amplifier.
In another embodiment, the invention provides a kind of method of in having the degenerative low dropout (LDO) regulator circuit of common mode, exporting burning voltage.The method comprising the steps of: produce one and amplify voltage in error amplifier, to amplify the driven driving element, increase the switching rate of driving element grid voltage by the common mode negative feedback unit in the use error amplifier, obtain output voltage from driving element, provide frequency compensation so that regulated output voltage.
Description of drawings
Other characteristic of the present invention and advantage will be in following detailed descriptions and are more obvious in conjunction with illustrated explanation, wherein:
Figure 1 shows that the structural drawing that has the degenerative low dropout voltage regulator of common mode (LDO).
Figure 2 shows that the schematic diagram of Fig. 1 LDO voltage stabilizer according to an embodiment of the invention.
Figure 3 shows that the analogous diagram of the transient response of Fig. 2 LDO voltage stabilizer.
Figure 4 shows that the schematic diagram of common mode negative feedback unit in accordance with another embodiment of the present invention.
Figure 5 shows that the schematic diagram of the common mode negative feedback unit of another embodiment according to the present invention.
Embodiment
The invention provides a kind of degenerative LDO voltage stabilizer of common mode that has, therefore when external loading changed under different condition, the LDO voltage stabilizer just can return to steady state (SS) with output voltage fast.Fig. 1 has illustrated to have the structural drawing of the degenerative LDO voltage stabilizer 100 of common mode.Voltage stabilizer 100 comprises an error amplifier 110, driving element 130, a feedback circuit 140 and a compensating circuit 150.Voltage stabilizer 100 also comprises a common mode negative feedback unit 120, thereby the switching rate of incorporating the MOS transistor grid voltage of driving element 130 by increase into is accelerated LDO Transient Structural Response speed.Supply voltage VIN offers error amplifier 110 and driving element 130 respectively.Driving element 130 provides output voltage VO UT for the external loading (not shown) at output terminal.
Fig. 2 has illustrated principle Figure 200 of one exemplary embodiment of Fig. 1 LDO voltage stabilizer 100.Voltage stabilizer 200 comprises an error amplifier 110, driving element 130, a feedback circuit 140 and a feedback circuit 150.Error amplifier 110 also comprises a common mode negative feedback unit 120A who strengthens the transient response speed of LDO stabilizator structure.Power supply VIN offers the driving element 130 between error amplifier 110 and power rail 11 and the ground connection rail 12.The current source (not shown) provides a bias current IBIAS from incoming line 13.Thereby bypass circuit 130 output voltage VO UT drive the external loading (not shown) on the output line 14.
In error amplifier 110, the differential input signal of line 15 and line 16 offers PMOS transistor 21,22 differential pairs.PMOS transistor 23 and 24,25 and 26 forms two independent current mirrors.PMOS transistor 23 is set up internal bias voltage according to the input bias current IBIAS on the line 13.PMOS transistor 24 is biased by bias voltage.The mirror image bias current of PMOS transistor 24 can start PMOS transistor 21 and 22.PMOS transistor 21 and 22 differential pairs receive voltage VREF on the line 15 and 16 and VFB and start working.Similarly, PMOS transistor 21 and 22 can start nmos pass transistor 29 and 30 respectively.The voltage VA of node A and B and VB can start nmos pass transistor 27 and 28 respectively.Operation nmos pass transistor 27 just can start PMOS transistor 25 and 26 current mirrors that form.The drain electrode output signal of PMOS transistor 26 drives driving element 130.In addition, error amplifier 110 also comprises the frequency compensated electric capacity 62 that is used for optimal compensating circuit 150.
Common mode negative feedback unit 120A comprises resistance 41 and 42.Resistance 41 is connected between node A and the node CMFB, and resistance 42 is connected between Node B and the node CMFB.Electric capacity 43 and resistance are 41 in parallel, electric capacity 44 is in parallel with resistance 42, and further frequency compensation is provided.
Resitstance voltage divider is as feedback circuit 140.Resitstance voltage divider comprises first resistance 47 and second resistance 48 of series connection.Resistance 47 can be according to resistance 47 and 48 different resistances to the output voltage VO UT dividing potential drop on the line 14 with 48, and with a grid that is lower than the Voltage Feedback of VOUT to PMOS transistor 22.As shown in the figure, resistance 47 and 48 has been realized the feedback system of voltage stabilizer, and can regulate feedback voltage with 48 different resistances by choosing resistance 47.
Compensating circuit 150 comprises miller compensation electric capacity 52.Compensating circuit 150 is connected between output voltage VO UT and the node A.Thereby compensating circuit 150 mainly affords redress and utilizes Miller effect to guarantee voltage stabilizer 200 output voltage stabilizations.
Traditionally, the load capacitance with equivalent series resistance (ESR) (not shown) is in parallel with external loading, and is connected between the output terminal and ground of voltage stabilizer.In this embodiment, IC is defined as the electric current that flows through load capacitance, and ILOAD represents to flow through the electric current of external loading.
Under the transient state situation, if load current ILOAD increases, the load capacitance discharge is charged to external loading.Therefore, output voltage VO UT reduces at once, and the feedback voltage V FB on the isochrone 16 is corresponding to be reduced.As a result, flow through I 2 increases of PMOS transistor 22 drain electrodes.The electric current I R flow direction that flows through resistance 42 and 41 can be with shown in Figure 2 opposite.Therefore, the voltage VB of Node B increases relatively, and the voltage VA of node A reduces relatively.Because the grid of nmos pass transistor 27 is connected to node A, therefore the grid voltage of nmos pass transistor 27 also can reduce.Electric current I 27 and image current I26 will reduce.Because nmos pass transistor 28 is connected to Node B, the corresponding increase of the grid voltage of nmos pass transistor 28.The increase of nmos pass transistor grid voltage makes electric current I 28 increase.Therefore, the grid forced electric discharge of PMOS transistor 31 makes the grid voltage of PMOS transistor 31 descend.Output current IO UT on the line 14 diminishes along with the grid voltage of PMOS transistor 31 and increases.Thereby the output current IO UT of increase can will increase load capacitance charging and output voltage VO UT.At last, output voltage VO UT can remain on a setting value.
In addition, if load current ILOAD reduces, load capacitance can be recharged, and output voltage VO UT will increase like this.Under the transient state situation, the feedback voltage V FB on the line 16 scales up.The increase of feedback voltage V FB makes electric current I 2 reduce.Therefore, electric current I R flows through resistance 41 and 42 with direction shown in Fig. 2.The voltage of node A increases relatively, and the voltage of Node B reduces relatively.Because the grid of nmos pass transistor 27 is connected to node A, the grid voltage of nmos pass transistor 27 also will increase.The grid voltage of nmos pass transistor 27 increases makes the electric current I 27 that flows through 25 drain electrodes of PMOS transistor increase.The image current I26 that PMOS transistor 25 and 26 current mirrors that form produce increases along with the increase of electric current I 27.The voltage of Node B reduces to cause the grid voltage of nmos pass transistor 28 to diminish.Therefore, electric current I 28 also reduces corresponding.Flow through the gate charges of the electric current I 26 of PMOS transistor 26 drain electrodes with pair pmos transistor 31, PMOS transistor 31 grid voltages just will increase rapidly like this.Therefore, the output current IO UT on the line 14 can reduce to a smaller value and load capacitance is discharged fast.Thereby output voltage VO UT reduces fast and finally remains on a setting value.Therefore, the grid voltage of PMOS transistor 31 can change fast according to load current, and promptly the switching rate of driving element 130 grid voltages significantly improves.
Referring to Fig. 3, Fig. 3 has illustrated the exemplary simulation figure of the transient response of LDO voltage stabilizer 200 among Fig. 2.Following output voltage VO UT on voltage table timberline 14 among Fig. 3 descends.LDO voltage stabilizer 200 is the variation of regulated output voltage VOUT rapidly, and final output voltage VO UT can remain stable within a short period of time (for example Δ t1).Opposite, because external loading changes when output voltage VO UT upper punch, LDO voltage stabilizer 200 reduces the upper punch of output voltage VO UT rapidly.Therefore, LDO voltage stabilizer 200 is reduced to another stationary value rapidly with output voltage VO UT value in the Δ t2 time.
For simplicity, Fig. 4 and Fig. 5 have omitted the like of LDO voltage stabilizer 200 among other embodiment, only the different structure of common mode negative feedback unit are briefly described.Fig. 4 has illustrated the schematic diagram of common mode negative feedback unit 120B according to an embodiment of the invention.Common mode negative feedback unit 120B is incorporated in the error amplifier 110 and can replaces common mode negative feedback unit 120A.Fig. 5 has illustrated according to the schematic diagram of another common mode negative feedback unit 120C of the present invention.Common mode negative feedback unit 120C also may be incorporated in the error amplifier 110.The embodiment 120B of Fig. 4 and Fig. 5 and 120C are not just giving unnecessary details here according to the function of similar principles realization Fig. 2 common mode negative feedback unit 120A.
Among Fig. 4, common mode negative feedback unit 120B comprises resistance 401 and 402, inductance 411 and 412, PMOS transistor 431 and 432 and nmos pass transistor 441 and 442.Resistance 401 is connected to node A, and resistance 402 is connected to Node B.The drain electrode of PMOS transistor 432 is connected to node CMFB.The source electrode of PMOS transistor 431 is connected to the DC input voltage VIN, and the grid of PMOS transistor 431 is connected to node D, and the drain electrode of PMOS transistor 431 is connected to the drain electrode of nmos pass transistor 441. Nmos pass transistor 441 and 442 forms image current.The source electrode of PMOS transistor 432 is connected to the DC input voltage VIN, and the grid of PMOS transistor 432 is connected to a setting voltage, and the drain electrode of PMOS transistor 432 is connected to the drain electrode of nmos pass transistor 432.
Referring to Fig. 5, common mode negative feedback unit 120C comprises resistance 402 and 402, electric capacity 411 and 412 and nmos pass transistor 551.The direct ground connection of the drain electrode of PMOS transistor 431.The drain and gate of nmos pass transistor 551 is connected to the drain electrode of PMOS transistor 432, the source ground of nmos pass transistor 551.The grid of nmos pass transistor is connected to node CMFB.
Though among Fig. 2 capacitor C C1 is described, those skilled in the art will be appreciated that the element that can also use other types, for example, and polycrystalline electric capacity or MOS transistor.Similarly, those skilled in the art will be appreciated that can also carry out many transformations to the present invention realizes feedback circuit 140.For example, can adopt variable resistor in the feedback circuit 140.What in addition, the type of various MOS transistor neither be fixed among Fig. 2.Those skilled in the art will be appreciated that also there are other substitutes of MOS transistor in present embodiment.Can adopt the transistor of other types and other combinations to realize the function of error amplifier 110 and driving element 130, these do not break away from spirit of the present invention.
Those skilled in the art will be appreciated that and can also carry out many alternative, modifications and variations to the present invention to common mode negative feedback unit 120.All alternative, modifications and variations do not break away from spirit of the present invention.
In service, LDO voltage regulator circuit 100 receives a DC input signal VIN and exports a stable dc voltage VOUT according to the different demands of many application.Error amplifier 110 in the LDO voltage regulator circuit 100 is compared a reference signal VREF with the feedback signal VFB that receives from feedback circuit 140, and the difference of an amplification is provided at output terminal.
At the embodiment of this narration is the some of them of many possible embodiment, these embodiment be illustrative and and nonrestrictive.Obviously, can also implement conspicuous for those skilled in the art other embodiment, not break away from as the defined the spirit and scope of the present invention of accessory claim.
Claims (20)
1. one kind has the degenerative low dropout voltage regulator of common mode, it is characterized in that, comprising:
One has the error amplifier that common mode negative feedback unit is used to produce the error voltage of an amplification, described error amplifier has a first input end that receives reference voltage, second input end that receives feedback voltage, one the 3rd input end and an output terminal;
One offers the driving element of at least one outer member with output voltage, and described driving element has an input end and an output terminal, and the input end of described driving element is connected to the output terminal of described error amplifier;
Feedback circuit with the output voltage dividing potential drop, described feedback circuit has one first end and one second end, first end of described feedback circuit is connected to the output terminal of described driving element, and second end of described feedback circuit is connected to second input end of described error amplifier; With
A compensating circuit that affords redress, described compensating circuit have one first end and one second end, and first end of described compensating circuit is connected to the output terminal of described driving element, and second end of compensating circuit is connected to the 3rd end of described error amplifier.
2. low dropout (LDO) regulator circuit according to claim 1 is characterized in that, described common mode negative feedback unit has one first end, one second end and one the 3rd end.
3. low dropout (LDO) regulator circuit according to claim 2 is characterized in that, described common mode negative feedback unit comprises first resistance with one first end and one second end, second resistance with one first end and one second end.First end of described first resistance is connected to first end of described common mode negative feedback unit, second end of described second resistance is connected to second end of described common mode negative feedback unit, and first end of second end of described first resistance and described second resistance is connected to the 3rd end of described common mode negative feedback unit.
4. low dropout (LDO) regulator circuit according to claim 3, it is characterized in that, described common mode negative feedback unit further comprises one first electric capacity and one second electric capacity, described first electric capacity is in parallel with described first resistance to be used to provide frequency compensation, and described second electric capacity is in parallel with described second resistance to be used to provide frequency compensation.
5. low dropout (LDO) regulator circuit according to claim 2, it is characterized in that, described common mode negative feedback unit comprises first resistance with one first end and one second end, second resistance with one first end and one second end, one the one PMOS transistor, one the 2nd PMOS transistor, one first nmos pass transistor and one second nmos pass transistor.
6. low dropout (LDO) regulator circuit according to claim 5, it is characterized in that, first end of described first resistance is connected to first end of described common mode negative feedback unit, second end of described first resistance and first end of described second resistance are connected to a common node, and second end of described second resistance is connected to second end of described common mode negative feedback unit.
7. low dropout (LDO) regulator circuit according to claim 5, it is characterized in that, the transistorized source electrode of a described PMOS is connected to the transistorized source electrode of described the 2nd PMOS, the transistorized grid of described PMOS is connected to described common node, and described PMOS transistor drain is connected to the drain electrode of described first nmos pass transistor.
8. low dropout (LDO) regulator circuit according to claim 5 is characterized in that, the transistorized grid of described the 2nd PMOS is connected to a setting voltage, and described PMOS transistor drain is connected to the 3rd end of described common mode negative feedback unit.
9. low dropout (LDO) regulator circuit according to claim 5 is characterized in that the grid of described first nmos pass transistor is connected to the grid of described second nmos pass transistor, the source ground of described nmos pass transistor.
10. low dropout (LDO) regulator circuit according to claim 5 is characterized in that, the drain electrode of described second nmos pass transistor is connected to the 3rd end of described common mode negative feedback unit, the source ground of described second nmos pass transistor.
11. low dropout (LDO) regulator circuit according to claim 5, it is characterized in that, described common mode negative feedback unit further comprises one first electric capacity and one second electric capacity, described first electric capacity is in parallel with first resistance to be used to provide frequency compensation, and second electric capacity is in parallel with described second resistance to be used to provide frequency compensation.
12. low dropout (LDO) regulator circuit according to claim 2, it is characterized in that, described common mode negative feedback unit comprises first resistance with first end and one second end, second resistance with first end and second end, a PMOS transistor, one first nmos pass transistor and one second nmos pass transistor.
13. low dropout (LDO) regulator circuit according to claim 12, it is characterized in that, first end of described first resistance is connected to first end of described common mode negative feedback unit, second end of described first resistance and first end of described second resistance are connected to common node, and second end of described second resistance is connected to second end of described common mode negative feedback unit.
14. low dropout (LDO) regulator circuit according to claim 12, it is characterized in that, the transistorized source electrode of a described PMOS is connected to the transistorized source electrode of described the 2nd PMOS, the transistorized grid of a described PMOS is connected to described common node, and a described PMOS transistor drain ground connection.
15. low dropout (LDO) regulator circuit according to claim 12 is characterized in that, the transistorized grid of described the 2nd PMOS is connected to a setting voltage, and described the 2nd PMOS transistor drain is connected to the 3rd end of described common mode negative feedback unit.
16. low dropout (LDO) regulator circuit according to claim 12 is characterized in that, the drain and gate of described nmos pass transistor is connected to the 3rd end of common mode negative feedback unit, the source ground of described nmos pass transistor.
17. low dropout (LDO) regulator circuit according to claim 12, it is characterized in that, described common mode negative feedback unit further comprises one first electric capacity and one second electric capacity, described first electric capacity is used to provide frequency compensation with described first resistance is in parallel, and described second electric capacity is in parallel with described second resistance is used to provide frequency compensation.
18. low dropout (LDO) regulator circuit according to claim 1 is characterized in that, described error amplifier comprises that further a metal oxide semiconductor transistor is used for optimal compensating.
19. the method for an output burning voltage in having the degenerative low dropout (LDO) regulator circuit of common mode is characterized in that, comprises step:
In error amplifier, produce the voltage of an amplification;
Driven driving element with described amplification;
Increase the switching rate of driving element grid voltage by the common mode negative feedback unit in the use error amplifier;
Obtain an output voltage from driving element; With
Thereby provide the frequency compensation regulated output voltage to low dropout voltage regulator.
20. method according to claim 21 is characterized in that, further comprises step:
Receive a reference voltage; With
Receive a feedback voltage, wherein reference voltage and feedback voltage are used to produce the voltage of described amplification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100801547A CN100437415C (en) | 2005-06-30 | 2005-06-30 | Low-pressure drop stabilizer with common-mode negative feedback |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100801547A CN100437415C (en) | 2005-06-30 | 2005-06-30 | Low-pressure drop stabilizer with common-mode negative feedback |
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| CN1889001A true CN1889001A (en) | 2007-01-03 |
| CN100437415C CN100437415C (en) | 2008-11-26 |
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| CNB2005100801547A Expired - Fee Related CN100437415C (en) | 2005-06-30 | 2005-06-30 | Low-pressure drop stabilizer with common-mode negative feedback |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411394A (en) * | 2011-11-10 | 2012-04-11 | 昌芯(西安)集成电路科技有限责任公司 | Linear voltage stabilizer with low pressure differential and Sink and Source current capabilities |
| CN104635824A (en) * | 2013-11-14 | 2015-05-20 | 台湾积体电路制造股份有限公司 | Low dropout regulator and related method |
| CN105634521A (en) * | 2014-11-26 | 2016-06-01 | 成都振芯科技股份有限公司 | MLVDS receiving circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2096844U (en) * | 1991-07-06 | 1992-02-19 | 叶志高 | Symmetry audio-frequency amplifier |
| US5686821A (en) * | 1996-05-09 | 1997-11-11 | Analog Devices, Inc. | Stable low dropout voltage regulator controller |
| US6703816B2 (en) * | 2002-03-25 | 2004-03-09 | Texas Instruments Incorporated | Composite loop compensation for low drop-out regulator |
| US6774722B2 (en) * | 2002-10-16 | 2004-08-10 | Centillium Communications, Inc. | Frequency compensation of common-mode feedback loops for differential amplifiers |
| CN2906714Y (en) * | 2005-06-30 | 2007-05-30 | 凹凸科技（中国）有限公司 | Low pressure drop voltage regulator with common mode negative feedback |
-
2005
- 2005-06-30 CN CNB2005100801547A patent/CN100437415C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411394A (en) * | 2011-11-10 | 2012-04-11 | 昌芯(西安)集成电路科技有限责任公司 | Linear voltage stabilizer with low pressure differential and Sink and Source current capabilities |
| CN102411394B (en) * | 2011-11-10 | 2014-04-23 | 昌芯(西安)集成电路科技有限责任公司 | Linear voltage stabilizer with low pressure differential and Sink and Source current capabilities |
| CN104635824A (en) * | 2013-11-14 | 2015-05-20 | 台湾积体电路制造股份有限公司 | Low dropout regulator and related method |
| CN105634521A (en) * | 2014-11-26 | 2016-06-01 | 成都振芯科技股份有限公司 | MLVDS receiving circuit |
| CN105634521B (en) * | 2014-11-26 | 2018-01-23 | 成都振芯科技股份有限公司 | A kind of MLVDS receiving circuits |
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| CN100437415C (en) | 2008-11-26 |
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