CN1197947A - Constant-voltage circuit capable of preventing overshoot at circuit output terminal - Google Patents
Constant-voltage circuit capable of preventing overshoot at circuit output terminal Download PDFInfo
- Publication number
- CN1197947A CN1197947A CN98105985A CN98105985A CN1197947A CN 1197947 A CN1197947 A CN 1197947A CN 98105985 A CN98105985 A CN 98105985A CN 98105985 A CN98105985 A CN 98105985A CN 1197947 A CN1197947 A CN 1197947A
- Authority
- CN
- China
- Prior art keywords
- voltage
- nmos pass
- circuit
- pass transistor
- added
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Power Engineering (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Control Of Electrical Variables (AREA)
Abstract
A constant-voltage circuit has a differential amplifier circuit and an output stage circuit. The differential amplifier circuit is supplied with a predetermined reference voltage and produces an amplifier voltage in accordance with the predetermined reference voltage. The output stage circuit has a circuit output terminal and outputs an output voltage from the circuit output terminal in response to the amplifier voltage. The constant-voltage circuit further comprises an overshoot preventing section and a supplying section. The supplying section supplies a control signal to the overshoot preventing section when the source voltage is supplied to the constant-voltage circuit. The overshoot preventing section prevents the overshoot at the circuit output terminal in response to the control signal to control the output voltage to the predetermined constant voltage.
Description
The present invention relates to constant voltage circuit, particularly do not have spike to occur and make the constant voltage circuit of output voltage stabilization at circuit output end.
Constant voltage circuit is used to obtain the constant voltage as output voltage.Conventional constant voltage circuit is made up of with the output-stage circuit that links to each other with differential amplifier circuit differential amplifier circuit, and sort circuit is called the first conventional constant voltage circuit.Output-stage circuit further links to each other with the output load circuit of circuit output end.When differential amplifying circuit was added with reference voltage, then output-stage circuit output became the output voltage of constant voltage.As will be described, spike appears in circuit output end in the first conventional constant voltage circuit inevitably.Therefore, in the first conventional constant voltage circuit, be difficult to make output voltage stabilization.
In addition, be known among the Japanese kokai publication sho 64-29915 (29915/1989) and disclose a kind of constant voltage circuit, sort circuit is called the second conventional constant voltage circuit.
And, being known among the Japanese kokai publication hei 1-314319 (314319/1989) and disclosing constant voltage circuit, sort circuit is called the 3rd conventional constant voltage circuit.
Just as will be described, also all spike can appear in the second and the 3rd conventional constant voltage circuit.Therefore, be difficult to make the output voltage stabilization of the second and the 3rd conventional constant voltage circuit.
The purpose of this invention is to provide one does not have spike to occur at circuit output end, and makes the constant voltage circuit of output voltage stabilization.
It is very clear that other purpose of the present invention will become when being described.
The invention provides a kind of constant voltage circuit, this circuit is made up of the differential multiplying arrangement, output unit and the restraining device that are added with predetermined reference voltage, this differential amplifier circuit device is used for producing amplification voltage according to predetermined reference voltage, this output unit has circuit output end, and this output terminal is used for according to the voltage that amplifies and output voltage.Restraining device is used for being suppressed at circuit output end and spike occurring when source voltage is added in constant voltage circuit, output voltage is controlled to be predetermined stable voltage.
Fig. 1 is the circuit diagram of the first conventional constant voltage circuit;
Fig. 2 is the circuit diagram of the second conventional constant voltage circuit;
Fig. 3 is the circuit diagram of the 3rd conventional constant voltage circuit;
Fig. 4 is the circuit diagram of the constant voltage circuit of first embodiment of the invention;
Fig. 5 is the circuit diagram of the constant voltage circuit of second embodiment of the invention;
Fig. 6 is the circuit diagram of the constant voltage circuit of third embodiment of the invention;
Fig. 7 is the circuit diagram of the constant voltage circuit of fourth embodiment of the invention;
Fig. 8 is the circuit diagram of the constant voltage circuit of fifth embodiment of the invention;
Fig. 9 is the circuit diagram of the constant voltage circuit of sixth embodiment of the invention;
Figure 10 is the circuit diagram of the constant voltage circuit of seventh embodiment of the invention.
Referring to Fig. 1,, the first conventional constant voltage circuit 10 is described at first for ease of understanding the present invention.The first conventional constant voltage circuit 10 is made up of with the output-stage circuit 2 that is connected with differential amplifier circuit 1 differential amplifier circuit 1.In the example of describing, output-stage circuit 2 is connected with output load circuit 3.
Differential amplifier circuit 1 is made up of the constant flow element of first to the 8th metal-oxide semiconductor (MOS) (MOS) the transistor Tr 1-Tr8 and the constant current I1 that flows through.For simplicity, constant flow element is represented with label I1.Differential amplifier circuit 1 has the circuit input end Ti that is added with reference voltage V REF.And differential amplifier circuit 1 adds active voltage vcc.
Output-stage circuit 2 is made up of P-channel metal-oxide-semiconductor (PMOS) transistor Tr 9, first resistor, second resistor and capacitor.First resistor and second resistor have first resistance R 1 and second resistance R 2 respectively.Capacitor has capacitor C 1.For simplicity, first and second resistors are represented with label R1 and R2 respectively.Capacitor is represented with label C1.Output-stage circuit 2 has circuit output end To, from the VREG output voltage of this output terminal output as constant voltage.Output-stage circuit 2 adds active voltage vcc.
In the example of describing, output load circuit 3 is made up of loading resistor and load capacitor.Loading resistor and load capacitor have pull-up resistor RL and load capacitance CL respectively, and for simplicity, loading resistor and load capacitor are represented with label RL and CL.
Differential amplifier circuit 1 work is to suppress output current.When output voltage was not less than the voltage of steady state (SS), owing to feedback voltage on the grid that is added to PMOS transistor Tr 9 postpones, differential amplifier circuit 1 was difficult to suppress output current.As a result, on the basis of output current, there is spike to appear at output terminal To.Output current is through first resistor R 1 and second resistor R 2 the earth of flowing through.Output voltage reaches the voltage of steady state (SS).
In the first conventional constant voltage circuit, just after the source voltage vcc was added on the constant voltage circuit, PMOS transistor Tr 9 had the grid potential that equates with ground potential.As a result, PMOS transistor Tr 9 can be circuit output end To bigger electric current is provided.On the other hand, differential amplifier circuit 1 has less circuital current.Like this, differential amplifier circuit 1 is difficult to suppress the electric current of PMOS transistor Tr 9.As mentioned above, there is spike to occur at circuit output end To.
In addition, each of a R1 and second resistance R 2 is all bigger.Like this, when when spike appears in circuit output end To, need long time to make output voltage reach the voltage of * (converge) steady state (SS) at interval.
Referring to Fig. 2, be described with regard to the second conventional constant voltage circuit now.Constant voltage circuit shown in the figure is made up of to Tr31, circuit capacitor, voltage comparator circuit COMP, diode D21 and first to the 4th resistor first to the 3rd constant current source, the first and second PNP transistor Tr 21 and Tr22, first to the 9th NPN transistor Tr23.Constant voltage circuit is that the load capacitance of C22 is connected with having capacitance.
First to the 3rd constant current source produces constant current I21 respectively to I23.For simplicity, first to the 3rd constant current source is represented to I23 with label I21.Equally, circuit capacitor has capacitor C 21, and represents with label C21.First to the 4th resistor has first to the 4th resistance R 21 to R24 respectively.For simplicity, first to the 4th resistor is represented to R24 with label R21 respectively.In addition, load capacitor is represented with label C22.
In the example of describing, load capacitor C22 is added with from the next output voltage V o of constant voltage circuit.In the second conventional constant voltage circuit, just after the source voltage vcc was added on the constant voltage circuit, output voltage V o equaled ground potential.As a result, the small initial current constant voltage circuit of flowing through.On the basis of this small initial circuit electric current, output voltage V o slowly rises, so need reach constant voltage for a long time.In order to address the above problem, constant voltage circuit is made up of to Tr31 the 6th to the 9th transistor Tr 28.To Tr31, output voltage V o rises rapidly by the 6th to the 9th NPN transistor Tr28, reaches the predetermined voltage that equates with constant voltage at interval so only require a very short time.
Yet, when transistors all in the second conventional constant voltage circuit is MOS transistor, just after the source voltage vcc is added on the constant voltage circuit, have spike to occur at the output terminal of constant voltage circuit.
Referring to Fig. 3, be described with regard to the 3rd conventional constant voltage circuit.The 3rd conventional constant voltage circuit is structurally different with the second conventional constant voltage circuit shown in Fig. 2.The 3rd conventional constant voltage circuit comprises and the identical part of the second conventional constant voltage circuit that this part is denoted by the same reference numerals.The 3rd conventional constant voltage circuit does not have working voltage comparator circuit COMP and the 4th resistor R 24, and it comprises the tenth NPN transistor Tr32 and diode D22.In the example that illustrates, load capacitor C22 is added with from what constant voltage circuit was come voltage Vo is shown.In the 3rd conventional constant voltage circuit, after the source voltage vcc was added on the constant voltage circuit, output voltage V o equaled ground potential just.As a result, the small initial circuit electric current constant voltage circuit of flowing through.On the basis of this small initial circuit electric current, output voltage V o slowly rises, so need reach constant voltage for a long time.In order to address the above problem, constant voltage circuit comprises that the 6th to the 9th NPN transistor Tr28 is to Tr31.To Tr31, output voltage V o rises rapidly by the 6th to the 9th NPN transistor Tr28, reaches the predetermined voltage that equates with constant voltage at interval so only require a very short time.
Yet, when transistors all in the 3rd conventional constant voltage circuit is MOS transistor, just after the source voltage vcc is added on the constant voltage circuit, have spike to occur at the output terminal of constant voltage circuit.
Referring to Fig. 4, the constant voltage circuit of the first embodiment of the present invention will be described now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit shown in Fig. 1, and this circuit is represented with other label 20 like this.Constant voltage circuit includes the part identical with constant voltage circuit shown in Figure 1, and this part is denoted by the same reference numerals.This constant voltage circuit 20 comprises differential amplifier circuit 1 and the output-stage circuit 2 that is connected with output load circuit 3.This constant voltage circuit 20 further comprises charging and discharge circuit 4.This charging and discharge circuit 4 is that the additional resistor of R4 is connected with circuit output end To through nmos pass transistor Tr10 and resistance value.For simplicity, Fu Jia resistor is represented with label R4.
Especially, charging and discharge circuit 4 are made up of elementary * (primary) resistor and the primary condenser that are one another in series.Elementary resistor and primary condenser have elementary resistance R3 and elementary electric capacity C2 respectively.For simplicity, this elementary resistor and primary condenser are represented with label R3 and C2.Elementary resistor R3 is connected with ground.Primary condenser C2 is connected with the source voltage vcc.The grid of nmos pass transistor Tr10 is received on the tie point between elementary resistor R3 and the primary condenser C2
Constant voltage circuit 20 shown in the figure as contrast Fig. 1 describe as negative feedback amplifier circuit.Especially, differential amplifier circuit 1 is controlled the 6th MOS transistor Tr6 as voltage follower circuit according to the variation of output voltage, then the 6th MOS transistor Tr6 have with from circuit input end Ti input the grid potential that equates of reference voltage V REF.As a result, PMOS transistor Tr 9 makes output voltage V REG obtain by VREF * (R1+R2)/R2.Ground current flows to the earth through additional resistor R 4 and nmos pass transistor Tr10.Just as described later, the size of ground current is controlled by control voltage, and this control voltage is added in the grid of nmos pass transistor Tr10 from charging and discharge circuit 4.When the source voltage vcc was added on the constant voltage circuit 20, because PMOS transistor Tr 9 has the grid potential that equates with ground potential, PMOS transistor Tr 9 became conducting state.As a result, output current flows to circuit output end To by PMOS transistor Tr 9.
Just after constant voltage circuit 20 started, the grid potential of PMOS transistor Tr 9 equaled ground potential.Like this, PMOS transistor Tr 9 becomes conducting state.Output current flows to output terminal To by PMOS transistor Tr 9.Because output current continues to flow to output terminal To, be suppressed by differential amplifier circuit 1 up to the electric current of PMOS transistor Tr 9, so the spike of output current occurs at output terminal.In order to stop the appearance of spike, constant voltage circuit 20 has charging and discharge circuit 4.Especially, elementary electric capacity C2 makes the grid potential of nmos pass transistor Tr1O become the source voltage vcc.In other words, charge and discharge circuit 4 provides the control that equates with source voltage vcc voltage for the grid of nmos pass transistor Tr10.As a result, nmos pass transistor Tr10 becomes conducting state.Electric charge is discharged into the earth by additional resistor R 4 and nmos pass transistor Tr10.Output voltage becomes the voltage of steady state (SS) after the short time interval.This short time interval is determined by additional resistor R 4.This charging and discharge circuit 4 have the time constant of being determined by primary condenser C2 and elementary resistor R3.This time constant was set up according to the short time interval.In the example shown in the figure, this time constant equals this short time interval.Like this, after the less time interval, control voltage becomes the voltage more less than source voltage vcc.When control voltage became than the less voltage of source voltage vcc, nmos pass transistor Tr10 became nonconducting state.Because the grid potential of nmos pass transistor Tr10 descends gradually according to the time constant of being determined by primary condenser C2 and elementary resistor R3 above-mentioned.Output voltage is transformed into the voltage of steady state (SS) reposefully, and does not have to produce noise because of the conversion of nmos pass transistor Tr10.
Referring to Fig. 5, the constant voltage circuit of the second embodiment of the present invention is described now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit 20 shown in Fig. 4, and this circuit is represented with other label 30 like this.Constant voltage circuit 30 comprises identical part, and this part is denoted by the same reference numerals.This constant voltage circuit 30 comprises nmos pass transistor Tr11, and does not have nmos pass transistor Tr10 shown in Fig. 4 and additional resistor R 4.This charging is connected with the grid of discharge circuit 4 with nmos pass transistor Tr11.As shown in Figure 5, the drain electrode of nmos pass transistor Tr11 (chain) is connected with Tr6 with the 6th MOS transistor Tr4 with the 4th.Nmos pass transistor Tr11 source ground.
Fig. 4 is described as contrast, and the constant voltage circuit 30 shown in the figure is as negative feedback amplifier circuit.Especially, differential amplifier circuit 1 is as voltage follower circuit.This differential amplifier circuit 1 is controlled the 6th MOS transistor Tr6 according to the variation of output voltage, so the 6th MOS transistor Tr6 has the grid potential that equates with the reference voltage V REF that imports from circuit input end Ti.As a result, PMOS transistor Tr 9 can make output voltage V REG obtain by VREF * (R1+R2)/R2.
Just after constant voltage circuit 20 started, primary condenser C2 made the grid potential of nmos pass transistor Tr11 become the source voltage vcc.In other words, charging and discharge circuit 4 provide the control that equates with source voltage vcc voltage for the grid of nmos pass transistor Tr11.As a result, nmos pass transistor Tr11 becomes conducting state.When nmos pass transistor Tr11 became conducting state, the circuital current in the differential amplifier circuit 1 increased.When the circuital current in the differential amplifying circuit 1 increased, PMOS transistor Tr 9 became conducting state rapidly, so output voltage becomes the voltage of steady state (SS).In other words, behind the interval of very short time, output voltage becomes the voltage under the steady state (SS).
As in conjunction with described in Fig. 4, the time constant of charging and discharge circuit 4 is according to short time interval foundation.In the example of describing, time constant equals the short time interval.Control voltage becomes the voltage more less than source voltage vcc after the short time interval.Like this, when control voltage became than the less voltage of source voltage vcc, nmos pass transistor became nonconducting state.Because the grid potential of nmos pass transistor Tr11 descends gradually according to the time constant by primary condenser C2 and elementary resistor R3 decision, output voltage is transformed into the voltage under the steady state (SS) reposefully, and the noise that does not exist the switch because of nmos pass transistor Tr10 to produce.
Referring to Fig. 6, be described the constant voltage circuit of the third embodiment of the present invention now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit 20 shown in Fig. 4, and this circuit is represented with other label 40 like this.Constant voltage circuit 40 comprises the identical part that is denoted by the same reference numerals.This constant voltage circuit 40 comprises PMOS transistor Tr 12, and does not have the nmos pass transistor Tr10 shown in Fig. 4.This charging is connected with the grid of discharge circuit 4 with PMOS transistor Tr 12.The drain electrode of PMOS transistor Tr 12 is connected with the source electrode of PMOS transistor Tr 9.The source electrode of PMOS transistor Tr 9 is connected with power supply.
Constant voltage circuit 40 output shown in the figure is as in conjunction with the described output voltage of Fig. 4.
Just after constant voltage circuit 40 started, primary condenser C2 made the grid potential of PMOS transistor Tr 12 become the source voltage vcc.In other words, charging and discharge circuit 4 provide the control that equates with source voltage vcc voltage for the grid of PMOS transistor Tr 12.As a result, PMOS transistor Tr 12 becomes conducting state.When PMOS transistor Tr 12 became conducting state, the electric current of PMOS transistor Tr 9 was suppressed.Suppressed to appear at the spike of circuit output end To.After the short time interval, output voltage becomes the voltage under the steady state (SS).The unloading factor * (dumping factor) of circuit output end To is optimized on the basis of strength of current, and this strength of current is controlled by PMOS transistor Tr 12 with by the time constant that primary condenser C2 and elementary resistor R3 determine.The result, because the grid potential of nmos pass transistor Tr11 descends gradually according to the time constant of being determined by primary condenser C2 and elementary resistor R3, output voltage is transformed into the voltage under the steady state (SS) reposefully, and the noise of the switch of nmos pass transistor Tr10 do not occur resulting from.
Referring to Fig. 7, be described the constant voltage circuit of the fourth embodiment of the present invention now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit 20 shown in Fig. 4, and this circuit is represented with other label 50 like this.Constant voltage circuit 50 comprises the identical part that is denoted by the same reference numerals.This constant voltage circuit 50 also comprises the nmos pass transistor Tr11 shown in Fig. 5.
Just after constant voltage circuit 50 started, primary condenser C2 made the grid potential of nmos pass transistor Tr10 become the source voltage vcc.Equally, primary condenser C2 makes the grid potential of nmos pass transistor Tr11 become the source voltage vcc.In other words, charging and discharge circuit 4 provide the control that equates with source voltage vcc voltage for the grid of nmos pass transistor Tr10 and Tr11.As a result, nmos pass transistor Tr10 becomes conducting state.Electric charge is discharged into ground by additional resistor R 4 and nmos pass transistor Tr10.Nmos pass transistor Tr11 becomes conducting state.When nmos pass transistor Tr11 became conducting state, the electric current in the differential amplifier circuit 1 increased.When the electric current in the differential amplifying circuit 1 increased, PMOS transistor Tr 9 became conducting state rapidly.Like this, output voltage is at the voltage that promptly becomes under the cooperation of nmos pass transistor Tr10 and Tr11 under the steady state (SS).
Referring to Fig. 8, be described the constant voltage circuit of the fifth embodiment of the present invention now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit 20 shown in Fig. 4, and this circuit is represented with other label 60 like this.Constant voltage circuit 60 comprises the identical part that is denoted by the same reference numerals.This constant voltage circuit 60 also comprises PMOS transistor Tr 12.Charging is connected with the grid of discharge circuit 4 with PMOS transistor Tr 12.The drain electrode of PMOS transistor Tr 12 is connected with the source electrode of PMOS transistor Tr 9.The source electrode of PMOS transistor Tr 12 adds active voltage vcc.
Constant voltage circuit 60 output shown in the figure is as in conjunction with the described output voltage of Fig. 4.
Just after constant voltage circuit 60 started, primary condenser C2 made the grid potential of nmos pass transistor Tr10 become the source voltage vcc.Equally, primary condenser C2 makes the grid potential of PMOS transistor Tr 12 become the source voltage vcc.In other words, charging and discharge circuit 4 provide the control that equates with source voltage vcc voltage for the grid of nmos pass transistor Tr10 and PMOS transistor Tr 12.As a result, nmos pass transistor Tr10 and PMOS transistor Tr 12 all become conducting state.
When nmos pass transistor Tr10 became conducting state, electric charge was discharged into ground by additional resistor R 4 and nmos pass transistor Tr10.When PMOS transistor Tr 12 becomes conducting state, suppress the electric current of PMOS transistor Tr 9.Like this, suppressed to appear at the spike of circuit output end To.Under the cooperation of nmos pass transistor Tr10 and PMOS transistor Tr 12, after the very short time interval, output voltage becomes the voltage under the steady state (SS).
Referring to Fig. 9, be described the constant voltage circuit of the sixth embodiment of the present invention now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit 30 shown in Fig. 5, and this circuit is represented with other label 70 like this.Constant voltage circuit 70 comprises the identical part that is denoted by the same reference numerals.This constant voltage circuit 70 also comprises PMOS transistor Tr 12.
Charging is connected with the grid of discharge circuit 4 with PMOS transistor Tr 12.The drain electrode of PMOS transistor Tr 12 is connected with the source electrode of PMOS transistor Tr 9.The source electrode of PMOS transistor Tr 12 adds active voltage vcc.
Just after constant voltage circuit 70 started, primary condenser C2 made the grid potential of nmos pass transistor Tr11 become the source voltage vcc.Equally, primary condenser C2 makes the grid potential of PMOS transistor Tr 12 become the source voltage vcc.In other words, charging and discharge circuit 4 provide the control that equates with source voltage vcc voltage for the grid of nmos pass transistor Tr11 and PMOS transistor Tr 12.As a result, nmos pass transistor Tr11 and PMOS transistor Tr 12 all become conducting state.
When nmos pass transistor Tr11 became conducting state, the electric current in the differential amplifier circuit 1 increased.When the electric current in the differential amplifying circuit 1 increased, PMOS transistor Tr 9 became conducting state rapidly.On the other hand, when PMOS transistor Tr 12 becomes conducting state, suppress the electric current of PMOS transistor Tr 9.Like this, suppressed to appear at the spike of circuit output end To.Under the cooperation of nmos pass transistor Tr11 and PMOS transistor Tr 12, after the very short time interval, output voltage becomes the voltage under the steady state (SS).
Referring to Figure 10, the constant voltage circuit of the seventh embodiment of the present invention is described now.Constant voltage circuit shown in the figure is structurally different with the constant voltage circuit 20 shown in Fig. 4, and this circuit is represented with other label 80 like this.Constant voltage circuit 80 comprises identical part, and this part is denoted by the same reference numerals.This constant voltage circuit 80 also comprises nmos pass transistor Tr11 and PMOS transistor Tr 12.
Charging is connected with the grid of discharge circuit 4 with nmos pass transistor Tr11.The drain electrode of nmos pass transistor Tr11 is connected with Tr6 with the 6th MOS transistor Tr4 with the 4th.Charging is connected with the grid of discharge circuit 4 with PMOS transistor Tr 12.The drain electrode of PMOS transistor Tr 12 is connected with PMOS transistor Tr 9 source electrodes.PMOS transistor Tr 12 adds active voltage vcc.
Constant voltage circuit 80 output shown in the figure is as in conjunction with the described output voltage of Fig. 4.
Just after constant voltage circuit 80 started, primary condenser C2 made the grid potential of nmos pass transistor Tr10 become the source voltage vcc.Equally, primary condenser C2 makes the grid potential of nmos pass transistor Tr11 become the source voltage vcc.Primary condenser C2 makes the grid potential of PMOS transistor Tr 12 become the source voltage vcc.In other words, charging and discharge circuit 4 provide the control that equates with source voltage vcc voltage for the grid of nmos pass transistor Tr10, Tr11 and PMOS transistor Tr 12.As a result, nmos pass transistor Tr10, Tr11 and PMOS transistor Tr 12 all become conducting state.
When nmos pass transistor Tr10 became conducting state, electric charge was discharged into ground from circuit output end To through additional resistor R 4 and nmos pass transistor Tr10.When nmos pass transistor Tr11 became conducting state, the electric current in the differential amplifier circuit 1 increased.When the electric current in the differential amplifying circuit 1 increased, PMOS transistor Tr 9 became conducting state rapidly.On the other hand, when PMOS transistor Tr 12 becomes conducting state, suppressed the electric current in the PMOS transistor Tr 9.Like this, suppressed to appear at the spike of circuit output end To.Under nmos pass transistor Tr10, Tr11 and 12 cooperations of PMOS transistor Tr, after the very short time interval, output voltage becomes the voltage under the steady state (SS).
After in conjunction with the preferred embodiments the present invention being described in detail, those ordinary skill in the art personnel are easy to and can be committed to practice to the present invention in every way.
Claims (10)
1. a constant voltage circuit comprises differential multiplying arrangement, output unit and restraining device;
Described differential multiplying arrangement is added with predetermined reference voltage, amplifies voltage to produce according to described predetermined reference voltage;
Described output unit has circuit output end, to respond described amplification voltage from output voltage of described circuit output end output; And
Described restraining device is suppressed at described circuit output end and spike occurs, when source voltage is added to described constant voltage circuit, to control described output voltage at predetermined constant voltage.
2. constant voltage circuit according to claim 1 is characterized in that: described restraining device comprises spike restraining device and feedway;
Described spike restraining device responsive control signal suppresses the appearance of described spike, thereby controls the voltage of described output voltage in described predetermined constant; And
Described feedway is providing described control signal to described spike restraining device when described source voltage is added in described constant voltage circuit.
3. constant-voltage equipment according to claim 2 is characterized in that: described feedway comprises the elementary resistor and the primary condenser of ground connection;
Described primary condenser is connected in series on the described elementary resistor and is added with described source voltage at tie point;
Described control signal is added on the described spike restraining device from described tie point as control voltage.
4. constant voltage circuit according to claim 3 is characterized in that: described spike restraining device comprises booster resistor and nmos pass transistor;
Described booster resistor is connected on the described circuit output end; And
Described nmos pass transistor is connected on the described booster resistor and ground connection, and the grid of described nmos pass transistor is connected on the described tie point and is added with described control voltage.
5. constant-voltage equipment according to claim 3 is characterized in that: the spike restraining device comprises nmos pass transistor;
The drain electrode of described nmos pass transistor is connected on the described differential multiplying arrangement, and the source ground of described nmos pass transistor, the grid of described nmos pass transistor are connected on the described tie point to be added with described control voltage.
6. constant voltage circuit according to claim 3 is characterized in that: described spike restraining device comprises the PMOS transistor;
The transistorized source electrode of described PMOS is added with described source voltage, and described PMOS transistor drain is connected to described output unit, and the transistorized grid of described PMOS is connected on the described tie point and is added with described control voltage.
7. constant voltage circuit according to claim 3 is characterized in that: described spike restraining device comprises booster resistor, first nmos pass transistor and second nmos pass transistor;
Described booster resistor is connected to described circuit output end;
Described first nmos pass transistor is connected to described additional resistor and ground connection, and the grid of described first nmos pass transistor is connected to described tie point, is added with described control voltage on the described tie point; And
The drain electrode of described second nmos pass transistor is connected on the described differential multiplying arrangement, and the source ground of described second nmos pass transistor, the grid of described second nmos pass transistor are connected to and are added with described control voltage on the described tie point.
8. constant voltage circuit according to claim 3 is characterized in that: described spike restraining device comprises additional resistor, nmos pass transistor and PMOS transistor;
Described additional resistor is connected on the described circuit output end;
Described nmos pass transistor is connected with described additional resistor and ground connection, and the grid of described nmos pass transistor is connected with described tie point and is added with described control voltage; And
The transistorized source electrode of described PMOS is added with described source voltage, and drain electrode connects described output unit, and the transistorized grid of described PMOS connects described tie point and is added with described control voltage.
9. constant voltage circuit according to claim 3.It is characterized in that: described spike restraining device comprises a nmos pass transistor and a PMOS transistor;
The drain electrode of described nmos pass transistor is connected with described differential multiplying arrangement, and the source ground of described nmos pass transistor, the grid of described nmos pass transistor connect described tie point and be added with described control voltage; And
The transistorized source electrode of described PMOS is added with described source voltage, and its drain electrode connects described output unit, and the transistorized grid of described PMOS connects described tie point and is added with described control voltage.
10. constant-voltage equipment according to claim 3 is characterized in that: described spike restraining device comprises booster resistor, first nmos pass transistor, second nmos pass transistor and described PMOS transistor;
Described booster resistor is connected with described circuit output end;
Described first nmos pass transistor is connected with described booster resistor and ground connection, and the grid of described first nmos pass transistor connects described tie point and is added with described control voltage;
The drain electrode of described second nmos pass transistor connects described differential multiplying arrangement, and the source ground of described second nmos pass transistor, the grid of described second nmos pass transistor connect described tie point and be added with described control voltage; And
The transistorized source electrode of described PMOS is added with described source voltage, and its drain electrode is connected with described output unit, and the transistorized grid of described PMOS connects described tie point and is added with control voltage.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16782/97 | 1997-01-30 | ||
| JP9016782A JP3068482B2 (en) | 1997-01-30 | 1997-01-30 | Constant voltage circuit |
| JP16782/1997 | 1997-01-30 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1197947A true CN1197947A (en) | 1998-11-04 |
| CN1119733C CN1119733C (en) | 2003-08-27 |
Family
ID=11925768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98105985A Expired - Fee Related CN1119733C (en) | 1997-01-30 | 1998-01-27 | Constant-voltage circuit capable of preventing overshoot at circuit output terminal |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5920185A (en) |
| JP (1) | JP3068482B2 (en) |
| KR (1) | KR100292898B1 (en) |
| CN (1) | CN1119733C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107229301A (en) * | 2016-03-23 | 2017-10-03 | 精工半导体有限公司 | Voltage regulator |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000155620A (en) * | 1998-11-20 | 2000-06-06 | Mitsubishi Electric Corp | Reference voltage generation circuit |
| GB2356267B (en) * | 1999-11-10 | 2003-08-13 | Fujitsu Ltd | Reference voltage generating circuitry |
| JP2002108468A (en) * | 2000-09-28 | 2002-04-10 | Toshiba Corp | Current source circuit |
| JP3874247B2 (en) * | 2001-12-25 | 2007-01-31 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit device |
| JP4122910B2 (en) * | 2002-09-24 | 2008-07-23 | ミツミ電機株式会社 | Power supply circuit |
| US6894473B1 (en) * | 2003-03-05 | 2005-05-17 | Advanced Micro Devices, Inc. | Fast bandgap reference circuit for use in a low power supply A/D booster |
| JP4212036B2 (en) * | 2003-06-19 | 2009-01-21 | ローム株式会社 | Constant voltage generator |
| JP2005122574A (en) | 2003-10-17 | 2005-05-12 | Renesas Technology Corp | Semiconductor integrated circuit |
| JP2006127225A (en) * | 2004-10-29 | 2006-05-18 | Torex Device Co Ltd | Power circuit |
| JP2007094970A (en) | 2005-09-30 | 2007-04-12 | Toko Inc | Voltage supply circuit |
| JP4819514B2 (en) * | 2006-01-26 | 2011-11-24 | 株式会社ニューフレアテクノロジー | DAC settling characteristic evaluation method, DAC settling characteristic evaluation apparatus, and electron beam drawing apparatus |
| JP2007316811A (en) * | 2006-05-24 | 2007-12-06 | Fujitsu Ten Ltd | Dc power unit |
| KR100780209B1 (en) | 2006-05-26 | 2007-11-27 | 삼성전기주식회사 | Voltage regulating apparatus |
| JP5085200B2 (en) * | 2007-06-15 | 2012-11-28 | ラピスセミコンダクタ株式会社 | Regulator circuit |
| JP2009003764A (en) * | 2007-06-22 | 2009-01-08 | Seiko Epson Corp | Semiconductor integrated circuit and electronic equipment |
| JP5280176B2 (en) | 2008-12-11 | 2013-09-04 | ルネサスエレクトロニクス株式会社 | Voltage regulator |
| KR101039878B1 (en) * | 2009-05-11 | 2011-06-09 | 주식회사 하이닉스반도체 | Voltage generating circuit |
| JP5434248B2 (en) * | 2009-05-12 | 2014-03-05 | ミツミ電機株式会社 | Regulator circuit |
| CN101951003B (en) * | 2010-09-29 | 2012-12-19 | 无锡中星微电子有限公司 | Charging management device |
| US10784917B2 (en) * | 2018-11-27 | 2020-09-22 | Texas Instruments Incorporated | PSI5 base current sampling in synchronous mode |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US29619A (en) * | 1860-08-14 | Mode of marking stock | ||
| JPS6429915A (en) * | 1987-07-24 | 1989-01-31 | Canon Kk | Constant voltage circuit |
| JPH01314319A (en) * | 1988-06-14 | 1989-12-19 | Canon Inc | Constant voltage circuit |
| DE3904910A1 (en) * | 1989-02-17 | 1990-08-23 | Texas Instruments Deutschland | INTEGRATED PULL-OUT LEVEL |
| US5559424A (en) * | 1994-10-20 | 1996-09-24 | Siliconix Incorporated | Voltage regulator having improved stability |
| DE19609971A1 (en) * | 1996-03-14 | 1997-09-18 | Philips Patentverwaltung | Regulated supply voltage source |
-
1997
- 1997-01-30 JP JP9016782A patent/JP3068482B2/en not_active Expired - Fee Related
-
1998
- 1998-01-23 KR KR1019980002137A patent/KR100292898B1/en not_active IP Right Cessation
- 1998-01-27 CN CN98105985A patent/CN1119733C/en not_active Expired - Fee Related
- 1998-01-29 US US09/015,532 patent/US5920185A/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107229301A (en) * | 2016-03-23 | 2017-10-03 | 精工半导体有限公司 | Voltage regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| US5920185A (en) | 1999-07-06 |
| CN1119733C (en) | 2003-08-27 |
| JP3068482B2 (en) | 2000-07-24 |
| KR19980070800A (en) | 1998-10-26 |
| KR100292898B1 (en) | 2001-06-15 |
| JPH10214121A (en) | 1998-08-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1119733C (en) | Constant-voltage circuit capable of preventing overshoot at circuit output terminal | |
| US6794940B2 (en) | Operational amplifier circuit | |
| CN1294692C (en) | Voltage step down circuit, power source circuit ands emiconductor integrated circuit | |
| CN1497405A (en) | Voltag regulator | |
| CN1252927C (en) | Semiconductor integrated circuit | |
| EP0321226A1 (en) | Intermediate potential generation circuit for generating a potential intermediate between a power source potential and ground potential | |
| CN1395310A (en) | Internal power supply for IC with temp. compensating pedestal generator | |
| CN1728520A (en) | Power supply controller and method | |
| CN1702729A (en) | Drive circuit, operation state detection circuit, and display device | |
| CN1141587C (en) | Current sensing circuit | |
| CN1165427A (en) | Operational amplification circuit | |
| US7202647B2 (en) | Power supply circuit | |
| CN1696861A (en) | Constant voltage outputting circuit | |
| CN1114262C (en) | Emitter follower circuit having no temperature dependency | |
| CN1573637A (en) | Power supply circuit | |
| US6498517B2 (en) | Peak hold circuit | |
| CN1081841C (en) | Constant current circuit with small output current fluctuation | |
| CN1107374C (en) | Integrated circuit and method for generating transimpedance function | |
| CN114895743B (en) | Low starting current circuit for dynamic bias current LDO | |
| CN1167188C (en) | Amplifier | |
| EP1091485A1 (en) | Input stage for buffer with negative feedback | |
| CN111130318B (en) | Switching power supply control circuit and method thereof | |
| CN1244067A (en) | Shunt regulatable push-pull circuit with wide frequency range | |
| CN111934653A (en) | Voltage mode PWM modulation feedforward circuit | |
| CN1048123C (en) | Cicuit of voltage limiter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030321 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20030321 Address after: Kawasaki, Kanagawa, Japan Applicant after: NEC Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: RENESAS KANSAI CO., LTD. Free format text: FORMER NAME: NEC CORP. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: Kawasaki, Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Kawasaki, Kanagawa, Japan Patentee before: NEC Corp. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030827 Termination date: 20140127 |