CN1885742A - Hardware terminal of cognitive radio experiment system - Google Patents
Hardware terminal of cognitive radio experiment system Download PDFInfo
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- CN1885742A CN1885742A CN 200610043027 CN200610043027A CN1885742A CN 1885742 A CN1885742 A CN 1885742A CN 200610043027 CN200610043027 CN 200610043027 CN 200610043027 A CN200610043027 A CN 200610043027A CN 1885742 A CN1885742 A CN 1885742A
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Abstract
The disclosed hardware terminal comprises: one PCB as sending channel and power module, and another PCB as the receiving channel and power module, wherein the first/second base-band process module with input connected to a PC/signal output to a PC, a first/second MF process module, and a first/second RF process module with output/input connected the sending antenna/receiving antenna. This invention realizes the CR experimental system.
Description
Technical field
The present invention relates to a kind of experimental system of cognition wireless telecommunication, particularly a kind of hardware terminal of verifying cognitive radio experiment system.
Background technology
In order to alleviate the contradiction between the low and ever-increasing frequency spectrum resource demand of the current availability of frequency spectrum, academia has proposed the notion of CR (Cognitive Radio, cognitive radio).Cognitive radio realizes that by frequency spectrum environment such as perceived frequency, time and spatial domains frequency spectrum is dynamically shared, and spectrum utilization flexibly is provided, and utilizes the frequency spectrum that leaves unused to carry out the signal transmission, to satisfy commerce, military, the continuous demand that changes of government guest.The research of CR at present is at the early-stage, and a lot of viewpoints are also ununified, even dispute is very big, and for example authorized user is suspected the reliability of CR user's frequency spectrum detection, worries that communication reliability is subjected to CR user's threat; The various frequency spectrum detecting methods that propose at present the system in reality of often the having no chance checking of getting on the other hand.Therefore, a concrete experimental system can well illustrate and verify the problems of CR, can accumulate experience, provide reference to the establishment of CR Study on Theory and standard.But present domestic a kind of CR experimental system that also do not have, abroad also not seeing has similarly open report.
Summary of the invention
The objective of the invention is provides experiment support for the research of CR, and a kind of hardware terminal of CR experimental system is provided.
For reaching above purpose, the present invention takes following technical scheme to be achieved:
A kind of hardware terminal of cognitive radio experiment system, it is characterized in that, this terminal comprises two PCB (printed circuit board (PCB)): sendaisle is arranged and to the sendaisle power module of sendaisle power supply on first PCB, receive path is arranged and to the receive path power module of receive path power supply on second PCB; Described sendaisle comprises first baseband processing module, the first intermediate frequency process module that is connected with the signal output of first baseband processing module, exports the first radio frequency processing module that is connected with the signal of the first intermediate frequency process module, the input of described first baseband processing module connects PC, and the output of the described first radio frequency processing module connects transmitting antenna.Receive path includes second baseband processing module, the second intermediate frequency process module and the second radio frequency processing module, the input of the described second radio frequency processing module connects reception antenna, the signal input of the second intermediate frequency process module connects the output of the second radio frequency processing module, the signal input of second baseband processing module connects the output of the second intermediate frequency process module, and the signal of second baseband processing module outputs to PC; Parallel cable is connected between described first baseband processing module and second baseband processing module.
In the such scheme, described first baseband processing module comprises a DSP (digital signal processor) module, be used for the DSP procedure stores a FLASH (flash memory) module and with a DSP module interconnects and and a FPGA (field programmable gate array) module of its collaborative work; The input that the output of a described FPGA module divides two-way to be connected to the first intermediate frequency process module, and link to each other with PC by USB interface, be connected with the second baseband processing module parallel cable by general-purpose interface simultaneously.Described second baseband processing module comprises the 2nd DSP module, be used for the DSP procedure stores the 2nd FLASH module and with the 2nd DSP interconnection and and the 2nd FPGA module of its collaborative work, described the 2nd FPGA module divides two-way to be connected to the output of the second intermediate frequency process module, and link to each other with PC by USB interface, be connected with the first baseband processing module parallel cable by general-purpose interface simultaneously; Described the 2nd DSP also is connected with two SDRAM (synchronous DRAM).
The first intermediate frequency process module comprises DUC (Digital Up Convert) and DAC (digital to analog converter) chip, an AGC (automatic gain control) module that links to each other with this chip output, first Surface Acoustic Wave Filter that links to each other with an AGC module output and the 2nd AGC module that is connected to the first Surface Acoustic Wave Filter output, the input of described DUC and DAC chip is connected first baseband processing module, and the output of described the 2nd AGC module connects the first radio frequency processing module.The second intermediate frequency process module comprises the 3rd AGC module, second Surface Acoustic Wave Filter that links to each other with the 3rd AGC module output, the fixed gain broadband operational amplifier that links to each other with rising tone table filter output, ADC (analog to digital converter) module that links to each other with this fixed gain broadband operational amplifier output and DDC (Digital Down Convert) module that links to each other with the output of ADC module, the input of described the 3rd AGC module is connected to the second radio frequency processing module, and the output of described DDC module is connected to second baseband processing module.Described DUC and DAC chip are the AD9857 chip, and this chip is connected with differential clocks between the FPGA and exchanges resaistance-capacity coupling circuit.Described ADC module is the AD9433 chip, and this chip is connected with differential clocks between the 2nd FPGA and exchanges resaistance-capacity coupling circuit.
Characteristics of the present invention are Base-Band Processing mode, the digital if technologies that adopt based on DSP-FPGA, and the radio-frequency (RF) receiving and transmission module in the digital television system is used for the hardware terminal of CR experimental system, obtained to constitute the good effect of the checking CR experimental system that can be used for practical operation.
Traditional radio communication experimental system can only be used pre-assigned definite frequency range usually, and its hardware is only supported less frequency band range, and can only be with fixing bandwidth work.The CR experimental system of CR hardware terminal of the present invention and formation thereof is compared with traditional radio communication experimental system, its beneficial effect is embodied in, it can select working frequency range in whole TV uhf band scope, in conjunction with specific algorithm, possess existence and the appearance analyzing radio frequency environment, judge authorized user (for example TV user), and adjust parameter, take rationally to dodge ability such as strategy according to analysis result, and can not cause flagrant influence to the original authorized user on the TV band.
Description of drawings
Fig. 1 is a CR experimental system hardware terminal general structure block diagram of the present invention.
Fig. 2 is the structured flowchart of sendaisle first baseband processing module among Fig. 1.
Fig. 3 is the structured flowchart of receive path second baseband processing module among Fig. 1.
Fig. 4 is the structured flowchart of the sendaisle first intermediate frequency process module among Fig. 1.
Fig. 5 is the structured flowchart of the receive path second intermediate frequency process module among Fig. 1.
Fig. 6 is the power module of CR terminal among Fig. 1, and wherein Fig. 6 (a) is the power module of sendaisle, and Fig. 6 (b) is the power module of receive path.
Fig. 7 is the differential clocks circuit of DUC and DAC module among Fig. 4.
Fig. 8 is the differential clocks circuit of ADC module among Fig. 5.
Fig. 9 is the electric source filter circuit of DSP module lock Xiang Huan (PLL) among Fig. 2 and Fig. 3.
Figure 10 is the electric source filter circuit of FPGA module lock Xiang Huan (PLL) among Fig. 2 and Fig. 3
Figure 11 is a CR experimental system schematic diagram.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples:
As shown in Figure 1, a kind of hardware terminal of cognitive radio experiment system, this terminal comprise two PCB channel plates: sendaisle I and the sendaisle power module 10 of powering to sendaisle I, receive path II and the receive path power module 11 of powering for receive path II.Sendaisle I comprises baseband processing module 1, the intermediate frequency process module 3 that is connected with the signal output of baseband processing module 1, exports the radio frequency processing module 5 that is connected with the signal of intermediate frequency process module 3, the input of described baseband processing module 1 connects the USB interface of PC 9, and the output of described radio frequency processing module 5 connects transmitting antenna 7.Receive path II comprises baseband processing module 2, the intermediate frequency process module 4 that is connected with the signal input of baseband processing module 2, the radio frequency processing module 6 that is connected with the signal input of intermediate frequency process module 4, the signal output of described baseband processing module 2 connects the USB interface of PC 9, and the input of described radio frequency processing module 6 connects reception antenna 8.Be connected by parallel cable between sendaisle baseband processing module 1 and the receive path baseband processing module 2.
The baseband processing module 1 of sendaisle I receives the data file to be sent that PC 9 produces by USB interface, finishes source encoding, chnnel coding, interweaves, QAM shine upon (or QPSK, 16QAM etc.), carries out OFDM (OFDM) then and modulates.In above data handling procedure, need to add OFDM required training sequence and pilot tone synchronously, add verification and control information according to CR agreement needs simultaneously.Baseband processing module 1 disposes, and the I/Q two paths of data is delivered to intermediate frequency process module 3, finishes Digital Up Convert, DAC, amplification and filtering.What radio frequency processing module 5 adopted is the prompt modulator that becomes of finished product that uses in the digital television system, its input is analog if signal (centre frequency 36MHz, bandwidth 8MHz), output can cover the TV RF full frequency band, radio frequency processing module 5 receives the analog intermediate frequency signal of intermediate frequency process module 3 outputs, be modulated to the radio frequency band of appointment, launch by transmitting antenna 7.What receive path II finished is the inverse process of sendaisle I, the tuner finished product that uses in the digital television system that radio frequency processing module 6 adopts, input can cover the TV RF full frequency band, is output as the analog if signal of 36.13MHz centre frequency (36MHz is slightly variant with the sendaisle IF-FRE), 8MHz bandwidth.Radio frequency processing module 5 and 6 has guaranteed that terminal can be in the work of whole VHF/UHF frequency range.
Fig. 2 is the structured flowchart of baseband processing module 1, and this module comprises DSP module 21, is used for the FLASH module 23 of DSP procedure stores, and connects also and the FPGA module 22 of its collaborative work with DSp module 21; The input that the output of FPGA module 22 divides two-way (I/Q) to be connected to intermediate frequency process module 3, FPGA module 22 link to each other and carry out signal by parallel cable with the baseband processing module 2 of receive path II with PC 9 by USB interface and be connected.In the present embodiment, what DSP module 21 was selected for use is the TMS320C6416TGLZ7 digital signal processing chip of TI company, this chip system clock can reach 720M, has very strong signal handling capacity, that FPGA module 22 is selected for use is Stratix II EP2s30F672C5, there are enough hardware multipliers and memory cell in inside, and that FLASH module 23 is selected for use is AM29LV400B.DSP module 21 is that the control unit and the responsible partial data of whole baseband processing module 1 handled, it is connected with FPGA module 22 by EMIFA (external memory interface A), carry out data interaction, and (general purpose I/O) pin all has been connected to FPGA module 22, divides neatly by FPGA module 22 to be equipped with other devices of control with the McBSP1 (multichannel buffered serial port 1) of DSP module 21,2 external interrupt and GPIO; The peripheral circuit of DSP module 21 comprises FLASH module 23, clock circuit and the chip that resets (MAX708S), and wherein FLASH module 23 links to each other with DSP module 21 by EMIFB (external memory interface B); Whole system baseband portion data processing is finished in 21 cooperations of FPGA module 22 and DSP module jointly, and it is divided into the I/Q two-way exports intermediate frequency process module 3 to.FPGA module 22 is responsible for communicating by letter by the data of USB interface reception PC and with receive path II, wherein USB interface is to realize by the CY7C68013 interface connect chip of CYPRESS company, realizes by the universal I pin that directly is connected sendaisle I and receive path II with receive path II communication interface.
Fig. 3 is the structured flowchart of receive path II baseband processing module 2, this module comprises DSP module 31, be used as the FLASH module 33 of DSP procedure stores, be used as the SDRAM memory 35 and 36 of storage, and interconnect also and the FPGA module 32 of its collaborative work with DSP module 31; The output of 32 fens two-way (I/Q) of FPGA module connection intermediate frequency process module 4, FPGA module 32 links to each other with PC 9 by USB interface and is connected with sendaisle I by parallel cable.In the present embodiment, the chip of the module 21,22,23 in the chip that DSP module 31, FPGA module 32 and FLASH module 33 are selected for use and the sendaisle I baseband processing module 1 is identical, and that SDRAM memory 35 and 36 is selected for use is two MT48LC4M32B2.The peripheral circuit of DSP module 31 has increased by two SDRAM, is used for the data in the temporary intermediate link of data handling procedure; FPGA module 32 is connected by EMIFB with DSP module 31.
Fig. 4 is the structured flowchart of sendaisle intermediate frequency process module 3 of the present invention.This module comprises DUC and DAC chip 41, the first order AGC module 42 that links to each other with these chip 41 outputs, the Surface Acoustic Wave Filter 43 that links to each other with AGC module 42 outputs and the second level AGC module 44 that is connected to Surface Acoustic Wave Filter 43 outputs, the two-way of described chip 41 (I/Q) input connects sendaisle baseband processing module 1, and the output of described second level AGC module 44 connects sendaisle radio frequency processing module 5.In the present embodiment, DUC and DAC chip 41 are finished by chip of AD9857, its built-in system frequency can reach 200MHz, can pass through total its target frequency of line traffic control of SPI (Serial Peripheral Interface (SPI)), interpolation rate and gain, its function is with the baseband I of baseband processing module 1/Q data, carry out Digital Up Convert on the centre frequency of 36.15M and carry out digital-to-analogue conversion, its SPI line is the McBSP1 that is connected to DSP21 by FPGA22; Two AGC modules are all selected AD8369 for use, and the gain of AD8369 can be at-10dB to+35dB configuration, and its control interface is connected to general purpose I/O pin of FPGA22; That Surface Acoustic Wave Filter 43 is selected for use is the LBN03601 of 36.15M centre frequency 8M bandwidth, and its typical attenuation is 27.8dB.
Fig. 5 is the circuit block diagram of receive path intermediate frequency process module 4 of the present invention.This module comprises AGC module 51, the Surface Acoustic Wave Filter 52 that links to each other with AGC module 51 outputs, the fixed gain broadband operational amplifier 53 that links to each other with Surface Acoustic Wave Filter 52 outputs, the ADC module 54 that links to each other with these fixed gain broadband operational amplifier 53 outputs and the DDC module 55 that links to each other with the output of ADC module 54, the input of described AGC module 51 connects receive path radio frequency processing module 6, and the two-way of described DDC module 55 (I/Q) output is connected to receive path baseband processing module 2.In the present embodiment, the module the 42, the 43rd in AGC module 51, Surface Acoustic Wave Filter 52 and the sendaisle intermediate frequency process module 3 is identical.The control pin of AGC module 51 is connected on general purpose I/O pin of FPGA32; That fixed gain broadband operational amplifier 53 adopts is AD8350-20, and its gain is 20dB; That ADC module 54 is selected for use is AD9433, and sample rate is 105MSPS, and the highest frequency of the signal that can sample is 350MHz; That DDC module 55 is selected for use is GC1012B, and sample rate can reach 100MSPS, can export the complex signal or the real signal of different in width, can control output gain, and its control interface is a parallel interface, is connected to general purpose I/O interface of FPGA32.
Fig. 6 is a power module of the present invention, and wherein Fig. 6 (a) is the power module 10 of sendaisle I, and Fig. 6 (b) is the power module 11 of receive path II.Power module 10 comprises the large-current electric source chip 61 of the 5V voltage output that connects external power source, and these chip 61 outputs connect the large-current electric source chip 62 of 1.2V voltage output, the large-current electric source chip 63 and 3.3V voltage output LDO (low pressure difference linear voltage regulator) chip 64 of 3.3V voltage output; Power module 11 comprises the large-current electric source chip 65 of the 5V voltage output that connects external power source, the output of this chip 65 connects the large-current electric source chip 66 of 1.2V voltage output, the large-current electric source chip 67 and the 2.85V voltage output LDO chip 68 of 3.3V voltage output, and the 5V output LDO chip 69 that connects the external power source input; Because the core voltage of DSP and FPGA requires relatively harsher, electric current is bigger, so the selection particular importance of chip.That power supply chip 61 and 65 is selected in the present embodiment is LM2678, that power supply chip 62,63 and 66,67 is selected is the power module PT6944 of TI, 1.2V and 3.3V voltage can be provided simultaneously, what power supply chip 64,68 and 69 was selected is the AMS1117 family chip, and each power supply chip basic parameter is as shown in table 1.These power supply chips of selecting for use in the present embodiment can satisfy DSP and the FPGA demand when full load, have guaranteed the operate as normal of terminal.
The basic parameter of table 1 power supply chip
| Device | Input voltage (V) | Output voltage (V) | Output maximum current (A) | Efficiency eta |
| PT6944 | 4.5～5.5 | 1.2±0.022 3.3±0.043 | 6 (minimum 0.1) 6 (minimum 0.1) | The 90%@5V input, 4A output |
| LM2678-5 | 8～40 | 4.9～5.1 | 5 (minimum 0.1) | The 82%@12V input, 5A output |
| AMS1117-3.3 | 4.75～12 | 3.267～3.333 | 1 (minimum 0) | / |
| AMS1117-5 | 6.5～12 | 4.9～5.1 | 1 (minimum 0) | / |
| AMS1117-2.85 | 4.35～12 | 2.79～2.91 | 1 (minimum 0) | / |
Fig. 7 and Fig. 8 are to be respectively the DUC among Fig. 4 and the differential clocks circuit of the ADC module 54 (AD9433) among DAC module 41 (AD9857) and Fig. 5.AD9857 adopts interchange resistance-capacitance coupling mode to be connected with FPGA22, two input port CLKp, CLKn connect the positive and negative end of the difference output pin of FPGA 22 enhancement mode PLL (lock Xiang Huan) respectively among Fig. 7, wherein resistance R 97～100 provides syntype bias voltage (2V) for the clock of AD9857, the resistance R 96 that is provided with resistance and is 100 Ω between the differential clocks input pin of AD9857 is as impedance matching, and clkp_1 and clkn_1 are connected the positive and negative end of the clock input of AD9857 respectively.AD9433 provides syntype bias (3.75V) at chip internal for the PECL signal, promptly requiring the input clock level is PECL (not being LVPECL), can solve FPGA32 and the inconsistent problem of AD9433 common mode electrical level by the interchange resistance-capacitance coupling among Fig. 8, two input port ENCp in this circuit, the difference output pin that ENCn connects FPGA 32 enhancement mode PLL (lock Xiang Huan) respectively just, negative terminal, AD9433_ENCp, AD9433_ENCn is just connecting the input of AD9433 clock respectively, negative terminal, the resistance R 17 that is provided with resistance and is 100 Ω between the differential clocks input pin of AD9433 is as impedance matching.
The PLL of DSP and FPGA requires very high to power supply quality, the present invention has adopted Fig. 9 and circuit shown in Figure 10 that the power supply of PLL is carried out filtering respectively.The input pin of the lock item ring power supply of DSP module (21), (31) all is connected to the circuit of Fig. 9.The lock item ring power pins of FPGA module (22), (32) all will connect a circuit shown in Figure 10.
The whole experimental system schematic diagram of Figure 11 for constituting by CR terminal of the present invention.This system consists of the following components: 5 CR terminal use NO.1～NO.5, wherein NO. is a central user, NO.1～NO.4 is a domestic consumer, for cooperating the basic function of checking CR experimental system, a TV signal transmitter (the TV signal transmitting tower among Figure 11) and some television receivers (TV among Figure 11) have been introduced.This CR experimental system can in diameter is the zone of 300m, not support between any two common CR users QoS, data transfer rate at 5M/bps with interior RFDC, and in communication process, can detect authorized user.If authorized user occurs, then the new idle channel of Qie Huaning is kept former communication.The database storage of central user NO.5 the operating position of frequency spectrum in the system, and it is responsible for other users and allocates frequency range in advance, and with the mode transfer channel assignment information of broadcasting, it does not participate in continuing of data service.From the communications band of central user NO.5 acquisition oneself, communicate then before other domestic consumer's communications.In concrete experimentation, native system is operated in the 614-734MHz frequency range, the FDD duplex mode is adopted in communication between any two CR users, different user adopts the FDMA mode to realize multiple access, each CR user's up-downgoing channel takies the 8M bandwidth respectively, and the broadcast channel of central user NO.5 also is the 8M bandwidth.
According to top testing program, the present invention can verify the basic function of CR, has realized perceived frequency, has realized frequency spectrum share at frequency spectrum environment such as time and spatial domains, has reached the experiment effect of expection.
Claims (7)
1. the hardware terminal of a cognitive radio experiment system is characterized in that, this terminal comprises two printed circuit board, and first printed circuit board is provided with sendaisle (I) and gives the sendaisle power module (10) of sendaisle (I) power supply; Second printed circuit board is provided with receive path (II) and gives the receive path power module (11) of receive path (II) power supply; Described sendaisle (I) comprises first baseband processing module (1), the first intermediate frequency process module (3) that is connected with the signal output of first baseband processing module (1), exports the first radio frequency processing module (5) that is connected with the signal of the first intermediate frequency process module (3), the input of described first baseband processing module (1) connects PC (9), and the output of the described first radio frequency processing module (5) connects transmitting antenna (7); Described receive path (II) includes second baseband processing module (2), the second intermediate frequency process module (4) and the second radio frequency processing module (6); The input of the described second radio frequency processing module (6) connects reception antenna (8), the signal input of the described second intermediate frequency process module (4) connects the output of the second radio frequency processing module (5), the signal input of described second baseband processing module (2) connects the output of the second intermediate frequency process module (4), and the signal output of second baseband processing module (2) is connected to PC (9); Parallel cable is connected between described first baseband processing module (1) and second baseband processing module (2).
2. the hardware terminal of cognitive radio experiment system according to claim 1, it is characterized in that, described first baseband processing module (1) comprises a DSP module (21), be used for the DSP procedure stores a FLASH module (23) and with a DSP module (21) interconnection and and a FPGA module (22) of its collaborative work; The output of a described FPGA module (22) divides two-way to be connected to the input of the first intermediate frequency process module (3), the input of the one FPGA module (22) is linked to each other with PC (9) by USB interface, is connected with second baseband processing module (2) parallel cable by general-purpose interface simultaneously.
3. the hardware terminal of cognitive radio experiment system according to claim 1, it is characterized in that, described second baseband processing module (2) comprises the 2nd DSP module (31), the 2nd FLASH module (33) that is used for the DSP procedure stores, and the 2nd DSP module (31) interconnects also and the 2nd FPGA module (32) of its collaborative work together, the input of described the 2nd FPGA module (32) divides two-way to be connected to the output of the second intermediate frequency process module (4), the output of the 2nd FPGA module (32) is linked to each other with PC (9) by USB interface, is connected with first baseband processing module (1) parallel cable by general-purpose interface simultaneously; Described the 2nd DSP module (31) also is connected with two SDRAM (35) and (36).
4. the hardware terminal of cognitive radio experiment system according to claim 1, it is characterized in that, the described first intermediate frequency process module (3) comprises DUC and DAC chip (41), an AGC module (42) that links to each other with this chip (41) output, first Surface Acoustic Wave Filter (43) that links to each other with AGC module (a 42) output, and the 2nd AGC module (44) that is connected to first Surface Acoustic Wave Filter (43) output, the input of described DUC and DAC chip (41) is connected first baseband processing module (1), and the output of described second level AGC module (44) connects the first radio frequency processing module (5).
5. the hardware terminal of cognitive radio experiment system according to claim 1, it is characterized in that, the described second intermediate frequency process module (4) comprises the 3rd AGC module (51), second Surface Acoustic Wave Filter (52) that links to each other with the 3rd AGC module (51) output, the fixed gain broadband operational amplifier (53) that links to each other with second Surface Acoustic Wave Filter (52) output, the ADC module (54) that links to each other with this fixed gain broadband operational amplifier (53) output, and the DDC module (55) that links to each other with the output of ADC module (54), the input of described the 3rd AGC module (51) is connected to the second radio frequency processing module (6), and the output of described DDC module (55) is connected to second baseband processing module (2).
6. the hardware terminal of cognitive radio experiment system according to claim 4 is characterized in that, described DUC and DAC chip (41) are the AD9857 chip, and this chip is connected with the circuit that exchanges resistance-capacitance coupling with differential clocks between the FPGA (22).
7. the hardware terminal of cognitive radio experiment system according to claim 5 is characterized in that, described ADC module (54) is the AD9433 chip, and this chip is connected with differential clocks between the 2nd FPGA (32) and exchanges resaistance-capacity coupling circuit.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281414A (en) * | 2011-09-13 | 2011-12-14 | 深圳数字电视国家工程实验室股份有限公司 | Digital television radio-frequency signal acquisition device and method |
| CN102545916A (en) * | 2011-12-30 | 2012-07-04 | 三维通信股份有限公司 | Wireless digital algorithm experimental hardware system with multi-system compatibility and high flexibility |
| CN104299616A (en) * | 2014-09-10 | 2015-01-21 | 浪潮电子信息产业股份有限公司 | Voice base-band processing system based on DSP chip and FPGA chip |
| CN104717026A (en) * | 2015-03-05 | 2015-06-17 | 成都大公博创信息技术有限公司 | Anti-interference single-channel direction-finding processing device and method |
| CN106199649A (en) * | 2016-07-22 | 2016-12-07 | 中国人民解放军63908部队 | Satellite navigation receiver test platform |
| CN106226792A (en) * | 2016-07-22 | 2016-12-14 | 中国人民解放军63908部队 | Intermediate-freuqncy signal generation module |
| CN106405491A (en) * | 2016-08-29 | 2017-02-15 | 成都川美新技术股份有限公司 | Unmanned plane monitoring system based on software radio |
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2006
- 2006-06-26 CN CNB2006100430274A patent/CN100518013C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281414A (en) * | 2011-09-13 | 2011-12-14 | 深圳数字电视国家工程实验室股份有限公司 | Digital television radio-frequency signal acquisition device and method |
| CN102281414B (en) * | 2011-09-13 | 2014-10-15 | 深圳数字电视国家工程实验室股份有限公司 | Digital television radio-frequency signal acquisition device and method |
| CN102545916A (en) * | 2011-12-30 | 2012-07-04 | 三维通信股份有限公司 | Wireless digital algorithm experimental hardware system with multi-system compatibility and high flexibility |
| CN104299616A (en) * | 2014-09-10 | 2015-01-21 | 浪潮电子信息产业股份有限公司 | Voice base-band processing system based on DSP chip and FPGA chip |
| CN104717026A (en) * | 2015-03-05 | 2015-06-17 | 成都大公博创信息技术有限公司 | Anti-interference single-channel direction-finding processing device and method |
| CN106199649A (en) * | 2016-07-22 | 2016-12-07 | 中国人民解放军63908部队 | Satellite navigation receiver test platform |
| CN106226792A (en) * | 2016-07-22 | 2016-12-14 | 中国人民解放军63908部队 | Intermediate-freuqncy signal generation module |
| CN106405491A (en) * | 2016-08-29 | 2017-02-15 | 成都川美新技术股份有限公司 | Unmanned plane monitoring system based on software radio |
| CN106405491B (en) * | 2016-08-29 | 2018-11-30 | 成都川美新技术股份有限公司 | Unmanned plane based on software radio monitors system |
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