CN106199649A - Satellite navigation receiver test platform - Google Patents
Satellite navigation receiver test platform Download PDFInfo
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- CN106199649A CN106199649A CN201610581292.1A CN201610581292A CN106199649A CN 106199649 A CN106199649 A CN 106199649A CN 201610581292 A CN201610581292 A CN 201610581292A CN 106199649 A CN106199649 A CN 106199649A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/23—Testing, monitoring, correcting or calibrating of receiver elements
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- Computer Networks & Wireless Communication (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Position Fixing By Use Of Radio Waves (AREA)
Abstract
The invention discloses a kind of satellite navigation receiver test platform, relate to satellite navigation test device technique field.Described test platform includes intermediate-freuqncy signal mod subsystem, Radio Frequency Subsystem and host computer, it is connected by pci interface between described host computer with intermediate frequency Modulation subsystem, the intermediate-freuqncy signal outfan of described intermediate frequency Modulation subsystem is connected with the signal input part of described Radio Frequency Subsystem, the RF signal output of described Radio Frequency Subsystem is connected with the radio-frequency (RF) signal input end of tested satellite navigation receiver, is attached by serial ports between described tested satellite navigation receiver and described host computer.Described test platform can multiple frequency radio frequencies output of the satellite navigation system such as the analog simulation Big Dipper, GPS, for satellite navigation receiver is tested, and test simple, convenient, flexible, portable easy-to-use.
Description
Technical field
The present invention relates to satellite navigation test device technique field, particularly relate to a kind of satellite navigation receiver test flat
Platform.
Background technology
Beidou satellite navigation system is the regionality active three-dimensional satellite location and communication system that China develops voluntarily
(CNSS), it is the 3rd ripe satellite navigation system after the global positioning system (GPS) except the U.S., Muscovite GLONASS
System.This system can the most round-the-clock, round-the-clock be that all types of user provides high accuracy, highly reliable location, navigates, awards
Time service, and have short message communication capacity concurrently.The foundation of this system, for promoting that China's satellite navigation industrial chain is formed, is formed
The perfect support of national satellite navigation application industry, popularization and security system tool are of great significance.
After three big-dipper satellites of China in 2011 are sent into the predetermined transfer orbit of space by " No. three first of the Long March " carrier rocket,
On February 25th, 2012, the 11st Beidou navigation satellite of China is fiery by " Long March No. three third " delivery in Xichang Launching Site
Arrow is successfully introduced into the predetermined transfer orbit of space.According to the development strategy of Beidou satellite navigation system " three-step-march ", China in 2012
Launch 5 Beidou navigation networking satellites the most successively, with territory, continuous increase coverage, promote system service performance.
Beidou satellite navigation system December in 2011 starts to provide continuous print navigator fix to China and surrounding area on the 27th
With time service service, since operation, system working stability, some technical specification is 25 meters beyond expection, such as positioning precision expection, but
Actual test finds substantially to reach 20 meters in the whole service area providing trail run, and some area can reach 10 meters of left sides
Right；To the end of the year 2012, Beidou satellite navigation system will complete Asia-Pacific networking, form the service ability covering the Asian-Pacific area, when the time comes
To provide commencement of commercial operation service, its service precision will reach about 10 meters；To about the year two thousand twenty, will build up by more than 30 satellites
The Beidou satellite navigation system of composition, it is provided that high accuracy covering the whole world, highly reliable location, navigation and time service service.
Along with the Beidou satellite navigation system of China's independent development progressively goes up to the sky, a large amount of Beidou satellite receivers are attached to portion
In team's equipment.By global positioning receiver and the integrated navigation and location such as gyro, inertial navigation, ensureing operation, training
The aspects such as location assembly, precision strike, attitude measurement, the control commander of group have played the effect that can not be substituted.As: in nothing
Man-machine upper installation global positioning receiver, global positioning receiver and unmanned plane automatic pilot with the use of, real
Now the guiding to unmanned plane difference air route section, also can realize the Deep space tracking etc. of unmanned plane；Radar loads Global Satellite fixed
Position receiver, can realize radar be accurately positioned, orientation etc.；When artilleryman fights, it is possible to use global positioning receiver, real
Now the accurate navigation to cannon, the fine sight to impact point hit, and assist headquarter's unified command, scheduling networking cannon
Deng；Guided missile loads global positioning receiver, can accurately guide guided missile that impact point is attacked, be greatly improved and lead
The hit rate of bullet；In C4ISR system, utilize the precision time service function of global positioning receiver, all arms, each can be made
System, the operating synchronization etc. of each weapon.
But, global positioning receiver need to receive the signal of many aeronautical satellites at open field simultaneously could realize
Location, this this kind equipment regular maintenance especially prewar is prepared needed for Function detection, performance verification and assessment, fault detect with
Location, quickly guarantee maintenance etc. cause the biggest adverse effect, it is difficult to ensure the weapon dress using global navigation satellite location
Standby hidden deposit, quickly launch an attack, the quickly fight requirement such as navigation.
Summary of the invention
The technical problem to be solved is to provide a kind of satellite navigation receiver test platform, described test platform
Can multiple frequency radio frequencies output of the satellite navigation system such as the analog simulation Big Dipper, GPS, for satellite navigation receiver is carried out
Test, and test simple, convenient, flexible, portable easy-to-use.
For solving above-mentioned technical problem, the technical solution used in the present invention is: a kind of satellite navigation receiver test is flat
Platform, it is characterised in that: include intermediate-freuqncy signal mod subsystem, Radio Frequency Subsystem and host computer, described host computer and middle frequency modulation
Connected by pci interface between subsystem, the intermediate-freuqncy signal outfan of described intermediate frequency Modulation subsystem and described radio frequency subsystem
The signal input part of system connects, the RF signal output of described Radio Frequency Subsystem and the radio frequency of tested satellite navigation receiver
Signal input part connects, and is attached by serial ports between described tested satellite navigation receiver and described host computer；Described
Host computer is for man-machine interaction and calculates various emulation signal condition parameter and navigation message, produces the output of base band level data, real
Time be sent to intermediate frequency Modulation subsystem and receive positioning result that tested satellite navigation receiver sends back and according to receiving
Data resolve the performance of indices, complete satellite navigation receiver function and performance test；Intermediate frequency Modulation subsystem is used for
Complete the generation of analog if signal and the output specified；Radio Frequency Subsystem for upconverting to the frequency specified by intermediate-freuqncy signal
Point, carries out power control, and exports to tested satellite navigation receiver through radio-frequency (RF) switch conjunction road.
Further technical scheme is: described intermediate-freuqncy signal mod subsystem includes that several intermediate-freuqncy signals produce mould
Block.
Further technical scheme is: described intermediate-freuqncy signal generation module includes pci interface module, FPGA module, DSP
Module, DAC module, SRAM module and power transfer module, described pci interface module is bi-directionally connected with described FPGA module,
For realizing the data interaction of described intermediate-freuqncy signal generation module and described host computer；Described DSP module and described FPGA module
It is bi-directionally connected；DAC module is connected with the signal output part of described FPGA module；DSP module and the two-way company of described Radio Frequency Subsystem
Connect；Described FPGA module has been used for the generation of signal, it is achieved workflow and data interaction；Described DSP module for
Position machine transmits the data come and processes, and calculates the control word generated needed for intermediate-freuqncy signal；Described DAC module is controlled by described
FPGA module, is used for realizing digital-to-analogue conversion and up-conversion；Described power transfer module and described signal generator module need to supply
The power input of the module of electricity connects, for providing working power for it；Described SRAM module is two-way with described FPGA module
Connect, for data cached.
Further technical scheme is: described FPGA module is selected in the V6 series of XILINX company
XC6VLX240T-1FFG1156；DSP module selects the TMS320C6713B-225 chip of TI company；DAC module is selected
AD9779A；Power module selects the SN74CB3T16211 of TI company, and SRAM module selects ISSI company
IS61WV102416BLL chip.
Further technical scheme is: described power module includes the first to the 5th independent power source module, described first point
The input termination 12V input power of power module and the second independent power source module, the output voltage of described first independent power source module is
2.5V, the outfan of the first independent power source module is divided into two-way, the first via to be connected with the power input of the second independent power source module, the
Two tunnels are connected with a power input of FPGA, and the output voltage of described second independent power source module is 1V, described second point of electricity
The power output end of source module is connected with FPGA power input；The input termination 12V input of the 3rd independent power source module
Power supply, the output voltage of the 3rd independent power source module is 3.3V, the power output end of the 3rd independent power source module and a power supply of DSP
Input connects；The input termination 3.3V power supply of the 4th and the 5th independent power source module, the output voltage of the 4th independent power source module is
1.2V, the outfan of the 4th independent power source module is divided into two-way, the first via to be connected with a power input of DSP, the second tunnel with
One power input of FPGA connects；The output voltage of the 5th independent power source module is 1.8V, the output of the 5th independent power source module
End is connected with the power input of the module in addition to FPGA and DSP in intermediate-freuqncy signal generation module.
Further technical scheme is: described first independent power source module includes PTR08100W type power supply chip U35, institute
1 foot stating U35 is unsettled, and 2 feet of described U35 connect 12V input power, and electric capacity C258 is connected in parallel between the input of power supply and ground,
The 3 foot ground connection of described U35,5 feet of described U35 are through resistance R180 ground connection；4 feet of described U35 are divided into three tunnels, and the first via is through electric capacity
C256 ground connection, the second tunnel is divided into again three tunnels through electric capacity C257 ground connection, the 3rd tunnel after connector J8, and the first via is successively through resistance
Ground connection after R178 and light emitting diode D21, the second tunnel is a power output end of described first independent power source module, and the 3rd tunnel is
Another power output end of described first part of power module, two output voltages of described first independent power source module are 2.5V；
Described second independent power source module includes PTH04T240W type power supply chip U36, the 1 of described U36,3,4,7 foot ground connection,
2 feet of described U36 are connected with a power output end of described first independent power source module, and 5 feet and 6 feet of described U36 are divided into two
Road, the first via connects 9 feet of described U36 through electric capacity C261 ground connection, the second tunnel through resistance R175, and 8 feet of described U36 are through resistance R181
Ground connection；10 feet of described U36 are connected with 2 feet of described U36, and the power input of described U36 is parallel with electric capacity C259 and electric capacity
11 feet of C260, described U36 are unsettled, and the node of resistance R175 and electric capacity C261 is divided into two-way, the first via through electric capacity C262 ground connection,
Second tunnel is divided into again two-way after connector J9, and the first via is a power output end of described second independent power source module, and second
Road is another power output end of the second independent power source module；
Described 3rd independent power source module includes that 1 foot of TPS73801 type power supply chip U39, described U39 connects 12V input electricity
Source, filter capacitor C269 is connected in parallel on the power input of described U39,3 feet of described U39 and 6 foot ground connection, 5 feet of described U39
2 feet meeting VCC, described U39 are divided into three tunnels, and first via ground connection after resistance R184, resistance R187 successively, the second tunnel is through electric capacity
Ground connection after C268, the 3rd tunnel is divided into two-way after patch plug J12, and the first via is the power supply output of described second independent power source module
End, the second tunnel ground connection after resistance R185, light emitting diode D23 successively；
Described 4th independent power source module includes 1-4 foot and the 15-16 foot of ADP1740 type power supply chip U37, described U37
Being divided into two-way, the first via to connect 3.3V input power, the second tunnel connects 1.2V input power, 3.3V power input through resistance R182
5 feet being provided with filter capacitor C263, described U37 connect 1.2V input power, the 6 foot ground connection of described U37, the 7 foot warps of described U37
Ground connection after electric capacity C265,8 feet of described U37 are unsettled, and the 9-11 foot of described U37 is connected with 12 feet of described U37, described U37's
12 feet are divided into two-way, and the first via is connected with 13 feet and 14 feet of described U37 respectively, and the second tunnel is divided into two-way after patch plug J10,
The first via is a power output end of described 4th independent power source module, and the second tunnel is another of described 4th independent power source module
Power output end；
Described 5th independent power source module includes that 5 feet of LT1963A type power supply chip U34, described U34 and 8 feet connect as power supply
Input, 4 feet that described electric capacity input is provided with filter capacitor C254, described U34 are unsettled, the 3 of described U34,6,7 feet connect
Ground, 2 feet of described U34 and 1 foot connect, and 1 foot of described U34 is divided into three tunnels, and the first via is through electric capacity C255 ground connection, and the second tunnel is successively
Ground connection after resistance R176 and light emitting diode D20, the 3rd tunnel is the power output end of described 5th independent power source module.
Further technical scheme is: DSP include control word register module, code NCO control word generation module,
Satellite number and chip select control word generation module, navigation message generation module, amplitude control words generation module and carrier wave NCO
Control word generation module；FPGA includes a yard NCO generation module, frequency divider, spread spectrum code generation module, subcarrier generation module, meter
Number device, FIFO generation module, band spectrum modulation module, carrier wave NCO generation module and orthogonal modulation module, described control word depositor
The outfan of module selects control word generation module, navigation with described code NCO control word generation module, satellite number and chip respectively
Text generation module, the input of amplitude control words generation module connect, the outfan warp of described code NCO control word generation module
Described code NCO generation module is connected with the input of described frequency divider, and described satellite number and chip select control word generation module
Outfan be connected with the input of described spread spectrum code generation module, an outfan of described frequency divider and described spread spectrum code are raw
The input becoming module connects, and another outfan of described frequency divider is through described subcarrier generation module and described spread spectrum
One input of modulation module connects, and an outfan of spread spectrum code generation module is defeated with one of described band spectrum modulation module
Entering end to connect, another outfan of described spread spectrum code generation module is through an input of described enumerator Yu described fifo module
End connects, and the outfan of described navigation message generation module is connected with an input of described fifo module, described FIFO mould
The outfan of block is connected with an input of described band spectrum modulation module, the outfan of described amplitude control words generation module with
One input of described band spectrum modulation module connects, and described carrier wave NCO control word generation module generates through described carrier wave NCO
After module, two inputs with described orthogonal modulation module are connected, the outfan of described band spectrum modulation module and described positive intermodulation
One input of molding block connects, and an outfan of described orthogonal modulation module is I branch road, and another outfan is that Q props up
Road, I branch road and Q branch road are connected with the input of described DAC module.
Further technical scheme is: described Radio Frequency Subsystem includes several up-converter modules, power module, crystal oscillator
And combiner, the input of described up-converter module is connected with the intermediate-freuqncy signal outfan of described intermediate-freuqncy signal mod subsystem,
Described power module is connected with the power input of the module needing power supply in described Radio Frequency Subsystem, for providing work for it
Power supply, the outfan of described up-converter module is connected with the input of described combiner, and the outfan of described combiner is described
The signal output part of Radio Frequency Subsystem, described crystal oscillator be described Radio Frequency Subsystem provide work clock, described up-converter module with
And combiner is controlled by described intermediate-freuqncy signal mod subsystem.
Further technical scheme is: described up-converter module includes microcontroller, LO module, I/Q modulator, filtering
The intermediate frequency letter of device, AGC module and attenuation network module, the signal input part of described I/Q modulator and intermediate-freuqncy signal mod subsystem
Number outfan connects, the input termination crystal oscillator input of described LO module, the outfan of described LO module and described I/Q modulator
Control end to connect, the most filtered device of outfan of described I/Q modulator, AGC module and the input of described attenuation network module
Connect, the outfan of described attenuation network module is RF signal output, the control output end of described microprocessor respectively with
The control end of described LO module and attenuation network module connects, and described microcontroller is with described intermediate-freuqncy signal mod subsystem even
Connect, the control command of receiving intermediate frequency signal mod subsystem output.
Further technical scheme is: described AGC module includes level detector, LPF module, comparator, control electricity
Pressure generation module and VGA module, the outfan of described level detector produces through described LPF module, comparator, control voltage successively
Raw circuit is connected with the control end of described VGA module, and the input of described VGA module terminates input voltage, described VGA module defeated
Going out end and be divided into two-way, the first via is voltage output end, and the second tunnel is connected with the input of described level detector, described comparator
One input termination reference voltage.
Use produced by technique scheme and have the beneficial effects that: can the satellite navigation system such as the analog simulation Big Dipper, GPS
Multiple frequency RF output of system, signal output accuracy is better than the satellite navigation signals of reality；Random time, arbitrarily can be simulated
The visual Big Dipper in place, the satellite navigation emulation signal of GPS system；Can simulate raw according to typical weaponry kinetic characteristic
Become the navigation satellite signal under different carriers varying environment.Also can be loaded into real movement locus, simulate output satellite signal, real
Now the closed loop of navigation positioning system performance is verified；Arrange according to different application scenarios, position error factor and big I thereof；
Can the dynamic response capability of on-line testing satellite positioning receiver, signal receiving sensitivity, positioning precision, timing accuracy, speed
Multiple receiver technical specifications such as degree precision, positioned update rate, startup time, and output test result；Fault diagnosis navigates to
The replaceable units of satellite navigation receiver.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings.
Fig. 1 is the theory diagram of test platform described in embodiment；
Fig. 2 is the theory diagram of embodiment intermediate-freuqncy signal generation module；
Fig. 3 is the theory diagram of power module in embodiment intermediate-freuqncy signal generation module；
Fig. 4-Fig. 8 is the circuit theory diagrams of the first to the 5th independent power source module in embodiment power module；
Fig. 9 is the theory diagram of DSP+FPGA in embodiment；
Figure 10 is the theory diagram of Radio Frequency Subsystem in embodiment；
Figure 11 is the theory diagram of signal up-converter module in embodiment；
Figure 12 is the theory diagram of AGC module in embodiment.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of protection of the invention.
Elaborate a lot of detail in the following description so that fully understanding the present invention, but the present invention is all right
Using other to be different from alternate manner described here to implement, those skilled in the art can be without prejudice to intension of the present invention
In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Overall, as it is shown in figure 1, the invention discloses a kind of satellite navigation receiver test platform, including intermediate-freuqncy signal
Mod subsystem, Radio Frequency Subsystem and host computer, be provided with test software and control software in described host computer.Described host computer
Being connected by pci interface with between intermediate frequency Modulation subsystem, the intermediate-freuqncy signal outfan of described intermediate frequency Modulation subsystem is with described
The signal input part of Radio Frequency Subsystem connects, and the RF signal output of described Radio Frequency Subsystem receives with tested satellite navigation
The radio-frequency (RF) signal input end of machine connects, and is carried out even by serial ports between described tested satellite navigation receiver and described host computer
Connect.
By the analysis and research to user type, user movement track and attitude, position error, battlefield navigational environment etc.,
Set up typical user model, error model and use scene.Signal scene generating module in simulation test application software
Generate different scene environment, according to the position (longitude, latitude and height) specified, the time specified and cycle and correspondence
The specific satellite information of ephemeris file generated, including each satellites in view satellite navigation data within a specified time, power electricity
Gentle Doppler frequency shift etc..It is separately added into the satellite constellation of the Big Dipper, GPS system, it is achieved multi-satellite navigation system real-time simulation
Ability.Use modular structure, possess expandability, can add other receiver of satellite navigation system as required
Test.
Described host computer is used for being responsible for man-machine interaction, according to set constellation orbital, signal structure, carrier movement state,
The simulation calculation such as propagated error various signal condition parameter and navigation message, produce the output of base band level data, and be sent in real time
Intermediate-freuqncy signal mod subsystem；Intermediate-freuqncy signal mod subsystem has been responsible for the band spectrum modulation of each signal, subcarrier modulation and has carried
Ripple is modulated, it is achieved the accurate control of Doppler, code phase, carrier phase and relative level, and the modulation of multipath signal and control
System, and generate the analog if signal output specified after closing road；Radio Frequency Subsystem is responsible for the frequency up-converting the signals to specify,
Carry out power control, and exported to tested satellite navigation receiver by coaxial cable or antenna after radio-frequency (RF) switch closes road.
Described test platform can multiple frequency RF output of the satellite navigation system such as the analog simulation Big Dipper, GPS, signal is defeated
Go out precision and be better than the satellite navigation signals of reality；Random time, the visual Big Dipper of anywhere, the satellite of GPS system can be simulated
Navigation simulation signal；The navigation generated under different carriers varying environment can be simulated according to typical weaponry kinetic characteristic
Satellite-signal.Also can be loaded into real movement locus, simulate output satellite signal, it is achieved the closed loop to navigation positioning system performance
Checking；Arrange according to different application scenarios, position error factor and big I thereof；Can on-line testing satellite positioning receiver
Dynamic response capability, signal receiving sensitivity, positioning precision, timing accuracy, velocity accuracy, positioned update rate, start the time
Etc. multiple receiver technical specifications, and output test result；Fault diagnosis navigates to the replaceable list of satellite navigation receiver
Unit.
Intermediate-freuqncy signal mod subsystem includes several intermediate-freuqncy signal generation modules, the side of intermediate-freuqncy signal generation module design
Case uses PCI+DSP+FPGA+DAC framework.Host computer generates Satellite Observations and navigation message in pci interface is transferred to
Frequently signal generator module, intermediate-freuqncy signal generation module synthesizes digital medium-frequency signal according to Satellite Observations and navigation message, enters
Analog if signal is exported after row digital-to-analogue conversion.Further, as in figure 2 it is shown, described intermediate-freuqncy signal generation module includes that PCI connects
Mouth die block, FPGA module, DSP module, DAC module, SRAM module and power transfer module, described pci interface module and institute
State FPGA module to be bi-directionally connected, for realizing the data interaction of described intermediate-freuqncy signal generation module and described host computer.
In described intermediate-freuqncy signal generation module, the annexation of modules is as follows: described DSP module and described FPGA mould
Block is bi-directionally connected；DAC module is connected with the signal output part of described FPGA module；DSP module is two-way with described Radio Frequency Subsystem
Connect；Described FPGA module has been used for the generation of signal, it is achieved workflow and data interaction；Described DSP module is for right
Host computer transmits the data come and processes, and calculates the control word generated needed for intermediate-freuqncy signal；Described DAC module is controlled by described
FPGA module, is used for realizing digital-to-analogue conversion and up-conversion；Described power transfer module and described signal generator module need to supply
The power input of the module of electricity connects, for providing working power for it；Described SRAM module is two-way with described FPGA module
Connect, for data cached.
Signal processing: use FPGA+DSP+DAC structure, DSP major function is to calculate the control generated needed for intermediate-freuqncy signal
Word；The function of FPGA has been that signal produces, including pseudo noise code generation, carrier wave generation, band spectrum modulation, carrier modulation, He Lu
With sequencing contro etc., i.e. ensure workflow and the data interaction in whole intermediate frequency source；The control of DA is completed by FPGA, it is achieved number
Mould conversion and two functions of up-conversion.
Data process: completed by DSP, process to as if the packet that transmits from host computer (include each satellite channel
Observation data and navigation message information), it is achieved function be satellitosis to be observed data change into some control words, these control
Word processed passes to the FPGA generation for control signal.
Signal produces: completed by FPGA, by reading the control word that DSP is transferred in SRAM, it is achieved intermediate-freuqncy signal
Synthesis, including carrier wave NCO, code NCO, spectrum-spreading code generator, band spectrum modulation, carrier modulation, signal combiner etc. at digital signal
Reason function.
Sequencing contro: be also to be completed by FPGA.The realization of intermediate-freuqncy signal be required to meet host computer real-time transmission data,
DSP real-time processing data, FPGA produce signal in real time, need a public control between host computer, DSP and FPGA three
Molding block ensures between various piece that workflow meets and does not collides with each other in real time, and sequencing contro is exactly such control mould
Block.
The function that DAC module realizes is that digital medium-frequency signal changes into analog if signal, and also to realize mould
Intend the up-conversion of intermediate-freuqncy signal.
FPGA: selecting the XC6VLX240T-1FFG1156 in the V6 series of XILINX company, its dominant frequency is about 600M,
The Block RAM of 37680 Slice, about 15Mb, 768 DSP48E, various resources are the abundantest.In this problem, each intermediate frequency
Plate needs at most to provide two frequency bins totally 36 passages to produce Pseudolite signal, and resource requirement is bigger, and this kind of chip can meet
The demand of problem.
DSP: selecting the TMS320C6713B-225 chip of TI company, the highest arithmetic speed reaches 1200MIPS.This problem
In, the function of dsp chip is to calculate the data that host computer transmits, and result of calculation stores appointment position.Due to general
Dsp chip can complete this functionality, so we have selected a dsp chip that laboratory is very familiar
TMS320C6713B-225, saves development time and cost.
SRAM: select the IS61WV102416BLL chip of ISSI company, this kind of chip can be managed with the 2.5V IO of FPGA
Foot is joined directly together without voltage conversion chip, and Read-write Catrol (DDR) relatively is simple.The memory space of 16Mb is entirely capable of meeting
The needs (needing the total amount of data of storage less than 5Mb) of caching.
DAC:AD9779A is a 16 dynamic ranges DAC the widest that Analog Device company produces, sample rate
1Gsps, it is allowed to the up to multicarrier of nyquist frequency generates.It is novel that 2X, 4X, 8X interpolation device/coarse adjustment complex modulator can
Carrier wave to be placed on any position of DAC band alleviating distention in middle-JIAO, running voltage 1.8～3.3V, power consumption 1W during sample rate 1Gsps.
PXIE cabinet: select the PXIe-1075 cabinet of NI company, including 8 PXIE slots, 8 PXIE or PXI mixing are inserted
Groove, 1 system clock slot, 1 PXIE control module, support PXI, PXIE, Compact PCI and Compact PCIE interface
Module.Containing 4 PCIE Switch, each Switch by the LINK of 1 X4PCIE with 4 or 5 peripheral slot phases
Even, each slot support is up to the transmission bandwidth of 1GB/S.If multiple equipment are connected in a PCIE Switch, they are shared
The transmission bandwidth of 1GB/S.
Power conversion chip: owing to the I/O pin signal of DSP and DAC is 3.3V level, and FPGA obtains IO voltage is
2.5V, it is therefore desirable to power conversion chip carries out level conversion.Select SN74CB3T16211, the 2.5V single-ended power of TI company,
Electrical source consumption electric current is 70uA.The 3.3V high level output signal of DSP can be converted into the voltage of about 2.3V to FPGA, FPGA's
2.5V output can be converted into the output of about 2.2V to DSP, meets the minimum input voltage (>=2V) requirement of DSP high level.
Intermediate-freuqncy signal generation module is to be embedded in NI PXIE-1075 cabinet with the form of board, cabinet slot be that it carries
Power supply source inputs, and selects 3.3V/6A and 12V/4A to input as power supply, it should be noted that the power that each slot is provided that is
Greatly 38.25W.Power consumption analysis result according to chip, the powering solution of proposition is as shown in Figure 3.Wherein 12V to 3.3V/
During 2.5V/1V conversion, pressure reduction is relatively big, and the supply current needed for chip is the biggest, therefore selects Switching Power Supply DC-DC.And 3.3V
Turn 1.2V/1.8V pressure reduction less, and needed for chip, supply current is the least, therefore select linear stable.In power module each
The circuit theory diagrams of independent power source module are as shown in Fig. 4-Fig. 8.
As it is shown on figure 3, described power module includes the first to the 5th independent power source module, described first independent power source module and
The input termination 12V input power of two independent power source modules, the output voltage of described first independent power source module is 2.5V, first point of electricity
The outfan of source module is divided into two-way, the first via to be connected with the power input of the second independent power source module, and the second tunnel is with FPGA's
One power input connects, and the output voltage of described second independent power source module is 1V, the power supply of described second independent power source module
Outfan is connected with a power input of FPGA；The input termination 12V input power of the 3rd independent power source module, the 3rd point of electricity
The output voltage of source module is 3.3V, and the power output end of the 3rd independent power source module is connected with a power input of DSP；The
The input termination 3.3V power supply of the four and the 5th independent power source module, the output voltage of the 4th independent power source module is 1.2V, the 4th point of electricity
The outfan of source module is divided into two-way, the first via to be connected with a power input of DSP, the second tunnel and a power supply of FPGA
Input connects；The output voltage of the 5th independent power source module is 1.8V, and the outfan of the 5th independent power source module produces with intermediate-freuqncy signal
In raw module, the power input of the module in addition to FPGA and DSP connects.
As shown in Figure 4, described first independent power source module includes PTR08100W type power supply chip U35, and 1 foot of described U35 hangs
Sky, 2 feet of described U35 connect 12V input power, and electric capacity C258 is connected in parallel between the input of power supply and ground, 3 feet of described U35
Ground connection, 5 feet of described U35 are through resistance R180 ground connection；4 feet of described U35 are divided into three tunnels, the first via through electric capacity C256 ground connection,
Two tunnels are divided into again three tunnels through electric capacity C257 ground connection, the 3rd tunnel after connector J8, and the first via is successively through resistance R178 and luminous two
Ground connection after the pipe D21 of pole, the second tunnel is a power output end of described first independent power source module, and the 3rd tunnel is described first part of electricity
Another power output end of source module, two output voltages of described first independent power source module are 2.5V；
As it is shown in figure 5, described second independent power source module includes PTH04T240W type power supply chip U36, the 1 of described U36,3,
4,7 foot ground connection, 2 feet of described U36 are connected with a power output end of described first independent power source module, 5 feet of described U36 and
6 feet are divided into two-way, and the first via connects 9 feet of described U36 through electric capacity C261 ground connection, the second tunnel through resistance R175,8 feet of described U36
Through resistance R181 ground connection；10 feet of described U36 are connected with 2 feet of described U36, and the power input of described U36 is parallel with electric capacity
11 feet of C259 and electric capacity C260, described U36 are unsettled, and the node of resistance R175 and electric capacity C261 is divided into two-way, and the first via is through electricity
Holding C262 ground connection, the second tunnel is divided into again two-way after connector J9, and the first via is a power supply of described second independent power source module
Outfan, the second tunnel is another power output end of the second independent power source module；
As shown in Figure 6, described 3rd independent power source module includes that 1 foot of TPS73801 type power supply chip U39, described U39 connects
12V input power, filter capacitor C269 is connected in parallel on the power input of described U39,3 feet of described U39 and 6 foot ground connection, institute
State 5 feet of U39 to connect 2 feet of VCC, described U39 and be divided into three tunnels, first via ground connection after resistance R184, resistance R187 successively, second
Road is ground connection after electric capacity C268, and the 3rd tunnel is divided into two-way after patch plug J12, and the first via is the electricity of described second independent power source module
Source output terminal, the second tunnel ground connection after resistance R185, light emitting diode D23 successively；
As it is shown in fig. 7, described 4th independent power source module include the 1-4 foot of ADP1740 type power supply chip U37, described U37 with
And 15-16 foot is divided into two-way, the first via to connect 3.3V input power, the second tunnel connects 1.2V input power, 3.3V electricity through resistance R182
Source input is provided with 5 feet of filter capacitor C263, described U37 and connects 1.2V input power, the 6 foot ground connection of described U37, described
Ground connection after the 7 foot meridian capacitor C265 of U37,8 feet of described U37 are unsettled, and the 9-11 foot of described U37 is connected with 12 feet of described U37,
12 feet of described U37 are divided into two-way, and the first via is connected with 13 feet and 14 feet of described U37 respectively, and the second tunnel is after patch plug J10
Being divided into two-way, the first via is a power output end of described 4th independent power source module, and the second tunnel is described 4th independent power source mould
Another power output end of block；
As shown in Figure 8, described 5th independent power source module includes LT1963A type power supply chip U34,5 feet of described U34 and 8
Foot connects as power input, and 4 feet that described electric capacity input is provided with filter capacitor C254, described U34 are unsettled, described U34's
3,6,7 foot ground connection, 2 feet of described U34 and 1 foot connect, and 1 foot of described U34 is divided into three tunnels, the first via through electric capacity C255 ground connection,
Second tunnel ground connection after resistance R176 and light emitting diode D20 successively, the 3rd tunnel is that the power supply of described 5th independent power source module is defeated
Go out end.
Intermediate-freuqncy signal generation module completes based on DSP+FPGA, as it is shown in figure 9, DSP includes that control word is deposited
Device module, code NCO control word generation module, satellite number and chip select control word generation module, navigation message generation module, width
Degree control word generation module and carrier wave NCO control word generation module；FPGA includes a yard NCO generation module, frequency divider, spread spectrum code
Generation module, subcarrier generation module, enumerator, FIFO generation module, band spectrum modulation module, carrier wave NCO generation module and just
Hand over modulation module, the outfan of described control word register module respectively with described code NCO control word generation module, satellite number and
Chip selects control word generation module, navigation message generation module, the input of amplitude control words generation module to connect, described code
The outfan of NCO control word generation module is connected with the input of described frequency divider through described code NCO generation module, described satellite
Number and chip select control word generation module outfan be connected with the input of described spread spectrum code generation module, described frequency divider
An outfan be connected with an input of described spread spectrum code generation module, another outfan of described frequency divider is through institute
State subcarrier generation module to be connected with an input of described band spectrum modulation module, an outfan of spread spectrum code generation module
Being connected with an input of described band spectrum modulation module, another outfan of described spread spectrum code generation module is through described counting
Device is connected with an input of described fifo module, the outfan of described navigation message generation module and described fifo module
One input connects, and the outfan of described fifo module is connected with an input of described band spectrum modulation module, described width
The outfan of degree control word generation module is connected with an input of described band spectrum modulation module, described carrier wave NCO control word
Generation module two inputs with described orthogonal modulation module after described carrier wave NCO generation module are connected, and described spread spectrum is adjusted
The outfan of molding block is connected with an input of described orthogonal modulation module, an outfan of described orthogonal modulation module
For I branch road, another outfan is Q branch road, and I branch road and Q branch road are connected with the input of described DAC module.
In the present invention, sample clock frequency fS=90MHz, phase accumulator figure place and FREQUENCY CONTROL word bit number are all taken as N
=32, phase controlling word bit number only takes 16, but it is be added in phase accumulator high 16.By two form of look
Realizing the sinusoidal wave and phase/amplitude conversion output of cosine wave, deposit in look-up table is all that cos (x) is at x ∈ [0 pi/2]
Data, quantization digit is 16bit, and data amount check is 1024.The addressing bit number of look-up table is set to 10, intercepts phase accumulator 32
Low 10 addresses as look-up table of high 12 of position output input, and the 11st and the 12nd, as character control bit, controls
The local digital sine in 0～2 π whole cycles of output and cosine carrier signal.The local digital carrier wave letter of carrier wave NCO module output
Number frequency be fC=M/232× 90MHz, frequency resolution is Δ f=90MHz/232≈ 0.02Hz, meets design needs.Carrier wave
Real-time frequency control word and the real-time phase control word of NCO are calculated by DSP.
In the present invention, code NCO module is the same with carrier wave NCO module, sample clock frequency fS=90MHz, phase accumulator
Figure place and FREQUENCY CONTROL word bit number are all taken as N=32, and phase controlling word bit number only takes 16, but it is to be added in phase accumulator
High 16.The output of code NCO module need not look-up table, directly intercepts highest order that is the 31st of phase accumulator, is
Being used for driving the clock signal of pseudo-code generator, the same with carrier wave NCO module, its frequency size is also fC=Mfs/2N, frequency is divided
Resolution is also Δ f=fs/232。
Real-time frequency control word M and real-time phase control word P of code NCO module are calculated by DSP.Numeral closes road module
By 12 direct signal passages and 6 multipath signal passage compositions, can simulate simultaneously produce the straight of most 12 aeronautical satellites
Penetrate signal and the multipath signal of most 6 aeronautical satellites.Owing to the intermediate-freuqncy signal of GNSS signal simulator generation is by I road and Q road
Two paths of signals forms, therefore there is Liang Gehe road module I road and Q road signal respectively to each passage and carry out closing road.
Amplitude for making signal close road output does not changes with the change of visible satellite, all introduces in each single channel signal
The amplitude control words AMP_CTL of 16bit, and the value of each channel amplitude control word is the most identical；When the number of visible satellite is N,
Signal after each visible satellite passage is not multiplied by the band spectrum modulation of amplitude control words and subcarrier modulation is output as the A of 19biti(i
=1,2,3 ... N), the amplitude control words AMP_CTL of each passage is set to 0x1FFF/N, and result S_add after so closing road is:
Behind Ji He road, result maximum is not more than 35bit, this ensures that theres numeral conjunction road and only need to share a 35bit
Carrier adder, do not result in data overflow, saved the hardware resource of FPGA.Quantization digit due to AD9779A
Being 16, therefore the result on passage conjunction road needs to block, and takes high 16.
Data interaction main two: one between Radio Frequency Subsystem and intermediate-freuqncy signal mod subsystem is the simulation in intermediate frequency source
Intermediate-freuqncy signal needs to be transferred to radio-frequency head；Two is that intermediate frequency source controls correctly carrying out of radio-frequency head upconversion function, and detects radio frequency
The data interaction of the duty of end, the former is directly connected to.
Intermediate-freuqncy signal mod subsystem to the control of Radio Frequency Subsystem by I2C (Inter-Integrated Circuit)
Interface realizes, DSP complete.I2C bus is the twin wire universal serial bus developed by PHILIPS company, is used for connecting micro-control
Device processed and ancillary equipment thereof.It is a kind of specific form of synchronous communication, has interface line few, and control mode is simple, cabling side
Just, traffic rate relatively advantages of higher.
The data that IF board sends, its content is mainly performance number, is used for arranging or returning the output of radiofrequency signal
Value, in the operation that need not setting or return performance number, data content fills 0.Data have two bytes, are divided into high by eight
Position is with low eight, and the scope that can control power is :-140dB～-80dB, and precision is 0.5dB.
Radio Frequency Subsystem is mainly made up of 3 up-converter modules and 1 vector signal generator with upconversion function.
Wherein 3 up-converter circuit plates are mainly used in be produced, by intermediate-freuqncy signal, 3 frequency satellite navigation intermediate frequencies that processing unit obtains
Signal is converted to corresponding radiofrequency signal.Host computer produces processing unit by intermediate-freuqncy signal and realizes the frequency to radiofrequency signal simultaneously
Rate and the control of power.The each frequency point intermediate frequency signal of each system obtained by intermediate-freuqncy signal generation module is respectively via corresponding upper change
Frequency module upconverts to corresponding radiofrequency signal.
Concrete, as shown in Figure 10, described Radio Frequency Subsystem include several up-converter modules, power module, crystal oscillator and
Combiner, the input of described up-converter module is connected with the intermediate-freuqncy signal outfan of described intermediate-freuqncy signal mod subsystem, institute
The power input of the module stating power module and need power supply in described Radio Frequency Subsystem is connected, for providing work electricity for it
Source, the outfan of described up-converter module is connected with the input of described combiner, the outfan of described combiner be described in penetrate
Frequently the signal output part of subsystem, described crystal oscillator be described Radio Frequency Subsystem provide work clock, described up-converter module and
Combiner is controlled by described intermediate-freuqncy signal mod subsystem.
As shown in figure 11, described up-converter module includes that microcontroller, LO module, IQ modulate to individual signals up-converter module
Device, wave filter, AGC module and attenuation network module.The signal input part of described I/Q modulator and intermediate-freuqncy signal mod subsystem
Intermediate-freuqncy signal outfan connect, the input of described LO module termination crystal oscillator input, the outfan of described LO module and described IQ
The control end of manipulator connects, the most filtered device of outfan of described I/Q modulator, AGC module and described attenuation network module
Input connect, the outfan of described attenuation network module is RF signal output, the control of described microprocessor output
End control end with described LO module and attenuation network module respectively is connected, described microcontroller and the modulation of described intermediate-freuqncy signal
Subsystem connects, the control command of receiving intermediate frequency signal mod subsystem output.
Wherein: I/Q modulator is in order to realize the mixing of IF input signals and local oscillation signal.Wave filter for local oscillator with in
Frequently the filtering after signal mixing.AGC (automatic growth control) module is a kind of in the case of input signal amplitude change the most greatly
Make the automatic control circuit that amplitude output signal changes in smaller range.Power in order to make radio frequency export controls accurately, to press down
Device temperature drifts processed etc., use AGC module that manipulator output is controlled on certain power (0dBm).
AGC module principle is illustrated in fig. 12 shown below: described AGC module includes level detector, LPF module, comparator, control
Voltage generating module and VGA module, the outfan of described level detector is successively through described LPF module, comparator, control voltage
Produce circuit to be connected with the control end of described VGA module, the input termination input voltage of described VGA module, described VGA module
Outfan is divided into two-way, and the first via is voltage output end, and the second tunnel is connected with the input of described level detector, described comparison
One input termination reference voltage of device.
Attenuator circuit, radiofrequency signal generation processing unit, in order to ensure the accuracy of final output signal power, passes through AGC
Circuit makes it export and is fixed in a certain signal power (being typically selected in 0dbm).Last output be-180dBW～-
120dBW, power step value is 0.5dB, it is therefore necessary to introduces attenuator circuit and declines the signal power after agc circuit
Subtract, to meet output power signal requirement.
LO (local oscillator) module, LO module is for producing the high-frequency local oscillation signal required for up-conversion.
Signal power control parameter and interface: control signal transmission means: control signal is processed single by intermediate-freuqncy signal generation
Unit produces, and can be selected for I2C bus and realizes the data transmission between itself and radiofrequency signal generation processing unit microcontroller.I2C passes
Three lines of defeated need, are clock line, data wire and ground wire respectively, simple in construction, save space, interface module and each mould
Communicating between the microcontroller of block the most fairly simple, the transmission quantity of data is the least.
Combiner: combiner is used for realizing the output of multiple signals combination in any, and the analogue system selected due to user is different
(the multiple combination mode such as single system, multisystem, single-frequency point, multifrequency point), it is therefore desirable to pass through on-off control by on-off circuit
Whether the signal of a certain frequency exports, and this control signal is produced processing unit by corresponding data wire via penetrating by intermediate-freuqncy signal
The break-make of signal is controlled by the untreated device during signal produces processing unit frequently.
Claims (10)
1. a satellite navigation receiver test platform, it is characterised in that: include intermediate-freuqncy signal mod subsystem, Radio Frequency Subsystem
And host computer, it is connected by pci interface between described host computer with intermediate frequency Modulation subsystem, described intermediate frequency Modulation subsystem
Intermediate-freuqncy signal outfan is connected with the signal input part of described Radio Frequency Subsystem, the RF signal output of described Radio Frequency Subsystem
Being connected with the radio-frequency (RF) signal input end of tested satellite navigation receiver, described tested satellite navigation receiver is upper with described
It is attached by serial ports between machine；Described host computer is for man-machine interaction and calculates various emulation signal condition parameter and navigation
Text, produces the output of base band level data, is sent to intermediate frequency Modulation subsystem in real time and receives tested satellite navigation receiver and send out
The positioning result sent back to the performance resolving indices according to the data received, complete satellite navigation receiver function and property
Can test；Intermediate frequency Modulation subsystem has been used for the generation of analog if signal and the output specified；Radio Frequency Subsystem is used for will
Intermediate-freuqncy signal upconverts to the frequency specified, and carries out power control, and exports to tested satellite navigation through radio-frequency (RF) switch conjunction road
Receiver.
2. satellite navigation receiver test platform as claimed in claim 1, it is characterised in that: described intermediate-freuqncy signal modulation subsystem
System includes several intermediate-freuqncy signal generation modules.
3. satellite navigation receiver test platform as claimed in claim 2, it is characterised in that: described intermediate-freuqncy signal generation module
Including pci interface module, FPGA module, DSP module, DAC module, SRAM module and power transfer module, described pci interface
Module is bi-directionally connected with described FPGA module, for realizing the data friendship of described intermediate-freuqncy signal generation module and described host computer
Mutually；Described DSP module is bi-directionally connected with described FPGA module；DAC module is connected with the signal output part of described FPGA module；
DSP module is bi-directionally connected with described Radio Frequency Subsystem；Described FPGA module has been used for the generation of signal, it is achieved workflow and
Data interaction；Described DSP module processes for host computer is transmitted the data come, and calculates the control generated needed for intermediate-freuqncy signal
Word processed；Described DAC module is controlled by described FPGA module, is used for realizing digital-to-analogue conversion and up-conversion；Described power transfer module
It is connected with the power input of the module needing power supply in described signal generator module, for providing working power for it；Described
SRAM module is bi-directionally connected with described FPGA module, for data cached.
4. satellite navigation receiver test platform as claimed in claim 3, it is characterised in that: described FPGA module is selected
XC6VLX240T-1FFG1156 in the V6 series of XILINX company；DSP module selects the TMS320C6713B-of TI company
225 chips；DAC module selects AD9779A；Power module selects the SN74CB3T16211 of TI company, and SRAM module is selected
The IS61WV102416BLL chip of ISSI company.
5. satellite navigation receiver test platform as claimed in claim 3, it is characterised in that: described power module includes first
To the 5th independent power source module, the input of described first independent power source module and the second independent power source module terminates 12V input power, described
The output voltage of the first independent power source module is 2.5V, and the outfan of the first independent power source module is divided into two-way, the first via and second point
The power input of power module connects, and the second tunnel is connected with a power input of FPGA, described second independent power source module
Output voltage be 1V, the power output end of described second independent power source module is connected with a power input of FPGA；3rd
The input termination 12V input power of independent power source module, the output voltage of the 3rd independent power source module is 3.3V, the 3rd independent power source module
Power output end be connected with a power input of DSP；The input termination 3.3V power supply of the 4th and the 5th independent power source module,
The output voltage of the 4th independent power source module is 1.2V, and the outfan of the 4th independent power source module is divided into two-way, the first via and the one of DSP
Individual power input connects, and the second tunnel is connected with a power input of FPGA；The output voltage of the 5th independent power source module is
1.8V, in the outfan of the 5th independent power source module and intermediate-freuqncy signal generation module, the power supply of the module in addition to FPGA and DSP is defeated
Enter end to connect.
6. satellite navigation receiver test platform as claimed in claim 5, it is characterised in that: described first independent power source module bag
Including PTR08100W type power supply chip U35,1 foot of described U35 is unsettled, and 2 feet of described U35 meet 12V input power, electric capacity C258
Being connected in parallel between the input of power supply and ground, the 3 foot ground connection of described U35,5 feet of described U35 are through resistance R180 ground connection；Described
4 feet of U35 are divided into three tunnels, and the first via is through electric capacity C256 ground connection, and the second tunnel is through electric capacity C257 ground connection, and the 3rd tunnel is after connector J8
Being divided into again three tunnels, first via ground connection after resistance R178 and light emitting diode D21 successively, the second tunnel is described first independent power source mould
One power output end of block, the 3rd tunnel is another power output end of described first part of power module, described first point of electricity
Two output voltages of source module are 2.5V；
Described second independent power source module includes PTH04T240W type power supply chip U36, and the 1 of described U36,3,4,7 foot ground connection are described
2 feet of U36 are connected with a power output end of described first independent power source module, and 5 feet and 6 feet of described U36 are divided into two-way, the
One tunnel connects 9 feet of described U36 through electric capacity C261 ground connection, the second tunnel through resistance R175, and 8 feet of described U36 are through resistance R181 ground connection；
10 feet of described U36 are connected with 2 feet of described U36, and the power input of described U36 is parallel with electric capacity C259 and electric capacity C260,
11 feet of described U36 are unsettled, and the node of resistance R175 and electric capacity C261 is divided into two-way, the first via through electric capacity C262 ground connection, second
Road is divided into again two-way after connector J9, and the first via is a power output end of described second independent power source module, and the second tunnel is
Another power output end of second independent power source module；
Described 3rd independent power source module includes that 1 foot of TPS73801 type power supply chip U39, described U39 connects 12V input power, filter
Ripple electric capacity C269 is connected in parallel on the power input of described U39,3 feet of described U39 and 6 foot ground connection, and 5 feet of described U39 connect
2 feet of VCC, described U39 are divided into three tunnels, and first via ground connection after resistance R184, resistance R187 successively, the second tunnel is through electric capacity C268
Rear ground connection, the 3rd tunnel is divided into two-way after patch plug J12, and the first via is the power output end of described second independent power source module, the
Two tunnels ground connection after resistance R185, light emitting diode D23 successively；
Described 4th independent power source module includes that the 1-4 foot of ADP1740 type power supply chip U37, described U37 and 15-16 foot are divided into
Two-way, the first via connects 3.3V input power, and the second tunnel connects 1.2V input power through resistance R182, and 3.3V power input is provided with
5 feet of filter capacitor C263, described U37 connect 1.2V input power, the 6 foot ground connection of described U37,7 foot meridian capacitors of described U37
Ground connection after C265,8 feet of described U37 are unsettled, and the 9-11 foot of described U37 is connected with 12 feet of described U37,12 feet of described U37
Being divided into two-way, the first via is connected with 13 feet and 14 feet of described U37 respectively, and the second tunnel is divided into two-way after patch plug J10, and first
Road is a power output end of described 4th independent power source module, and the second tunnel is another power supply of described 4th independent power source module
Outfan；
Described 5th independent power source module includes that 5 feet of LT1963A type power supply chip U34, described U34 and 8 feet connect and input into power supply
End, 4 feet that described electric capacity input is provided with filter capacitor C254, described U34 are unsettled, the 3 of described U34,6,7 foot ground connection, institute
2 feet and 1 foot of stating U34 connect, and 1 foot of described U34 is divided into three tunnels, and the first via is through electric capacity C255 ground connection, and the second tunnel is successively through electricity
Ground connection after resistance R176 and light emitting diode D20, the 3rd tunnel is the power output end of described 5th independent power source module.
7. satellite navigation receiver test platform as claimed in claim 3, it is characterised in that: DSP includes that control word is posted
Buffer module, code NCO control word generation module, satellite number and chip select control word generation module, navigation message generation module,
Amplitude control words generation module and carrier wave NCO control word generation module；FPGA includes yard NCO generation module, frequency divider, a spread spectrum
Code generation module, subcarrier generation module, enumerator, FIFO generation module, band spectrum modulation module, carrier wave NCO generation module and
Orthogonal modulation module, the outfan of described control word register module respectively with described code NCO control word generation module, satellite number
Control word generation module, navigation message generation module, the input of amplitude control words generation module is selected to connect with chip, described
Code NCO control word generation module outfan be connected with the input of described frequency divider through described code NCO generation module, described in defend
Asterisk and chip select the outfan of control word generation module to be connected with the input of described spread spectrum code generation module, described frequency dividing
One outfan of device is connected with an input of described spread spectrum code generation module, another outfan warp of described frequency divider
Described subcarrier generation module is connected with an input of described band spectrum modulation module, an output of spread spectrum code generation module
End is connected with an input of described band spectrum modulation module, and another outfan of described spread spectrum code generation module is through described meter
Number device is connected with an input of described fifo module, the outfan of described navigation message generation module and described fifo module
Input connect, the outfan of described fifo module is connected with an input of described band spectrum modulation module, described
The outfan of amplitude control words generation module is connected with an input of described band spectrum modulation module, and described carrier wave NCO controls
Word generation module two inputs with described orthogonal modulation module after described carrier wave NCO generation module are connected, described spread spectrum
The outfan of modulation module is connected with an input of described orthogonal modulation module, an output of described orthogonal modulation module
End is I branch road, and another outfan is Q branch road, and I branch road and Q branch road are connected with the input of described DAC module.
8. satellite navigation receiver test platform as claimed in claim 1, it is characterised in that: if described Radio Frequency Subsystem includes
Dry individual up-converter module, power module, crystal oscillator and combiner, the input of described up-converter module is modulated with described intermediate-freuqncy signal
The intermediate-freuqncy signal outfan of subsystem connects, and needs the power supply of the module of power supply in described power module and described Radio Frequency Subsystem
Input connects, for providing working power, the outfan of described up-converter module to connect with the input of described combiner for it
Connecing, the outfan of described combiner is the signal output part of described Radio Frequency Subsystem, and described crystal oscillator is that described Radio Frequency Subsystem carries
For work clock, described up-converter module and combiner are controlled by described intermediate-freuqncy signal mod subsystem.
9. satellite navigation receiver test platform as claimed in claim 8, it is characterised in that: described up-converter module includes micro-
Controller, LO module, I/Q modulator, wave filter, AGC module and attenuation network module, the signal input part of described I/Q modulator
It is connected with the intermediate-freuqncy signal outfan of intermediate-freuqncy signal mod subsystem, the input termination crystal oscillator input of described LO module, described LO
The outfan of module is connected with the control end of described I/Q modulator, the most filtered device of outfan of described I/Q modulator, AGC mould
Block is connected with the input of described attenuation network module, and the outfan of described attenuation network module is RF signal output, institute
State the control output end of the microprocessor control end respectively with described LO module and attenuation network module to be connected, described microcontroller
Device is connected with described intermediate-freuqncy signal mod subsystem, the control command of receiving intermediate frequency signal mod subsystem output.
10. satellite navigation receiver test platform as claimed in claim 9, it is characterised in that: described AGC module includes level
Cymoscope, LPF module, comparator, control voltage generating module and VGA module, the outfan of described level detector warp successively
Described LPF module, comparator, control voltage generation circuit are connected with the control end of described VGA module, described VGA module defeated
Entering and terminate input voltage, the outfan of described VGA module is divided into two-way, and the first via is voltage output end, the second tunnel and described electricity
The input of flat cymoscope connects, an input termination reference voltage of described comparator.
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| CN201610581292.1A CN106199649A (en) | 2016-07-22 | 2016-07-22 | Satellite navigation receiver test platform |
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| CN106772464A (en) * | 2016-12-27 | 2017-05-31 | 天津七六四通信导航技术有限公司 | A kind of universal satellite navigation receiver test platform and method of testing |
| CN109343092A (en) * | 2018-08-31 | 2019-02-15 | 深圳市广和通无线股份有限公司 | Performance test methods, device, electronic equipment and storage medium |
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