CN1877833A - U-grooved integrated chip and method for fabricating same - Google Patents
U-grooved integrated chip and method for fabricating same Download PDFInfo
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- CN1877833A CN1877833A CNA2006100355269A CN200610035526A CN1877833A CN 1877833 A CN1877833 A CN 1877833A CN A2006100355269 A CNA2006100355269 A CN A2006100355269A CN 200610035526 A CN200610035526 A CN 200610035526A CN 1877833 A CN1877833 A CN 1877833A
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Abstract
The invention discloses a U-groove LED integrated chip and making method, which consists of several LED naked chips and silicon substrate, wherein the LED naked chip contains N-typed epitaxial film, P-typed epitaxial film; two metal layers are set at LED naked chip position of silicon substrate roof, which are welded on the metal layer through welding ball or metal welding wire; two separation layers I are set in the connecting region of metal layer and silicon substrate with several U-shaped flutes; the LED naked chip lies in the flute, which connects each other through metal layer to lead positive and negative electrode joints; the resin is filled in the flute; the metal layer is covered on the bottom of flute and lateral, whose outer surface is reflecting plane; the separation layer II is set between metal layer and silicon substrate. The making method comprises the following steps: forming screening layer, flute, oxide layer, separating layer, metal layer and protective layer; welding LED.
Description
Technical field
The present invention relates to a kind of U grooved integrated chip and manufacture method.
Background technology
Flip chip technology (fct) is one of current state-of-the-art microelectronic packaging technology, and it is a kind of chip interconnect technology, is again a kind of desirable die bonding technology, and it has risen to a new height with the circuit packaging density.In all surface mounting technique, flip-chip can reach minimum, the thinnest encapsulation, and along with further dwindling of electronic product volume, the application of flip-chip will be more and more widely.
The packing forms that the LED bare chip is tipped upside down on the silicon substrate is called flip LED.Traditional flip LED is a planarized structure; as shown in Figure 1; it comprises LED bare chip and silicon substrate 2; described LED bare chip is by substrate 10 and N type epitaxial loayer 11; P type epitaxial loayer 12 is formed; described silicon substrate 2 end faces have the depositing metal layers 30 of two separation; 31; described P type epitaxial loayer 12; described N type epitaxial loayer 11 is respectively by soldered ball 40; 41 are welded on described metal level 30; on 31; described metal level 30; 31 with the land of described silicon substrate 2 also have respectively one with described silicon substrate 2 opposite polarity separators 20; 21; be used to isolate described metal level 30; 31 with described silicon substrate 2, play the effect of protection.The PN junction of this traditional flip LED all can be luminous on positive, side and bottom surface, but because the light that send side and bottom surface all is scattered away, thereby be not fully utilized, and causes the luminous efficiency of LED lower, makes the front go out light intensity and reduce.
The formal dress chip technology is traditional microelectronic packaging technology, its technology maturation, and range of application is the most extensive.Present most LED is forward LED, LED bare chip formal dress is on a support that has a reflector, its P type epitaxial loayer, N type epitaxial loayer are welded on anode and the cathode leg by metal wire respectively, though this forward LED has reflector, but the light of mirrored sides makes it penetrate from the front, but effect is still good inadequately, and positive bright dipping meeting is covered by the metal bonding wire, when being heat-insulating material as substrate, its poor radiation.Simultaneously, this forward LED is difficult realizes that the multicore sheet is integrated.
Existing power-type LED chip all is to adopt a LED bare chip, and its manufacturing cost is higher, and luminous efficiency is lower; Its all heats all are by several soldered balls or bonding wire heat loss through conduction, because chip area is bigger, thermal source is concentrated, so radiating effect is bad.
Summary of the invention
Technical problem to be solved by this invention is the deficiency that overcomes on the prior art, the U grooved integrated chip of a kind of low cost of manufacture, luminous efficiency height, good heat dissipation effect is provided and makes the method for this integrated chip.
The technical scheme that U grooved integrated chip of the present invention is adopted is: U grooved integrated chip of the present invention comprises several LED bare chip and silicon substrates, described LED bare chip comprises substrate and N type epitaxial loayer, P type epitaxial loayer, described silicon substrate end face has the depositing metal layers of two separation in each described LED bare chip place, described P type epitaxial loayer, described N type epitaxial loayer is welded on the described metal level by solder-ball flip or by the metal wire formal dress respectively, the land of described metal level and described silicon substrate also has the separator I of a doping respectively, described silicon substrate upper surface has several U type grooves, several described LED bare chip correspondences are positioned at several described U type grooves, be connected by described metal level between several described LED bare chips and draw anode contact and cathode contact, the potting resin that transparent insulation is arranged in the described U type groove, described metal level is covered in the bottom surface and the side of each described U type groove, the outer surface of described metal level is a reflective surface, is provided with separator II between the described metal level of each described LED bare chip correspondence and the described silicon substrate.
Parallel connection or series connection or connection in series-parallel are connected between several described LED bare chips.
Described silicon substrate is＜100〉crystal orientation silicon substrate, and described U type groove is the truncated rectangular pyramids shape, and the angle between each side of described U type groove and the described silicon substrate end face is 54.7 °.
U groove flip-chip LED integrated chip of the present invention also comprises protective layer, and described protective layer is covered in described metal level outer surface.
Described silicon substrate is P type or N type, described separator I is opposite with described silicon substrate polarity, is mixed with fluorescent material in the described potting resin, and described soldered ball is gold goal bolt or copper ball bolt or tin ball, described metal wire is gold thread or aluminum steel or copper cash, and described metal level is metallic aluminium or silicon-aluminum.
The technical scheme that manufacture method adopted of U groove flip-chip LED integrated chip of the present invention is: it may further comprise the steps:
(a) form masking layer: the upper surface of the described silicon substrate with＜100〉crystal orientation grows oxide layer I at oxidation boiler tube internal heating oxidation, on mask aligner, utilize U groove lay photoetching mask plate to carry out photoetching then, form litho pattern, during photoetching the frame line of figure must with described silicon substrate wafer it＜011〉main flat edge direction parallel, with the corrosive liquid that contains HF the described litho pattern of oxide layer I is partly carried out etching again, remove the oxide layer I in the described litho pattern part, remaining oxide layer I constitutes masking layer; Perhaps
The upper surface of first general's＜100〉crystal orientation described silicon substrate is after oxidation boiler tube internal heating oxidation grows oxide layer II, grow silicon nitride film with Low Pressure Chemical Vapor Deposition again, on mask aligner, utilize U groove lay photoetching mask plate to carry out photoetching then, form litho pattern, during photoetching the frame line of figure must with described silicon substrate wafer it＜011〉main flat edge direction parallel, use the dry etching silicon nitride again, then with wet etching oxide layer II, remove silicon nitride film and oxide layer II in the described litho pattern part, residual silicon nitride film and oxide layer II constitute masking layer;
(b) form U type groove: utilize masking layer, described silicon substrate is carried out anisotropic etch, erode away＜111〉crystal orientation silicon face, form the described U type groove that several sides and end face are 54.7 ° with KOH or NaOH solution;
(c) form separator II: grow oxide layer III at oxidation boiler tube internal heating oxidation, on mask aligner, utilize the diffusion lay photoetching mask plate to carry out photoetching, adopt negative photoresist during photoetching, with the corrosive liquid that contains HF oxide layer III is carried out etching again, remove the oxide layer III in the litho pattern part, remaining oxide layer III constitutes described separator II;
(d) form separator I: thermal diffusion forms several described separator I in high temperature dispersing furnace;
(e) form metal level: with the method depositing metal layers I of sputter or evaporation, on mask aligner, utilize the metal lithographic mask to carry out photoetching then, adopt negative photoresist during photoetching, with wet method or dry method etch technology metal level I is carried out etching again, remaining metal level I formation serial or parallel connection or connection in series-parallel are connected after the etching described metal level and anode contact and cathode contact;
(f) form protective layer: with chemical vapour deposition technique deposition of silica or silicon nitride protective layer, on mask aligner, utilize the sheath lay photoetching mask plate to carry out photoetching then, with the corrosive liquid that contains HF silicon dioxide is carried out etching or silicon nitride is carried out etching with dry method again, make protective layer two openings that are used to plant soldered ball or bonding wire occur;
(g) LED bare chip encapsulation: plant gold goal bolt or copper ball bolt or tin ball in the opening of protective layer, again by ultrasonic bonding with several LED bare chip upside-down mountings on gold goal bolt or copper ball bolt or tin ball, perhaps, with the bottom of LED bare chip formal dress at described U type groove, the described metal wire that will connect the LED solder joint again is welded on the described metal level in two openings of protective layer with elargol;
(h) embedding potting resin: resin material is filled embedding go in each described U type groove, form described potting resin.
The invention has the beneficial effects as follows: because the described silicon substrate upper surface of U grooved integrated chip of the present invention has several U type grooves, several described LED bare chip correspondences are positioned at several described U type grooves, described metal level is covered in the bottom surface and the side of described U type groove, the light that the PN junction of described LED bare chip sends in side and bottom surface runs into the side of described groove and described metal level that the bottom surface covers can reflect, the light of reflection penetrates from the front again, like this, it no matter is front from PN junction, the bottom surface still is that the light that sends of side has all obtained effective utilization, can not cause the waste of side and bottom surface light, improved luminous efficiency, so U grooved integrated chip luminous efficiency height of the present invention, the front goes out the luminous intensity height; Owing to being connected by described metal level between several described LED bare chips of U grooved integrated chip of the present invention and drawing anode contact and cathode contact, a plurality of described LED bare chip distribution areas are wide, illumination effect is better, and manufacturing cost is lower than the power-type LED chip that adopts a LED bare chip, each described LED bare chip passes to described metal level by two described soldered balls or the metal wire that joins with it with heat, and heat is passed to described silicon substrate by described separator, the area of described metal level is bigger, the bottom surface and the side of described U type groove have been covered, thermal source disperses, good heat dissipation effect, so long service life is U grooved integrated chip luminous efficiency height of the present invention, good heat dissipation effect, long service life; In like manner, adopt the U grooved integrated chip of manufacture method manufacturing of the present invention to have above-mentioned advantage, and this method technology is easy, good product quality.
Description of drawings
Fig. 1 is the structural representation of traditional flip-chip LED integrated chip;
Fig. 2 is the plane arrangement structure schematic diagram of the embodiment of the invention one U grooved integrated chip;
Fig. 3 is the circuit theory diagrams of U grooved integrated chip shown in Figure 2;
Fig. 4 is the plane arrangement structure schematic diagram of the embodiment of the invention two U grooved integrated chips;
Fig. 5 is the circuit theory diagrams of U grooved integrated chip shown in Figure 4;
Fig. 6 is the plane arrangement structure schematic diagram of the embodiment of the invention three U grooved integrated chips;
Fig. 7 is the circuit theory diagrams of U grooved integrated chip shown in Figure 6;
Fig. 8 is the plane arrangement structure schematic diagram of the embodiment of the invention four U grooved integrated chips;
Fig. 9 is the circuit theory diagrams of U grooved integrated chip shown in Figure 8;
Figure 10 is the A-A cross-sectional view of Fig. 2, Fig. 4, Fig. 6, U groove flip-chip LED integrated chip shown in Figure 8;
Figure 11 is the structural representation after the manufacture method step (a) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 12 is the structural representation after the manufacture method step (b) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 13 is the structural representation after the manufacture method step (c) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 14 is the structural representation after the manufacture method step (d) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 15 is the structural representation after the manufacture method step (e) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 16 is the structural representation after the manufacture method step (f) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 17 is the structural representation after the manufacture method step (g) of U groove flip-chip LED integrated chip of the present invention is finished;
Figure 18 is the A-A cross-sectional view of Fig. 2, Fig. 4, Fig. 6, U groove forward LED integrated chip shown in Figure 8.
Embodiment
Embodiment one:
As Fig. 2, Fig. 3, shown in Figure 10, the U groove flip-chip LED integrated chip of present embodiment comprises nine LED bare chips 1 and silicon substrate 2, and described LED bare chip 1 comprises sapphire (Al
2O
3) substrate 10 and gallium nitride (GaN) N type epitaxial loayer 11, P type epitaxial loayer 12, certainly, described substrate 10 also can be the substrate of carborundum other materials such as (SiC), described silicon substrate 2 is＜100〉crystal orientation P type silicon substrate, described silicon substrate 2 upper surfaces have nine U type grooves, and each described LED bare chip 1 lays respectively in each described U type groove.Described silicon substrate 2 end faces have the depositing metal layers 32 of two separation in each described LED bare chip 1 place; 33; described metal level 32; 33 is metallic aluminium; can certainly adopt silicon-aluminum; described metal level 32; 33 are covered in the bottom surface and the side of described U type groove; described metal level 32; 33 outer surface is a reflective surface; described metal level 32; 33 be electrode be again the refractive body of side and bottom surface light; described P type epitaxial loayer 12; described N type epitaxial loayer 11 is respectively by soldered ball 40; 41 flip chip bondings are connected on described metal level 32; on 33; described soldered ball 40; 41 is the gold goal bolt; can certainly be copper ball bolt or tin ball; described metal level 32; 33 also have a Doping Phosphorus respectively with the land of described silicon substrate 2; the N type separator I 22 of materials such as arsenic; 23; be used to isolate described metal level 32; 33 with described silicon substrate 2; prevent described metal level 32; electric leakage or short circuit between 33; described separator I 22 of while; 23 and described silicon substrate 2 between also constitute an electrostatic protection diode; also can play the effect of electrostatic protection in encapsulation process; described separator 22 of while; 23 pass to described metal level 32 with described LED bare chip 1; 33 heat passes to described silicon substrate 2 again, plays good heat conduction; thermolysis.The potting resin 7 that transparent insulation is arranged in the described U type groove, be mixed with fluorescent material in the described potting resin 7, the blue light that described LED bare chip 1 sends through described Sapphire Substrate 10 encourages described fluorescent material to send sodium yellow, the light of two kinds of colors mixes, finally outwards send white light, between described metal level 32,33 and the described silicon substrate 2 a separator II 51,53 is arranged respectively, also have the separator II 52 that forms in the technical process between the described metal level 32,33.Described U groove flip-chip LED integrated chip also comprises protective layer 6, and described protective layer 6 is covered in described metal level 32,33 outer surfaces, and to prevent described metal level 32,33 short circuits, described protective layer 6 adopts silicon dioxide (SiO
2) material, can certainly adopt silicon nitride other materials such as (SiN).Described U type groove is positive truncated rectangular pyramids shape, and the angle between the side of described U type groove and described silicon substrate 2 end faces is 54.7 °, and certain described U type groove can be the truncated rectangular pyramids shape of rectangle for upper and lower bottom surface also.Certainly, described silicon substrate 2 also can be＜100〉the N type silicon substrate in crystal orientation, at this moment, described separator I 22,23 is the P type separator of materials such as doped with boron.Being in parallel by described metal level 32,33 between each described LED bare chip 1 connects and draws anode contact 80 and cathode contact 81, and all the LED bare chips 1 between promptly described anode contact 80 and the described cathode contact 81 are in parallel.
As Figure 10～shown in Figure 17, the manufacture method of the U groove flip-chip LED integrated chip of present embodiment may further comprise the steps:
(a) form masking layer: the upper surface of the described silicon substrate 2 with＜100〉crystal orientation grows the oxide layer I that thickness is 10000 dusts at oxidation boiler tube internal heating oxidation, the thickness range of described oxide layer I can be controlled in 2000～20000 dusts, on mask aligner, utilize U groove lay photoetching mask plate to carry out photoetching then, form litho pattern, during photoetching the frame line of figure must with described silicon substrate 2 wafers it＜011〉main flat edge direction parallel, otherwise when etching, have serious side etching and cause figure deformation, with the corrosive liquid that contains HF the described litho pattern of oxide layer I is partly carried out etching again, remove the oxide layer I in the described litho pattern part, remaining oxide layer I constitutes masking layer, and the last profile that forms of this step as shown in figure 11;
This step also can be replaced by following silicon nitride masking layer film process with the method for oxide layer as the masking layer diaphragm, that is:
The upper surface of first general's＜100〉crystal orientation described silicon substrate 2 is after oxidation boiler tube internal heating oxidation grows the oxide layer II that thickness is 350 dusts, the thickness range of described oxide layer II can be controlled in 200～500 dusts, grow the silicon nitride film that thickness is 1500 dusts with Low Pressure Chemical Vapor Deposition again, the thickness range of described silicon nitride film can be controlled in 1000～3000 dusts, on mask aligner, utilize U groove lay photoetching mask plate to carry out photoetching then, form litho pattern, during photoetching the frame line of figure must with described silicon substrate 2 wafers it＜011〉main flat edge direction parallel, use the dry etching silicon nitride again, then with wet etching oxide layer II, remove silicon nitride film and oxide layer II in the described litho pattern part, residual silicon nitride film and oxide layer II constitute masking layer, and the profile of Xing Chenging as shown in figure 11 at last;
(b) form U type groove: utilize masking layer, with temperature is 65 ℃, concentration is that 55% KOH solution carries out anisotropic etch to described silicon substrate 2, erode away＜111〉crystal orientation silicon face, form the described U type groove that nine sides and end face are 54.7 °, the degree of depth of described U type groove is controlled at 50～200 microns, the temperature of described KOH solution is controlled at 40～90 ℃, concentration is controlled at 30%～80% and all can, described KOH solution also can replace with NaOH solution, the formation of described U type groove has utilized KOH or the NaOH different characteristic of etch-rate on the silicon face of different crystal orientations, promptly adopted anisotropic etching, the last profile that forms of this step as shown in figure 12;
(c) form separator II: remove masking layer with the corrosive liquid that contains HF, grow the oxide layer III that thickness is 3000 dusts at oxidation boiler tube internal heating oxidation then, the thickness range of described oxide layer III can be controlled in 1000～5000 dusts, on mask aligner, utilize the diffusion lay photoetching mask plate to carry out photoetching, the bottom surface of described U type groove and the upper surface of described silicon substrate 2 are positioned at two Different Plane, simultaneously resolved during photoetching for reaching two table tops, adopt negative photoresist to replace integrated circuit positive photoetching rubber commonly used, and negative photoresist is easy to realize litho pattern than positive photoetching rubber, with the corrosive liquid that contains HF oxide layer III is carried out etching again, remove the oxide layer III in the litho pattern part, remaining oxide layer III constitutes described separator II 51,52,53, described separator II 52 might be etched in technical process, but do not exert an influence for product, the last profile that forms of this step as shown in figure 13;
(d) form separator I: thermal diffusion forms described separator I 22,23 in high temperature dispersing furnace, described separator I 22,23 will make two electrodes of LED be in isolation, avoid the short circuit electric leakage, simultaneously led chip can be dispelled the heat by silicon chip, the last profile that forms of this step as shown in figure 14;
(e) form metal level: the method deposit thickness with sputter or evaporation is the metal level I of 12000 dusts, the thickness range of described metal level I can be controlled in 5000～40000 dusts, on mask aligner, utilize the metal lithographic mask to carry out photoetching then, the same employing born photoresist during photoetching, the dry method etch technology of commonly using with semiconductor technology is carried out etching to metal level I again, certainly, also can adopt wet etching that metal level I is carried out etching, remaining metal level I constitutes the described metal level 32 that is connected in parallel after the etching, 33 and anode contact 80 and cathode contact 81, the last profile that forms of this step as shown in figure 15;
(f) form protective layer: with the chemical vapour deposition technique deposit thickness is the silicon dioxide layer of protection of 12000 dusts, the thickness range of described silicon dioxide layer of protection can be controlled in 8000～15000 dusts, described silicon dioxide layer of protection also can adopt silicon nitride protective layer to substitute, on mask aligner, utilize the sheath lay photoetching mask plate to carry out photoetching then, with the corrosive liquid that contains HF silicon dioxide is carried out etching or silicon nitride is carried out etching with dry method again, make protective layer two openings that are used to plant soldered ball occur in each described U type groove, the last profile that forms of this step as shown in figure 16;
(g) LED bare chip upside-down mounting: plant gold goal and be bolted in the opening of protective layer, again by ultrasonic bonding with each described LED bare chip 1 upside-down mounting on the gold goal bolt, certainly the gold goal bolt also can adopt copper ball bolt or tin ball, the last profile that forms of this step as shown in figure 17;
(h) embedding potting resin: the resin material filling embedding that will be mixed with fluorescent material is gone in each described U type groove, forms described potting resin 7, and the last profile that forms of this step as shown in figure 10.
Embodiment two:
As Fig. 4, Fig. 5, Figure 10～shown in Figure 17, present embodiment is with the difference of embodiment one: between each described LED bare chip 1 by described metal level 32,33 connected mode---being in series between each described LED bare chip 1 of present embodiment is connected, and all the LED bare chips 1 between promptly described anode contact 80 and the described cathode contact 81 are in series.All the other are identical with embodiment one.
Embodiment three:
As Fig. 6, Fig. 7, Figure 10～shown in Figure 17, the difference of present embodiment and embodiment one is: the connected mode by described metal level 32,33 between each described LED bare chip 1---between each described LED bare chip 1 of present embodiment earlier per three be connected into one group, again with three groups of connections that are in parallel.All the other are identical with embodiment one.
Embodiment four:
As Fig. 8～shown in Figure 17, the difference of present embodiment and embodiment one is: the connected mode by described metal level 32,33 between each described LED bare chip 1---between each described LED bare chip 1 of present embodiment earlier per three and be unified into one group, and again with three groups of connections that are in series.All the other are identical with embodiment one.
Embodiment five:
As Fig. 2～Fig. 9, shown in Figure 180, the difference of present embodiment and embodiment one～four is: the described LED bare chip 1 of each of the U grooved integrated chip of present embodiment is formal dress encapsulation pattern, with elargol 9 with the bottom of LED bare chip 1 formal dress at described U type groove, the described metal wire 45,46 that will connect the described P type epitaxial loayer 12 of LED bare chip 1, described N type epitaxial loayer 11 solder joints again is welded on the described metal level 32,33 in two openings of protective layer, described metal wire 45,46 is a gold thread, can certainly be aluminum steel or copper cash; Connected mode by described metal level 32,33 between each described LED bare chip 1 is that serial or parallel connection or connection in series-parallel are connected; Described separator II is made up of oxide layer 54,55,56,57 and silicon nitride layer 84,85,86,87.
The described LED bare chip 1 of U grooved integrated chip of the present invention and the quantity of described U type groove are not limited to nine, only illustrate among the embodiment.
U grooved integrated chip of the present invention is integrated in several described LED bare chips 1 on the described silicon substrate 2, luminous efficiency height, good heat dissipation effect, long service life.
The present invention can be widely used in the LED field.
Claims (6)
1, a kind of U grooved integrated chip, comprise several LED bare chips (1) and silicon substrate (2), described LED bare chip comprises substrate (10) and N type epitaxial loayer (11), P type epitaxial loayer (12), described silicon substrate (2) end face has the depositing metal layers (32 of two separation in each described LED bare chip place, 33), described P type epitaxial loayer (12), described N type epitaxial loayer (11) is respectively by soldered ball (40,41) upside-down mounting or by metal wire (45,46) formal dress is welded on described metal level (32,33) on, described metal level (32,33) also has the separator I (22 of a doping respectively with the land of described silicon substrate (2), 23), it is characterized in that: described silicon substrate (2) upper surface has several U type grooves, several described LED bare chip correspondences are positioned at several described U type grooves, pass through described metal level (32 between several described LED bare chips, 33) be connected and draw anode contact (80) and cathode contact (81), the potting resin (7) that transparent insulation is arranged in the described U type groove, described metal level (32,33) be covered in the bottom surface and the side of each described U type groove, described metal level (32,33) outer surface is a reflective surface, the described metal level (32 of each described LED bare chip correspondence, 33) and between the described silicon substrate (2) be provided with separator II.
2, U grooved integrated chip according to claim 1 is characterized in that: parallel connection or series connection or connection in series-parallel are connected between several described LED bare chips.
3, U grooved integrated chip according to claim 1 and 2, it is characterized in that: described silicon substrate (2) is＜100〉crystal orientation silicon substrate, described U type groove is the truncated rectangular pyramids shape, and the angle between each side of described U type groove and described silicon substrate (2) end face is 54.7 °.
4, U grooved integrated chip according to claim 1 and 2 is characterized in that: it also comprises protective layer (6), and described protective layer (6) is covered in described metal level (32,33) outer surface.
5, U grooved integrated chip according to claim 1 and 2, it is characterized in that: described silicon substrate (2) is P type or N type, described separator I (22,23) is opposite with described silicon substrate (2) polarity, described potting resin is mixed with fluorescent material in (7), described soldered ball (40,41) is gold goal bolt or copper ball bolt or tin ball, described metal wire (45,46) is gold thread or aluminum steel or copper cash, and described metal level (32,33) is metallic aluminium or silicon-aluminum.
6, a kind of method that is used to make the described U grooved integrated chip of claim 1 is characterized in that: may further comprise the steps:
(a) form masking layer: the upper surface of the described silicon substrate (2) with＜100〉crystal orientation grows oxide layer I at oxidation boiler tube internal heating oxidation, on mask aligner, utilize U groove lay photoetching mask plate to carry out photoetching then, form litho pattern, during photoetching the frame line of figure must with described silicon substrate (2) wafer it＜011〉main flat edge direction parallel, with the corrosive liquid that contains HF the described litho pattern of oxide layer I is partly carried out etching again, remove the oxide layer I in the described litho pattern part, remaining oxide layer I constitutes masking layer; Perhaps
The upper surface of first general's＜100〉crystal orientation described silicon substrate (2) is after oxidation boiler tube internal heating oxidation grows oxide layer II, grow silicon nitride film with Low Pressure Chemical Vapor Deposition again, on mask aligner, utilize U groove lay photoetching mask plate to carry out photoetching then, form litho pattern, during photoetching the frame line of figure must with described silicon substrate (2) wafer it＜011〉main flat edge direction parallel, use the dry etching silicon nitride again, then with wet etching oxide layer II, remove silicon nitride film and oxide layer II in the described litho pattern part, residual silicon nitride film and oxide layer II constitute masking layer;
(b) form U type groove: utilize masking layer, described silicon substrate (2) is carried out anisotropic etch, erode away＜111〉crystal orientation silicon face, form the described U type groove that several sides and end face are 54.7 ° with KOH or NaOH solution;
(c) form separator II: grow oxide layer III at oxidation boiler tube internal heating oxidation, on mask aligner, utilize the diffusion lay photoetching mask plate to carry out photoetching, adopt negative photoresist during photoetching, with the corrosive liquid that contains HF oxide layer III is carried out etching again, remove the oxide layer III in the litho pattern part, remaining oxide layer III constitutes described separator II;
(d) form separator I: thermal diffusion forms several described separator I (22,23) in high temperature dispersing furnace;
(e) form metal level: with the method depositing metal layers I of sputter or evaporation, on mask aligner, utilize the metal lithographic mask to carry out photoetching then, adopt negative photoresist during photoetching, with wet method or dry method etch technology metal level I is carried out etching again, remaining metal level I formation serial or parallel connection or connection in series-parallel are connected after the etching described metal level (32,33) and anode contact (80) and cathode contact (81);
(f) form protective layer: with chemical vapour deposition technique deposition of silica or silicon nitride protective layer, on mask aligner, utilize the sheath lay photoetching mask plate to carry out photoetching then, with the corrosive liquid that contains HF silicon dioxide is carried out etching or silicon nitride is carried out etching with dry method again, make protective layer two openings that are used to plant soldered ball or bonding wire occur;
(g) LED bare chip encapsulation: plant gold goal bolt or copper ball bolt or tin ball in the opening of protective layer, again by ultrasonic bonding with several LED bare chip upside-down mountings on gold goal bolt or copper ball bolt or tin ball, perhaps, with the bottom of LED bare chip formal dress at described U type groove, the described metal wire (45,46) that will connect the LED solder joint again is welded on the described metal level (32,33) in two openings of protective layer with elargol (9);
(h) embedding potting resin: resin material is filled embedding go in each described U type groove, form described potting resin (7).
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