CN1873756A - Sequential control circuit and method - Google Patents
Sequential control circuit and method Download PDFInfo
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- CN1873756A CN1873756A CN 200510073498 CN200510073498A CN1873756A CN 1873756 A CN1873756 A CN 1873756A CN 200510073498 CN200510073498 CN 200510073498 CN 200510073498 A CN200510073498 A CN 200510073498A CN 1873756 A CN1873756 A CN 1873756A
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- latch pulse
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Abstract
The invention is a sequential control circuit and the corresponding method thereof, for providing plural latch pulse signals for thin film transistor (TFT) display panel to avoid rewriting phenomenon. And the sequential control circuit is characterized in that: the latch pulse signals but the first latch pulse signal each synchronize with or lag behind the previous latch pulse signal and at least a latch pulse signal lags behind the previous latch pulse signal.
Description
Technical field
The present invention relates to a kind of sequential control circuit and method, and particularly relate to a kind of sequential control circuit and method that is applied to Thin Film Transistor-LCD (thin film transistor liquid crystal display abbreviates TFTLCD as).
Background technology
Please refer to Fig. 1, Figure 1 shows that a traditional TFT LCD panel 100 and relevant drive signal sequential chart.TFT LCD panel 100 comprises eight source electrode drivers (source driver) SD1～SD8 and three gate drivers (gate driver) GD1～GD3.Whenever the negative edge (falling edge) of latch pulse signal (latch pulse) LP, source electrode driver SD1～SD8 will send the required pixel of display frame (pixel) signal S-Line.And gate drivers GD1～GD3 can send grid impulse signal (gate pulse), allows picture element signal S-Line enter corresponding gate line (gate line).In the middle of Fig. 1, G1 is the grid impulse signal of article one gate line, and its pulse corresponds to the Data_G1 part of picture element signal S-Line, the just displaying contents of article one gate line; And G2 is the grid impulse signal of second gate line, and its pulse corresponds to the Data_G2 part of picture element signal S-Line, the just displaying contents of second gate line.
The shortcoming of prior art is that phenomenon can take place to write again, is example with the TFT LCD panel 100 of Fig. 1, and zone 101 is exactly the zone that easy generation writes phenomenon again.To be grid impulse signal G1, G2 be delivered to the process on right side from the left side of TFT LCD panel 100 its reason, can be subjected to the influence of line resistance and electric capacity and produce delay, makes that each thin film transistor (TFT) on the gate line is not to open at one time.Under the situation of the same grid impulse signal of input on same the gate line, more near TFT LCD panel 100 right sides, just more be in the late unlatching of can healing of the long-range thin film transistor (TFT) of gate line, also more close evening.
And,, therefore can send picture element signal S-Line simultaneously because source electrode driver SD1～SD8 accepts same latch pulse signal LP for source electrode driver SD1～SD8.That is to say that the pixel on same gate line can receive picture element signal S-Line at one time, this will cause and write phenomenon again, for example is denoted as the part of A1 in the middle of the picture element signal S-Line.Near the pixel on right side because of the delay (G1 delay after be represented by dotted lines) of grid impulse signal G1 as yet do not close on article one gate line this moment, and the data Data_G2 of second gate line has appearred in picture element signal S-Line.That is to say that the pixel on right side can write the data of Data_G1 and Data_G2 simultaneously, Here it is writes phenomenon again.
Write phenomenon again and can cause brightness disproportionation on the horizontal scanning line (scan line), have two kinds of methods to avoid at present.First method is as shown in Figure 2, utilizes grid shutdown signal OE to close pixel in advance, and its effect, does not have yet and writes phenomenon again even transmission delay is arranged just as the part that is denoted as A2.The shortcoming of but using grid shutdown signal OE is owing to close pixel in advance, must sacrifice the duration of charging of pixel, for the higher or larger-size TFT LCD of resolution panel, is easy to generate the phenomenon of undercharge.
Second kind of method of avoiding writing again phenomenon is to shift to an earlier date vertical clock signal (vertical clock does not show among the figure), and pixel is closed in advance.Its shortcoming is the same with first method, can produce the phenomenon of undercharge because close pixel in advance.
By above discussion as can be known, we need better method, to solve the problem that writes phenomenon and pixel undercharge more simultaneously.
Summary of the invention
The purpose of this invention is to provide a kind of sequential control circuit,, solve the problem that writes phenomenon and pixel undercharge more simultaneously to overcome the defective of prior art.Its advantage is dwindled thin-film transistor element for can increase the pixel duration of charging, increases aperture opening ratio.
Another object of the present invention provides a kind of sequential control method, to overcome the defective of prior art, solves the problem that writes phenomenon and pixel undercharge more simultaneously.Its advantage is for can increase the pixel duration of charging, and because the output time difference of each source electrode driver can reduce electromagnetic interference (EMI).
For reaching above-mentioned and other purpose, the present invention proposes a kind of sequential control circuit, export a plurality of latch pulse signals, above-mentioned sequential control circuit is characterised in that: in the middle of the above-mentioned latch pulse signal, except first latch pulse signal, each latch pulse signal all is synchronized with or lags behind previous latch pulse signal, and exists a latch pulse signal to lag behind previous latch pulse signal at least.
Above-mentioned sequential control circuit, in one embodiment, the quantity of latch pulse signal is two, and second latch pulse signal lags behind first latch pulse signal.
Above-mentioned sequential control circuit in one embodiment, also comprises time schedule controller (timingcontroller) and deferred mount.Time schedule controller is exported first latch pulse signal.Deferred mount receives first latch pulse signal, after postponing, produces and export second latch pulse signal.
Above-mentioned sequential control circuit, in one embodiment, above-mentioned deferred mount also comprises resistor, capacitor and impact damper.Resistor is electrically connected on the input end of deferred mount.Capacitor electrode is connected between resistor and the ground wire (ground).Impact damper is electrically connected between the output terminal of resistor, capacitor and deferred mount, receives the signal from the contact of resistor and capacitor, and this signal arrangement is output after the square wave.
Above-mentioned sequential control circuit, in one embodiment, except first latch pulse signal, each latch pulse signal all lags behind previous latch pulse signal.
Above-mentioned sequential control circuit also comprises time schedule controller and delay circuit in one embodiment.Time schedule controller is exported first latch pulse signal.Delay circuit produces and the latch pulse signal of output except first latch pulse signal according to first latch pulse signal.
Above-mentioned sequential control circuit also comprises a plurality of deferred mounts in one embodiment.The quantity of above-mentioned deferred mount is that the quantity of above-mentioned latch pulse signal subtracts one.Wherein first deferred mount is electrically connected on time schedule controller, and all the other I deferred mounts are electrically connected on I-1 deferred mount.I deferred mount receives I latch pulse signal, after postponing, produces and export I+1 latch pulse signal.Wherein I is a positive integer, and 1≤I≤N-1.N is the quantity of above-mentioned latch pulse signal.
From another viewpoint, the present invention proposes a kind of sequential control method in addition.The method provides a plurality of latch pulse signals, it is characterized in that: in the middle of the above-mentioned latch pulse signal, except first latch pulse signal, each latch pulse signal all is synchronized with or lags behind previous latch pulse signal, and exists a latch pulse signal to lag behind previous latch pulse signal at least.
The present invention providing to add postponing between the latch pulse signal of different source electrode drivers, cooperating the transmission delay of grid impulse signal, makes that the significant zone of grid impulse signal delay is also later receives corresponding picture element signal.At the grid impulse signal with under the delay of picture element signal cooperates, can effectively avoid writing again phenomenon, because of premature closure pixel unlike prior art, also can increase the pixel duration of charging simultaneously, and then reach the advantage of dwindling thin-film transistor element and increasing aperture opening ratio.In addition, because the output time difference of each source electrode driver can reduce electromagnetic interference (EMI).
For above and other objects of the present invention, feature and advantage can be become apparent, the present invention's cited below particularly preferred embodiment, and conjunction with figs. are described in detail below.
Description of drawings
The synoptic diagram of phenomenon takes place to write in Fig. 1 again for the display panels of prior art.
Fig. 2 writes the drive signal sequential chart of the method for phenomenon again for the solution of prior art.
Fig. 3 is the drive signal sequential chart that is pursuant to the sequential control circuit of one embodiment of the invention.
Fig. 4 to Fig. 6 is the synoptic diagram that is pursuant to the sequential control circuit of different embodiments of the invention.
Fig. 7 is the synoptic diagram that is pursuant to the deferred mount in the middle of the sequential control circuit of one embodiment of the invention.
Fig. 8 is the signal timing diagram of the deferred mount in the middle of Fig. 7.
The main element description of symbols
100: display panels
101: generation writes the zone of phenomenon more easily
301: the zone of drive signal
401,501,601: sequential control circuit
421～426,521,522,621～626: latch pulse signal
502,602: time schedule controller
503,611～615,701: deferred mount
603: delay circuit
801: boundary voltage
802: time delay
A1, A2: the emphasis part of signal
B: impact damper
C: capacitor
Data_G1, Data_G2: the content-data of picture element signal
G1, G2: grid impulse signal
GD1～GD3: gate drivers
GND: ground wire
LP: latch pulse signal
LP_IN, LP_OUT, M: circuit signal
OE: grid shutdown signal
R: resistor
S-Line: picture element signal
SD1～SD8: source electrode driver
Embodiment
Principle of the present invention is to add at latch pulse signal to postpone, to cooperate the transmission delay of grid impulse signal.Because source electrode driver can be at the negative edge output pixel signal of the latch pulse signal that is received, after the latch pulse signal delay, source electrode driver also can be delayed the time of output pixel signal.As shown in Figure 3, in the sequential chart on the right, be represented by dotted lines, and all represent with solid line through latch pulse signal LP that postpones and the picture element signal S-Line that is subjected to related influence through grid impulse signal G1, the G2 that postpones.Still keep synchronously after all signals all pass through and postpone, phenomenon just can not take place to write yet again.
Please refer to Fig. 4 now.Figure 4 shows that the latch pulse signal 421～426 of sequential control circuit according to an embodiment of the invention 401 and its output.Six source electrode driver SD1～SD6 are arranged in the middle of Fig. 4, receive a latch pulse signal 421～426 separately.In the present embodiment, except first latch pulse signal 421, each latch pulse signal 422～426 can be to be synchronized with previous latch pulse signal 421～425, does not just postpone between the two; Also can be to lag behind previous latch pulse signal 421～425, just exist between the two to postpone.As for the time delay between two latch pulse signals 421～426, can be identical, also can be inequality, as long as the delay between the latch pulse signal 421～426, the delay that can cooperate the grid impulse signal to increase gradually in transmittance process makes pixel on the whole piece gate line can not take place to write phenomenon again and gets final product.Therefore, in the middle of the latch pulse signal 421～426, have a latch pulse signal 422～426 at least and lag behind previous latch pulse signal 421～425.
As for how between latch pulse signal, to add postpone, a variety of methods are arranged.For example between two latch pulse signals that needs postpone, use deferred mount (detail as per the embodiment of back), or with an original latch pulse signal, each produces remaining latch pulse signal through the different delay of length, or uses other equivalent method.Said method all is included in the scope of the present invention.
Six latch pulse signals 421～426 are arranged in the middle of Fig. 4, corresponding one by one with six source electrode driver SD1～SD6.Yet the present invention is not limited to the embodiment of Fig. 4.In other embodiments, the corresponding relation between latch pulse signal and the source electrode driver can be one to one or one-to-many, shown in the embodiment of back.Latch pulse signal and source electrode driver also can be any amount greater than.
Figure 5 shows that the sequential control circuit 501 that is pursuant to another embodiment of the present invention.501 of sequential control circuits provide two latch pulse signals 521 and 522.Sequential control circuit 501 comprises time schedule controller 502 and deferred mount 503.Wherein time schedule controller 502 provides latch pulse signal 521 to source electrode driver SD1～SD3.Deferred mount 503 receives latch pulse signal 521, and after postponing, generation and output latch pulse signal 522 are to source electrode driver SD4～SD6.Therefore latch pulse signal 522 lags behind latch pulse signal 521.About deferred mount 503, the back has detailed description.
Figure 6 shows that the sequential control circuit 601 that is pursuant to another embodiment of the present invention.In the middle of Fig. 6, except first latch pulse signal 621, each latch pulse signal 622～626 all is to be produced through postponing by previous latch pulse signal 621～625.Sequential control circuit 601 comprises time schedule controller 602 and delay circuit 603.Time schedule controller 602 provides first latch pulse signal 621.Delay circuit 603 then produces and output latch pulse signal 622～626 according to first latch pulse signal 621.
Delay circuit 603 comprises five deferred mounts 611～615.Wherein, first deferred mount 611 is electrically connected on time schedule controller 602, and remaining deferred mount 612～615 respectively is electrically connected on previous deferred mount 611～614.Each deferred mount 611～615 receives latch pulse signal 621～625 separately, after postponing, produces separately and output latch pulse signal 622～626.Except the embodiment of Fig. 6, the present invention also comprises the extension of sequential control circuit 601, that is to say that deferred mount and latch pulse signal can be any amount greater than, the quantity that needs only the maintenance deferred mount is that the quantity of latch pulse signal subtracts one.
Fig. 7 is the circuit diagram of the deferred mount that uses of the embodiment of front.The deferred mount 701 of Fig. 7 comprises resistor R, capacitor C and impact damper B.Wherein resistor R is electrically connected on the input end LP_IN of deferred mount 701.Capacitor C is electrically connected between resistor R and the ground wire GND.Impact damper B then is electrically connected between the output terminal LP_OUT of resistor R, capacitor C and deferred mount 701.Impact damper B is responsible for receiving the signal from the contact M of resistor R and capacitor C, above-mentioned signal arrangement is exported afterwards for square wave, detail as per Fig. 8.
Fig. 8 is the coherent signal sequential chart of deferred mount 701.In the middle of Fig. 8, the square wave that is denoted as LP_IN is the input signal of deferred mount 701.Because the effect of resistor R and capacitor C, at the signal of the contact M of Fig. 7 just as the signal M in the middle of Fig. 8.Signal M can become the square wave that is denoted as LP_OUT in the middle of Fig. 8 through impact damper B.
In the present embodiment, impact damper B is composed in series with two inverters (inverter), is exactly the boundary voltage of the logic high electronegative potential of above-mentioned two inverters and be denoted as 801 horizontal dotted line in the middle of Fig. 8.So should be not difficult to know by inference, after twice inversion of the signal M of Fig. 8 through impact damper B, can become signal LP_OUT really.And the effect of resistor R, capacitor C and impact damper B can make to have one period time delay 802 between signal LP_OUT and the LP_IN.The length of time delay 802 is exactly the capacitance that the resistance value of resistor R multiply by capacitor C.
The present invention is not limited to the impact damper B that two inverters are composed in series, and in other embodiments, can use any circuit arrangement of same effect.The present invention also is not limited to the deferred mount 701 in the middle of Fig. 7, in other embodiments, can use any circuit arrangement of same delay effect.
Except above-mentioned sequential control circuit, the present invention also comprises a kind of sequential control method of correspondence.For one of ordinary skill in the art of the present invention, by the circuit embodiments of front, should implement sequential control method of the present invention easily, therefore will not give unnecessary details.
By the explanation of above embodiment as can be known, the present invention is providing to adding delay between the latch pulse signal of different source electrode drivers, the transmission delay that cooperates the grid impulse signal makes that the significant zone of grid impulse signal delay is also later receives corresponding picture element signal.At the grid impulse signal with under the delay of picture element signal cooperates, can effectively avoid writing again phenomenon, because of premature closure pixel unlike prior art, also can increase the pixel duration of charging simultaneously, and then reach the advantage of dwindling thin-film transistor element and increasing aperture opening ratio.In addition, because the output time difference of each source electrode driver can reduce electromagnetic interference (EMI).
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any one of ordinary skill in the art, without departing from the spirit and scope of the present invention; when can doing a little change and improvement, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (13)
1. a sequential control circuit is exported a plurality of latch pulse signals, it is characterized in that:
In the middle of the above-mentioned latch pulse signal, except first latch pulse signal, each latch pulse signal all is synchronized with or lags behind previous latch pulse signal, and exists a latch pulse signal to lag behind previous latch pulse signal at least.
2. sequential control circuit according to claim 1, the quantity that it is characterized in that above-mentioned latch pulse signal is two, and second this latch pulse signal lags behind first this latch pulse signal.
3. sequential control circuit according to claim 2 is characterized in that also comprising:
Time schedule controller is exported first this latch pulse signal; And
Deferred mount receives first this latch pulse signal, after postponing, produces and export second this latch pulse signal.
4. sequential control circuit according to claim 3 is characterized in that this deferred mount also comprises:
Resistor is electrically connected on the input end of this deferred mount;
Capacitor is electrically connected between this resistor and the ground wire; And
Impact damper is electrically connected between the output terminal of this resistor, this capacitor and this deferred mount, receives the signal from the contact of this resistor and this capacitor, and this signal arrangement is output after the square wave.
5. sequential control circuit according to claim 4 is characterized in that this impact damper is that two inverters are composed in series.
6. sequential control circuit according to claim 1 is characterized in that each this latch pulse signal all lags behind previous this latch pulse signal except first this latch pulse signal.
7. sequential control circuit according to claim 6 is characterized in that also comprising:
Time schedule controller is exported first this latch pulse signal; And
Delay circuit according to first this latch pulse signal, produces and the above-mentioned latch pulse signal of output except first this latch pulse signal.
8. sequential control circuit according to claim 7 is characterized in that this delay circuit also comprises:
A plurality of deferred mounts, the quantity of above-mentioned deferred mount is that the quantity of above-mentioned latch pulse signal subtracts one, wherein first this deferred mount is electrically connected on this time schedule controller, all the other I these deferred mounts are electrically connected on I-1 this deferred mount, and I this deferred mount receives I this latch pulse signal, after postponing, produce and export I+1 this latch pulse signal, wherein I is a positive integer, and 1≤I≤N-1, and N is the quantity of above-mentioned latch pulse signal.
9. sequential control circuit according to claim 8 is characterized in that each this deferred mount also comprises:
Resistor is electrically connected on the input end of this deferred mount;
Capacitor is electrically connected between this resistor and the ground wire; And
Impact damper is electrically connected between the output terminal of this resistor, this capacitor and this deferred mount, receives the signal from the contact of this resistor and this capacitor, and this signal arrangement is output after the square wave.
10. sequential control circuit according to claim 9 is characterized in that this impact damper is that two inverters are composed in series.
11. a sequential control method provides a plurality of latch pulse signals, it is characterized in that:
In the middle of the above-mentioned latch pulse signal, except first latch pulse signal, each latch pulse signal all is synchronized with or lags behind previous latch pulse signal, and exists a latch pulse signal to lag behind previous latch pulse signal at least.
12. sequential control method according to claim 11, the quantity that it is characterized in that above-mentioned latch pulse signal is two, and second this latch pulse signal lags behind first this latch pulse signal.
13. sequential control method according to claim 11 is characterized in that each this latch pulse signal all lags behind previous this latch pulse signal except first this latch pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510073498 CN1873756A (en) | 2005-06-01 | 2005-06-01 | Sequential control circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510073498 CN1873756A (en) | 2005-06-01 | 2005-06-01 | Sequential control circuit and method |
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| CN1873756A true CN1873756A (en) | 2006-12-06 |
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| CN 200510073498 Pending CN1873756A (en) | 2005-06-01 | 2005-06-01 | Sequential control circuit and method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101901586A (en) * | 2010-07-30 | 2010-12-01 | 南京中电熊猫液晶显示科技有限公司 | Method for increasing pixel electrode charging time under gate in array (GIA) driving |
| CN101599254B (en) * | 2009-05-05 | 2012-12-19 | 华映光电股份有限公司 | Adjustment device and adjustment method for output enable signal |
| CN105161062A (en) * | 2015-08-28 | 2015-12-16 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display panel |
| CN106448531A (en) * | 2015-08-13 | 2017-02-22 | 三星电子株式会社 | Source driver integrated circuit for compensating for display fan-out and display system including the same |
| CN113724666A (en) * | 2021-08-31 | 2021-11-30 | 上海中航光电子有限公司 | Display device and vehicle |
-
2005
- 2005-06-01 CN CN 200510073498 patent/CN1873756A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101599254B (en) * | 2009-05-05 | 2012-12-19 | 华映光电股份有限公司 | Adjustment device and adjustment method for output enable signal |
| CN101901586A (en) * | 2010-07-30 | 2010-12-01 | 南京中电熊猫液晶显示科技有限公司 | Method for increasing pixel electrode charging time under gate in array (GIA) driving |
| CN106448531A (en) * | 2015-08-13 | 2017-02-22 | 三星电子株式会社 | Source driver integrated circuit for compensating for display fan-out and display system including the same |
| CN106448531B (en) * | 2015-08-13 | 2021-07-13 | 三星电子株式会社 | Source driver integrated circuit compensating for display fanout and display system including the same |
| CN105161062A (en) * | 2015-08-28 | 2015-12-16 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display panel |
| CN105161062B (en) * | 2015-08-28 | 2018-05-04 | 南京中电熊猫液晶显示科技有限公司 | A kind of liquid crystal display panel |
| CN113724666A (en) * | 2021-08-31 | 2021-11-30 | 上海中航光电子有限公司 | Display device and vehicle |
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