CN1870121A - Data drive circuit, liquid crystal display panel, liquid crystal display module and display - Google Patents
Data drive circuit, liquid crystal display panel, liquid crystal display module and display Download PDFInfo
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- CN1870121A CN1870121A CN 200610093664 CN200610093664A CN1870121A CN 1870121 A CN1870121 A CN 1870121A CN 200610093664 CN200610093664 CN 200610093664 CN 200610093664 A CN200610093664 A CN 200610093664A CN 1870121 A CN1870121 A CN 1870121A
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Abstract
A data driving circuit used on film transistor liquid crystal display is prepared as switching off N1 numbers of channel outputs including multiplexer and displacement register, receiving level initial signal and at least one control signal by multiplexer and using said control signal to decide signal output of output end on multiplexer, receiving frequency signal and said output signal as well as outputting initial pulse signal by displacement register and using the first image data outputted by the first channel to decide which output end is used to output initial signal according to said output signal.
Description
Technical field
The invention relates to Thin Film Transistor-LCD, and particularly relevant for its data drive circuit.
Background technology
Shown in Figure 1A, in some conventional digital is used, the resolution of Thin Film Transistor-LCD (TFT-LCD) is 800RGB * 480,5 of the data drive circuit chips of its needs 480 channels, because the screen level number of channel is 800 * 3, equal the overall channel number that the data drive circuit chip of 5 480 channels can provide just.But based on the consideration that reduces cost, can the data drive circuit chip be reduced to 3 by 5 as far as possible, then the number of channel of data drive circuit chip need become 800 passages, yet 800 non-be 3 multiple, and in the design of data drive circuit chip, RGB is regarded as an indivisible unit, therefore, 800 numbers of channel are also infeasible in the data drive circuit chip design, thereby must change to 801 or 804 passages, further consider the problem of left-right symmetric, common 804 passages can be the port numbers that is proposed use.
Yet, when the data drive circuit chip be designed to 804 channels the time, existing timing controller can't use.Shown in Figure 1B, wherein 12 of a data drive circuit chip channels are not used, the function of counter-rotating about it can't be applied to have, and timing controller needs to revise to some extent, need earlier by first-in first-out (FIFO) circuit with data latching (latch) after, again data are lost.Fig. 1 C illustrates another situation, and wherein the data drive circuit chip of the left and right sides respectively has 6 channels not to be used, the application of counter-rotating about this symmetrical layout helps, but existing timing controller still can't provide corresponding support.
Summary of the invention
The invention provides a kind of data drive circuit, be used for Thin Film Transistor-LCD, its N passage output can be closed, it comprises multiplexer and shift register.Multiplexer receives horizontal start signal and at least one control signal, and the output of the signal of the output terminal of this multiplexer is to determine according to these control signals, shift register receiving frequency signals and this output signal, and the output initial pulse signal, this initial pulse signal is decided by first passage or N according to this output signal from what output terminal output
1+ 1 channel output the first stroke view data.
The invention provides a kind of driving method of Thin Film Transistor-LCD, whether it comprises provides a plurality of control signals and determines the output channel of the prearranged number of data drive circuit is closed according to the combination of this a plurality of control signals.
According to embodiments of the invention, under the cooperating of multiplexer in the data drive circuit and shift register, can allow the user determine whether the part delivery channel of data drive circuit is closed, so can promote the elasticity in the application of data drive circuit by control signal.
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.
Description of drawings
Figure 1A is depicted as the panel layout of traditional Thin Film Transistor-LCD.
Be respectively panel layout shown in Figure 1B and the 1C according to the Thin Film Transistor-LCD of one embodiment of the invention.
Figure 2 shows that channel off selection circuit according to the data drive circuit chip of one embodiment of the invention.
Figure 3 shows that display panels according to one embodiment of the invention.
Figure 4 shows that liquid crystal display device module according to one embodiment of the invention.
Figure 5 shows that driving method according to the Thin Film Transistor-LCD of one embodiment of the invention.
[main element label declaration]
MUX～multiplexer; SR1～first shift register;
SR2～second shift register; STH～horizontal start signal;
OS1, OS2 and ENOS～control signal; CLK～frequency signal;
DFF～D flip-flop; D～data input pin;
OUT1～first output terminal; Q～data output end;
OUT2～second output terminal; OUT3～the 3rd output terminal;
OUT4～the 4th output terminal;
510～a plurality of control signals are provided;
520～whether determine the output channel of the prearranged number of data drive circuit is closed according to the combination of this a plurality of control signals.
Embodiment
In order to promote the elasticity of data drive circuit chip on using, make itself and existing timing controller compatibility, and avoid the waste of developing, can on existing data drive circuit chip, add some circuit, make and optionally some delivery channel of data drive circuit chip to be closed, so that the total channel number of data drive circuit chip conforms to the horizontal resolution of screen, to be that the Thin Film Transistor-LCD of 800RGB * 480 is an example in resolution below with the data drive circuit chip application of 804 channels, as the explanation of the embodiment of the invention, but scope of the present invention is not as limit.
In order can optionally some delivery channel of data drive circuit chip to be closed, the deviser can set up following menu:
Table I
| ENOS | OS1 | OS2 | Function declaration |
| 1 | X | X | Do not close any output channel |
| 0 | 0 | 0 | Close 12 output channels in data drive circuit left side |
| 0 | 0 | 1 | Close 12 output channels on data drive circuit right side |
| 0 | 1 | 0 | Close 6 output channels in data drive circuit left side |
| 0 | 1 | 1 | Close 6 output channels on data drive circuit right side |
Wherein ENOS, OS1, OS2 are the control signal of circuit that the deviser adds, combination by these control signals, just can optionally some delivery channel of data drive circuit chip be closed, and the layout of its panel and data drive circuit chip will be as shown in Figure 1B and the 1C.
Figure 2 shows that channel off selection circuit according to the data drive circuit chip of one embodiment of the invention, it comprises multiplexer MUX, the first shift register SR1 and the second shift register SR2, this multiplexer MUX receives horizontal start signal STH and control signal OS1, OS2 and ENOS, and the output of the output signal of the output terminal of this multiplexer MUX is according to these control signals OS1, OS2 and ENOS and determine, wherein horizontal start signal STH comes from timing controller (not being shown among the figure), control signal then can be by pin position (pin) input of user by the data drive circuit chip, input/outgoing direction of the first shift register SR1 and the second shift register SR2 is reverse, and both receive the output signal of same frequency signal CLK and multiplexer MUX, and the output initial pulse signal, what channel output the first stroke view data this initial pulse signal is decided by according to this output signal from what output terminal output.
Preferable, this the first shift register SR1 and the second shift register SR2 comprise a plurality of D flip-flop DFF respectively, each D flip-flop DFF receives this frequency signal CLK, the data input pin D of first D flip-flop DFF is coupled to the first output terminal OUT1 of this multiplexer, and the data input pin D of each D flip-flop DFF thereafter all is coupled to the data output end Q of last D flip-flop DFF.The data output end Q of the 6th the D flip-flop DFF of the first shift register SR1 also is coupled to the second output terminal OUT2 of this multiplexer MUX, thus, suitable multiplexer design just can make when the ENOS of data drive circuit chip pin position is 1, the first stroke view data is in first channel output of data drive circuit chip, and the ENOS pin position of working as the data drive circuit chip is 0, OS1 pin position and OS2 pin position are respectively 1 and at 0 o'clock, six channels in the left side of data drive circuit chip are closed, and the first stroke view data is exported in the left side of data drive circuit chip the 7th channel.As shown in Figure 2, the data output end Q of the 12nd the D flip-flop DFF of the first shift register SR1 also is coupled to the 3rd output terminal OUT3 of this multiplexer MUX, thus, the design of suitable multiplexer just can make when the ENOS of data drive circuit chip pin position is 0, when OS1 pin position and OS2 pin position are respectively 0 and 0,12 passages in the left side of data drive circuit chip are closed, and the first stroke view data is exported in the left side of data drive circuit chip the tenth triple channel.This instructions only is the construction that example illustrates the first shift register SR1 with the D flip-flop, but the scope of the invention is as limit, and RS type, T type, JK D-flip flop also can be used to the construction first shift register SR1.
In Fig. 2, input/the outgoing direction of the second shift register SR2 and the first shift register SR1 are reverse each other, the data output end Q of the 6th the D flip-flop DFF of the second shift register SR2 also is coupled to the 4th output terminal OUT4 of this multiplexer MUX, thus, the design of suitable multiplexer just can make when the ENOS of data drive circuit chip pin position is 0, when OS1 pin position and OS2 pin position are respectively 1 and 1, six passages in the right side of data drive circuit chip are closed, and the first stroke view data is exported in the right side of data drive circuit chip the 7th passage.As shown in Figure 2, the data output end Q of the 12nd the D flip-flop DFF of the second shift register SR2 also is coupled to the first output terminal OUT1 of this multiplexer MUX, thus, the design of suitable multiplexer just can make when the ENOS of data drive circuit chip pin position is 0, when OS1 pin position and OS2 pin position are respectively 0 and 1,12 passages in the right side of data drive circuit chip are closed, and the first stroke view data is exported in the right side of data drive circuit chip the tenth triple channel.This instructions only is the construction that example illustrates the second shift register SR2 with the D flip-flop, but the scope of the invention is as limit, and RS type, T type, JK D-flip flop also can be used to the construction second shift register SR2.
Figure 3 shows that display panels 300 according to one embodiment of the invention, it comprises liquid crystal pixel array 310, gate driver circuit 320 and aforesaid data drive circuit 330, liquid crystal pixel array comprises that a plurality of pixels are arranged in array, each pixel-by-pixel basis is driven by pixel-driving circuit, and each pixel-driving circuit then all is coupled to this gate driver circuit and this data drive circuit.
Figure 4 shows that liquid crystal display device module 400 according to one embodiment of the invention, it comprises display panels 410, gate driver circuit chip 420 and aforesaid data drive circuit chip 430, display panels mainly comprises liquid crystal pixel array, be arranged in array by a plurality of pixels, each pixel-by-pixel basis is driven by pixel-driving circuit, and each pixel-driving circuit then all is coupled to this gate driver circuit chip and this data drive circuit chip.
Figure 5 shows that the driving method according to the Thin Film Transistor-LCD of one embodiment of the invention, whether it comprises provides a plurality of control signals (step 510) and determines the output channel of the prearranged number of data drive circuit is closed (step 520) according to the combination of this a plurality of control signals.
According to embodiments of the invention, under the cooperating of multiplexer in the data drive circuit and shift register, can allow the user determine whether the part delivery channel of data drive circuit is closed, so can promote the elasticity in the application of data drive circuit by control signal.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (10)
1. a data drive circuit is used for Thin Film Transistor-LCD, can be with its N
1Individual passage output is closed, and comprising:
Multiplexer receives horizontal start signal and at least one control signal, and the output of the output signal of the output terminal of this multiplexer is to determine according to these control signals; And
First shift register, receiving frequency signals and this output signal, and output initial pulse signal;
Wherein, what channel output the first stroke view data this initial pulse signal is decided by according to this output signal from what output terminal output.
2. data drive circuit according to claim 1, wherein this first shift register comprises a plurality of triggers, receive this frequency signal, the data input pin of first trigger is coupled to first output terminal of this multiplexer, the data input pin of each trigger thereafter all is coupled to the data output end of last trigger, and N
1The data output end of individual trigger also is coupled to second output terminal of this multiplexer.
3. data drive circuit according to claim 2, wherein those triggers comprise D type, RS type, T type or JK D-flip flop.
4. data drive circuit according to claim 2 also can be with N
2Individual passage output is closed, wherein N
2The data output end of individual trigger also is coupled to the 3rd output terminal of this multiplexer.
5. data drive circuit according to claim 1 also can be with N
3Individual channel output is closed, and this data drive circuit also comprises second shift register, receives this frequency signal and this output signal, and exports this initial pulse signal, and wherein input/the outgoing direction of this first and second shift register is reverse.
6. data drive circuit according to claim 5, wherein this second shift register comprises a plurality of triggers.
7. data drive circuit according to claim 6, wherein those triggers comprise D type, RS type, T type or JK D-flip flop.
8. a display panels comprises data drive circuit according to claim 1.
9. a liquid crystal display device module comprises data drive circuit according to claim 1.
10. the driving method of a Thin Film Transistor-LCD comprises:
A plurality of control signals are provided; And
Whether determine the output channel of the prearranged number of data drive circuit is closed according to the combination of this a plurality of control signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100936642A CN100426372C (en) | 2006-06-14 | 2006-06-14 | Data drive circuit, liquid crystal display panel, liquid crystal display module and display |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100936642A CN100426372C (en) | 2006-06-14 | 2006-06-14 | Data drive circuit, liquid crystal display panel, liquid crystal display module and display |
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| Publication Number | Publication Date |
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| CN1870121A true CN1870121A (en) | 2006-11-29 |
| CN100426372C CN100426372C (en) | 2008-10-15 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465111B (en) * | 2007-12-18 | 2010-11-10 | 胜华科技股份有限公司 | Multiplex circuit for display |
| CN106157902A (en) * | 2015-03-26 | 2016-11-23 | 群创光电股份有限公司 | Display device and sensing device |
| CN111627392A (en) * | 2020-05-20 | 2020-09-04 | 昇显微电子(苏州)有限公司 | Method for reducing power consumption of AMOLED display driving chip column driving circuit |
| CN111833825A (en) * | 2020-07-21 | 2020-10-27 | 北京集创北方科技股份有限公司 | Driving circuit, driving method and display device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100291770B1 (en) * | 1999-06-04 | 2001-05-15 | 권오경 | Liquid crystal display |
| CN100363971C (en) * | 2003-06-03 | 2008-01-23 | 友达光电股份有限公司 | Digital data driver and liquid-crystal displaying device |
| JP2005234077A (en) * | 2004-02-18 | 2005-09-02 | Sharp Corp | Data signal line driving circuit and display device equipped therewith |
-
2006
- 2006-06-14 CN CNB2006100936642A patent/CN100426372C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465111B (en) * | 2007-12-18 | 2010-11-10 | 胜华科技股份有限公司 | Multiplex circuit for display |
| CN106157902A (en) * | 2015-03-26 | 2016-11-23 | 群创光电股份有限公司 | Display device and sensing device |
| CN111627392A (en) * | 2020-05-20 | 2020-09-04 | 昇显微电子(苏州)有限公司 | Method for reducing power consumption of AMOLED display driving chip column driving circuit |
| CN111833825A (en) * | 2020-07-21 | 2020-10-27 | 北京集创北方科技股份有限公司 | Driving circuit, driving method and display device |
| JP7477711B2 (en) | 2020-07-21 | 2024-05-01 | 北京集創北方科技股▲ふん▼有限公司 | Driving circuit, driving method, and display device |
| US11978421B2 (en) | 2020-07-21 | 2024-05-07 | Chipone Technology (Beijing) Co., Ltd. | Driving circuit, driving method and display device |
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| Publication number | Publication date |
|---|---|
| CN100426372C (en) | 2008-10-15 |
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