CN1866477A - Method for removing etching residue on wafer surface - Google Patents
Method for removing etching residue on wafer surface Download PDFInfo
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- CN1866477A CN1866477A CN 200510072951 CN200510072951A CN1866477A CN 1866477 A CN1866477 A CN 1866477A CN 200510072951 CN200510072951 CN 200510072951 CN 200510072951 A CN200510072951 A CN 200510072951A CN 1866477 A CN1866477 A CN 1866477A
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- etch residues
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Abstract
The invention discloses an etching residue removing method of wafer surface, which comprises the following parts: low dielectric constant layer deposited on the wafer, metal layer formed on the low dielectric constant layer, photoproduced resists layer on the metal layer with pattern, wherein the pattern of photoproduced resists layer is moved in the metal layer to form metal pattern, which can be etching screen; the photoproduced resists layer is removed; the plasma is etched on the low dielectric constant layer to form hole, which deposits residue; the first wet-type disposal is to soften the residue; the dry-type plasma disposal is to split the residue; the second wet-type disposal is to remove residual completely.
Description
Technical field
The invention belongs to the field of semiconductor fabrication, the method of inlaying the etch residues in irrigation canals and ditches/guide hole opening in particularly a kind of effective removal low-dielectric constant layer, wherein the formation of this etch residues special during with these irrigation canals and ditches of etching/guide hole opening employed metallic hard shield relevant.
Background technology
Along with the spacing of semiconductor integrated circuit interconnection line is contracted to the deep-sub-micrometer grade, even near nano-scale the time, can successfully remove the etch residues of inlaying in irrigation canals and ditches/guide hole (trench/via) opening that is formed in the low-dielectric constant layer and become one of bottleneck of present copper conductor technology.Case proposes solution at this problem before existing at present, but its treatment effect is verified neither desirable to the greatest extent.
For example, United States Patent (USP) discloses a kind of dry type-wet type-dry type (dry-wet-dry) handling procedure that does not use solvent for No. 6797627, with removing high molecular residue and reduction and the high molecular residue Cu oxide of inlaying in irrigation canals and ditches/guide hole mixed in together.Aforesaid dry type-wet type-dry process program is to carry out after the silicon nitride that is come out via the guide hole opening or carborundum cap rock are removed thereupon.In addition, aforesaid patent and only be limited to its invention at aforesaid silicon nitride of etching or carborundum cap rock time institute especially and produce have carbon-fluorine bond knot (C-F) and copper-fluorine bond knot (Cu-F) is master's a macromolecule.
According to aforesaid patent content, at first must carry out carrying out dry process, and must make oxygen, nitrogen or hydrogen gas plasma and high molecular residue reaction form water-soluble accessory substance with the plasma of oxygen, nitrogen or hydrogen thrin.Then, utilize deionized water to soak again, the high molecular residue and the aforesaid water-soluble accessory substance that are formed on the sidewall of guide hole opening are removed.At last, utilize the hydrogen gas plasma of reproducibility, aforesaid Cu oxide is reduced into copper, the high molecular residue that will be formed on the bottom of guide hole opening is simultaneously removed.
And for example disclosed a kind of usefulness removes the dry type-wet processed program of photoresist and dry ecthing residue in No. the 6465352nd, United States Patent (USP), wherein this dried-wet process program must be carried out the hydrogen/nitrogen plasma treatment earlier, and then be carried out cleaning step with amine (amine-based) solvent again.According to this patent content, aforesaid hydrogen/nitrogen plasma treatment is used for changing the characteristic of so-called " resistive surface hardened layer (resist surface hardened layer) ", make it in follow-up wet treatment step, can be removed smoothly together with the dry ecthing residue.
As previously mentioned, it is still satisfactory inadequately that the disclosed method of above-mentioned prior art all has been proved its result, particularly in some process environments, when involving the etch shield of metal level as at etching dual damascene irrigation canals and ditches/guide hole opening the time.Above-mentioned metal etch shield technology can find detailed disclosure in No. the 6638871st, United States Patent (USP).United States Patent (USP) discloses a kind of method of using the dielectric layer-metal-hard shielding construction of dielectric layer of storehouse in dual-damascene technics for No. 6638871, and it does explanation for how removing the high molecular residue of inlaying in the opening more.
When involving the etch shield of metal level as at etching dual damascene irrigation canals and ditches/guide hole opening the time, the composition that is formed on the residue in irrigation canals and ditches/guide hole opening promptly becomes more complicated and is difficult to and clears up.To so far, there is not prior art that this class of effective removal can be provided as yet owing to use the method for the residue of being derived when the metallic hard screen carries out dual-damascene technics.
Summary of the invention
Therefore, the technical problem to be solved in the present invention is promptly providing a kind of method of improvement, can effectively remove the etch residues on the wafer surface.
According to a preferred embodiment of the invention, the invention provides a kind of method of removing the wafer surface etch residues, include: deposition one low-dielectric constant layer on this wafer; On this low-dielectric constant layer, form a metal level; On this metal level, form a photoresist layer, comprise a pattern; This design transfer of this photoresist layer to this metal level, is formed a metal pattern; Remove this photoresist layer; Utilize this metal pattern as etch shield, this low-dielectric constant layer of plasma dry etch, to form a perforate, wherein this plasma dry ecthing causes this perforate to deposit residue; Carry out one first wet processed, with softening this residue; Carry out a dry plasma and handle, with this residue of cracking; And carry out one second wet processed, to remove this residue fully.
In order a nearlyer step to understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 to Fig. 8 illustrated is that the preferred embodiment of the present invention forms the technology generalized section of inlaying opening in low-dielectric constant layer;
Fig. 9 is the flow chart that macromolecule of the present invention is removed handling procedure;
Figure 10 is the dry process parameter list of the preferred embodiment of the present invention.
Description of reference numerals
92 first wet processed, 94 dry process
96 second wet processed, 200 Semiconductor substrate
201 plain conductors, 202 silicon nitride cap rocks
204 first dielectric layers, 206 etching stopping layers
208 second dielectric layers, 210 CMP stop layer
212 metal levels, 214 dielectric barrier layers
216 BARC layers, 220 photoresist
222 openings, 224 BARC layers
230 photoresists, 232 guide hole openings
234 inlay opening 234a top ditch channel opening
234b bottom guide hole opening 320 high molecular residue
Embodiment
The present invention relates to a kind of method that can effectively remove the post-etch residue in irrigation canals and ditches/guide hole opening, wherein aforesaid irrigation canals and ditches/guide hole opening is to be to utilize metal level to etch in the low-dielectric constant layer formed as etch shield with etching mode.Because in copper enchasing technology, the aforementioned metal level that utilizes is the technology of up-to-date importing as the technology of etch shield, therefore believe that because etch metal layers produces the post-etch residue that may contain complicated organic metal composition its composition also is not suitable for reaching removal effectively completely with traditional dry type-wet type-dry process program or dry type-wet processed program.
For this reason, the present invention proposes a kind of wet type-dry type-wet processed program, and is special at involving the mosaic technology of utilizing metal level to carry out as etch shield, with the post-etch residue on effective removal wafer surface.More particularly, wet type-dry type of the present invention-wet processed program includes first wet processed, then handles with more positive oxidizability plasma, then handles with the reproducibility plasma again, finishes up with second wet processed at last.Wherein, employed fluorine class (fluoride-based) solvent that is all of the present invention's first wet processed and second wet processed.
According to a preferred embodiment of the invention, wet type-dry type of the present invention-wet processed program there is no photoresist and exists on the wafer when carrying out, but be not limited thereto.
Please consult Fig. 1 to Fig. 8 earlier, what it illustrated is that the preferred embodiment of the present invention forms the technology generalized section of inlaying opening in low-dielectric constant layer.As shown in Figure 1, be formed with a plain conductor 201 on the Semiconductor substrate 200, and on plain conductor 201 surfaces, be formed with the silicon nitride cap rock 202 that thickness is about 300 to the 700 Izod right sides.Deposition has first dielectric layer 204, etching stopping layer 206 and second dielectric layer 208 in regular turn on silicon nitride cap rock 202, and wherein first dielectric layer 204 and second dielectric layer 208 can be by CORAL
TMOr Black Diamond
TMConstitute Deng advanced low-k materials, and the dielectric constant k value of at present general advanced low-k materials is below 3.0.Etching stopping layer 206 can be the silicon nitride or the carborundum on about 300 to the 700 Izod right sides of thickness.
Then, on second dielectric layer 208, form cmp (CMP) in regular turn and stop layer 210, metal level 212, dielectric barrier layer 214 and bottom anti-reflective (BARC) layer 216, wherein CMP stops layer and 210 can be the silicon nitride or the carborundum of 400 to 700 dusts, and metal level 212 can be titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride etc.The thickness of metal level 212 is about 100 to 300 dusts.Dielectric barrier layer 214 can be silicon nitride or carborundum, and its thickness is about 1,000 to 2, the 000 Izod right side.Then, form photoresist pattern 220 on BARC layer 216, it defines an irrigation canals and ditches pattern.
As shown in Figure 2, utilize photoresist pattern 220 as etch shield, carry out a dry etching process, opening etching BARC layer 216, dielectric barrier layer 214 and metal level 212 via photoresist pattern 220, by this with photoresist pattern 220 defined irrigation canals and ditches design transfer to dielectric barrier layer 214 and metal level 212, form opening 222.
As shown in Figure 3, then photoresist 220 and BARC layer 216 are removed.At this moment, second dielectric layer 208 still stops layer 210 covering protection by CMP lives, and therefore photoresist 220 and BARC layer 216 being carried out plasma ashing when handling, is unlikely hurting second dielectric layer 208.
As shown in Figure 4, form another BARC layer 224 on dielectric barrier layer 214 and metal level 212 and in the opening 222, wherein BARC layer 224 and fill up opening 222.Then, on BARC layer 224, form the photoresist pattern 230 that a definition has the guide hole pattern.
As shown in Figure 5, then utilize photoresist pattern 230 as etch shield, carry out a dry etching process, stop layer 210, second dielectric layer 208 and etching stopping layer 206, form guide hole opening 232 via opening etching BARC layer 224, the CMP of photoresist pattern 230.
As shown in Figure 6, then utilize the plasma ashing mode, photoresist 230 and BARC layer 224 are removed.
As shown in Figure 7, utilize dielectric barrier layer 214 and metal level 212 as etch shield, carry out anisotropic dry etch technology, in first dielectric layer 204 and second dielectric layer 208, form by this and inlay opening 234, wherein inlay opening 234 and comprise and be formed on the top ditch channel opening 234a in second dielectric layer 208 and be formed on bottom guide hole opening 234b in first dielectric layer 204.Bottom guide hole opening 234b exposes the surface of plain conductor 201 partly again.
Inlay in the dry etch process of opening 234 in etching, high molecular residue 320 can be formed on the sidewall of inlaying opening 234 or the bottom.As previously mentioned, owing to involve metal level simultaneously by plasma etching in the dry etch process of opening 234 is inlayed in etching, the composition that therefore makes high molecular residue 320 is complicated more and be difficult to cleaning.
Then, as shown in Figure 8, carry out a series of macromolecule of the present invention and remove handling procedure, will be formed on the sidewall of inlaying opening 234 or the high molecular residue 320 of bottom is removed totally fully.Aforesaid macromolecule of the present invention is removed handling procedure and is illustrated among Fig. 9 with flow chart in addition, illustrates further to do.
As shown in Figure 9, aforesaid macromolecule removal handling procedure of the present invention comprises first wet clean process (step 92), the dry process (step 94) and second wet clean process (step 96).In step 92, under the room temperature, wafer is soaked in the amine solvent about 30 seconds to 90 minutes, but is not limited to above-mentioned time span.Handle through this, the top layer of high molecular residue 320 can be removed.And the prior purpose of this step 92 is the labyrinth of high molecular residue 320 is destroyed, and makes the softening or loose of its macromolecular structure, and can allow follow-up step remove.
After first wet clean process of completing steps 92, and then wafer carry out step 94, just dry process.Wherein, the parameter about this dry process is organized in the table of Figure 10.As shown in figure 10, according to a preferred embodiment of the invention, dry process can have five stages, but is not limited thereto.In initial 40 seconds, comprise stage 1 and 2, mainly be the warming-up step of plasma board.The power of plasma board is switched to 1,500 watt, and operating temperature is increased to 120 ℃, and pressure is adjusted to 0.9 stable holder ear by 2.0 holder ears.Comprise that oxygen and helium (carrier gas)/hydrogen gas mixture is passed in the reaction cabin of plasma board, wherein oxygen flow maintains 100 μ lm, and the flow of helium/hydrogen gas mixture maintains 10,000sccm, wherein hydrogen only account for approximately helium/hydrogen gas mixture flow about 5%.At ensuing 30 seconds, just the stage 3, operating temperature was increased to more than 200 ℃, preferably about about 270 ℃.And back to back 30 seconds, just the stage 4, the power of plasma board is switched to 1,200 watt.
According to the present invention, wafer is when carrying out dry process, at first utilize the plasma treatment (stage 1 to 4) that is about under the oxidation environment that contains aerobic and hydrogen about 100 seconds, purpose is after will be through first wet clean process, structure be softened or the high molecular residue of loose with ionic bombardment and cracking, remove most of high molecular residue 320 of inlaying opening 234 simultaneously.And can also be exposed at this moment at the Cu oxide microparticle of inlaying opening 234 bottoms.As shown in figure 10, last 90 seconds (stage 5), what stop supplies oxygen, wafer touched at this moment was to contain helium/hydrogen, and oxygen-free reproducibility plasma, and be able to the previous Cu oxide inlaying opening 234 bottoms that comes out is reduced into copper.
After carrying out above-mentioned dry process, wet processed is once carried out in the wafer continuation again, and in second wet clean process (step 96 of Fig. 9), uses fluorine kind solvent clean wafers surface equally.The time of cleaning or soaking can be between 30 seconds to 90 minutes, but are not limited thereto scope.Second wet clean process can be removed easily through what dry process of the present invention was crossed and remain in high molecular residue on the wafer surface.Inlayed opening 234 and can find that high molecular residue was removed totally fully through inspecting through what wet type-dry type of the present invention-wet processed program was handled.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. method of removing the wafer surface etch residues includes:
Deposition one low-dielectric constant layer on this wafer;
On this low-dielectric constant layer, form a metal level;
On this metal level, form a photoresist layer, comprise a pattern;
This design transfer of this photoresist layer to this metal level, is formed a metal pattern;
Remove this photoresist layer;
Utilize this metal pattern as etch shield, this low-dielectric constant layer of plasma dry etch, to form a perforate, wherein this plasma dry ecthing causes this perforate to deposit residue;
Carry out one first wet processed, with softening this residue;
Carry out a dry plasma and handle, with this residue of cracking; And
Carry out one second wet processed, to remove this residue fully.
2. the method for removal wafer surface etch residues as claimed in claim 1, wherein this dry plasma is handled and is included following steps:
This wafer and this are exposed in the oxidizability plasma environment through this softening residue, and this oxidation plasma environment contains aerobic and hydrogen; And
This wafer and this residue are exposed in the reproducibility plasma environment that does not contain aerobic.
3. the method for removal wafer surface etch residues as claimed in claim 1, wherein this first wet processed is used fluorine kind solvent (fluoride-based solvent).
4. the method for removal wafer surface etch residues as claimed in claim 1, wherein this second wet processed is used the fluorine kind solvent.
5. the method for removal wafer surface etch residues as claimed in claim 1, wherein this metal level includes titanium, titanium nitride, tantalum, tantalum nitride, and above any combination.
6. the method for removal wafer surface etch residues as claimed in claim 1, wherein before this metal level of deposition, deposition one cmp stops layer on this low-dielectric constant layer earlier.
7. the method for removal wafer surface etch residues as claimed in claim 1 is wherein before forming this photoresist layer, prior to deposition one dielectric barrier layer on this metal level.
8. method of removing the wafer surface etch residues, wherein the formation of this etch residues is that this method includes owing to use the metallic hard shielding in the etching process:
Carry out one first wet processed, with softening this residue;
Carry out a dry plasma and handle, with this residue of cracking, wherein this dry plasma is handled and is included following steps:
(1) under first temperature, this wafer and this are exposed in the oxidizability plasma environment through this softening residue, and this oxidizability plasma environment contains aerobic and hydrogen; And
(2) under second temperature, this wafer and this residue are exposed in the reproducibility plasma environment that does not contain aerobic;
Carry out one second wet processed, to remove this residue fully.
9. the method for removal wafer surface etch residues as claimed in claim 8, wherein this first wet processed is used the fluorine kind solvent.
10. the method for removal wafer surface etch residues as claimed in claim 8, wherein this second wet processed is used the fluorine kind solvent.
11. the method for removal wafer surface etch residues as claimed in claim 8, wherein this oxidizability plasma environment includes carrier gas in addition.
12. the method for removal wafer surface etch residues as claimed in claim 8, wherein this reproducibility plasma environment includes He/H
2Plasma.
13. the method for removal wafer surface etch residues as claimed in claim 8, wherein this first temperature is higher than room temperature.
14. the method for removal wafer surface etch residues as claimed in claim 8, wherein this second temperature is higher than 200 ℃.
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| CNB2005100729510A CN100392825C (en) | 2005-05-18 | 2005-05-18 | Method for removing etching residue on wafer surface |
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| CNB2005100729510A CN100392825C (en) | 2005-05-18 | 2005-05-18 | Method for removing etching residue on wafer surface |
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| CN102778821A (en) * | 2012-08-15 | 2012-11-14 | 信利半导体有限公司 | Method for stripping photoresist on Array plate |
| CN103247754A (en) * | 2012-02-03 | 2013-08-14 | 朗姆研究公司 | Waferless auto conditioning |
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| US6180534B1 (en) * | 1997-12-18 | 2001-01-30 | Advanced Micro Devices, Inc. | Borderless vias without degradation of HSQ gap fill layers |
| US6890864B2 (en) * | 2001-07-12 | 2005-05-10 | Nec Electronics Corporation | Semiconductor device fabricating method and treating liquid |
| KR100471163B1 (en) * | 2002-03-14 | 2005-03-09 | 삼성전자주식회사 | Methods of forming a semiconductor device having capacitors |
| US6610599B1 (en) * | 2002-06-19 | 2003-08-26 | Lucent Technologies Inc. | Removal of metal veils from via holes |
| US6821880B1 (en) * | 2003-12-01 | 2004-11-23 | Taiwan Semiconductor Manufacturing Co. Ltd. | Process of dual or single damascene utilizing separate etching and DCM apparati |
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| CN102315095A (en) * | 2010-07-09 | 2012-01-11 | 东京毅力科创株式会社 | The manufacturing approach of method of plasma processing and semiconductor device |
| CN102315095B (en) * | 2010-07-09 | 2014-04-09 | 东京毅力科创株式会社 | Plasma processing method and manufacturing method of semiconductor device |
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| CN102778821A (en) * | 2012-08-15 | 2012-11-14 | 信利半导体有限公司 | Method for stripping photoresist on Array plate |
| CN102778821B (en) * | 2012-08-15 | 2014-08-13 | 信利半导体有限公司 | Method for stripping photoresist on Array plate |
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| CN103420329B (en) * | 2013-08-29 | 2016-03-23 | 上海华虹宏力半导体制造有限公司 | For the TaN etch polymers residue removal method of MEMS technology |
| CN107768232A (en) * | 2016-08-23 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | The minimizing technology of the protective layer of device surface |
| CN107768232B (en) * | 2016-08-23 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | Method for removing protective layer on surface of device |
| CN114078694A (en) * | 2020-08-19 | 2022-02-22 | 和舰芯片制造(苏州)股份有限公司 | Method for forming semiconductor etching structure and method for removing residual polymer |
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