CN1864263A - Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof - Google Patents

Abstract

A photo-sensing device package and the method of packaging such device is provided. The package includes an assembly portion having a substrate formed of a material substantially transparent to light within a predetermined range of wavelengths; a sensing portion including at least one photo-sensing die photo-electronically transducing light within the predetermined range of wavelengths; and, a plurality of first solder joints joining the sensing and assembly portions. The assembly portion is formed with at least a first metal layer disposed on the substrate about a front surface region thereof; and, at least one passivation layer formed to extend over the first metal layer. The package is cheap and compact, and simply fabricated.

Description

A kind of Electronic Packaging of semiconductor device of photoinduction and making thereof and assembling

Technical field

The present invention relates in general to a kind of Electronic Packaging of semiconductor integrated circuit, more particularly, relates to the Electronic Packaging of the semiconductor device of photoinduction.

Background technology

The semiconductor device of photoinduction is installed in the ceramic packaging usually.Fig. 1 shows the generalized section of ceramic leadless chip carrier (CLCC), and this is the modal packing forms of photoinduction device.As shown in the figure, the inside in 6 overlay areas of glass lid adopts epoxy material or materials similar that the photoinduction semiconductor chip is fixed on the ceramic substrate 4 with facing up.Welding lead 8 is generally used for photoinduction chip 2 is connected on the ceramic substrate 4.Provide welding pad 10 to connect the package on the circuit board in the bottom of ceramic substrate 4.

Perhaps the most important defective of this encapsulation is that price is very expensive.Another defective is that the size of encapsulation for some hand-held application is inadequately little, for example with size little and in light weight be camera in the portable phone of essential feature.Another defective is, because the photoinduction chip fixes by epoxy material or materials similar, and encapsulation itself adopts soldering paste to fix, and therefore the structure of encapsulation is feasible is difficult to place the photoinduction device very exactly with respect to the focal plane of for example lens.

The 5th, 302, No. 778 United States Patent (USP)s that are entitled as " semiconducting insulation of optical device " have disclosed by integrated sensor, lens and mold frame in the molded assembling encapsulation that pilot pin is provided, thereby optical sensor have been installed on the printed circuit board.Above-mentioned patent is providing limited improvement with respect to before lens combination aspect the accurate positioning of transducer.And above-mentioned patent is only providing general accuracy aspect being placed on encapsulation itself on the mounting panel.

The method for packing of another kind of known photoinduction semiconductor device is provided by Shellcase company.United States Patent (USP) 5,716,759,6,040,235 and 6,117,707 have disclosed concrete technology.Fig. 2 illustrates the generalized section of the encapsulation that forms according to these technology.The metal level of composition is applied on the semiconductor wafer of photoinduction, and welded disc is extended to the scribe region of wafer, described scribe region has narrower width between the chip that closes on.Adopt epoxy resin with the photoinduction die attach on glass substrate.Afterwards, abrasive disc is carried out so that the wafer attenuation in the back side of wafer.Then the silicon of scribe region is removed to expose metal wire.Needing more treatment step to finish making, is not necessary owing to it is clearly understood for the present invention still, has therefore omitted specific description at this.

Compare with the CLCC encapsulation, the advantage of this encapsulation is that its size is littler.However, also exist a plurality of defectives in this encapsulation.Perhaps the topmost defective of this encapsulation is the complexity of its structure and manufacturing process.Because complexity can make process yield descend, therefore this complexity is vital factor in a large amount of production.Because complexity and thing followed production loss, it is expensive therefore making this encapsulation.

Other major defects of this technology comprise, need the scribe line of broad, this with semiconductor fabrication in reduce the scribe line width to realize that in each wafer more the trend of multicore sheet is opposite.At present typical scribe line width is about 100 microns, is not enough to support this technology.Therefore, described encapsulation technology is incompatible with the semiconductor wafer with scribe line width of standard, needs specific measure to make the scribe line width wideer than common scribe line width.

Therefore, one object of the present invention is to provide a kind of encapsulation more cheaply that is used for the photoinduction device.Another object of the present invention is to provide a kind of encapsulation that is used for enough compactnesses of photoinduction device, and to adapt to the handheld applications resemble the cellular phone cameras, its small-medium size may be unique most important encapsulation factor.It is a kind of simple and be convenient to the encapsulation of making and assembling that another purpose of the present invention is to provide, wherein, can with simple mode realize on the horizontal plane and vertical plane on the accurate location of focal plane.

Summary of the invention

In brief, according to a preferred embodiment of the invention, the present invention relates to a kind of electron package structure of photoinduction semiconductor device and the method for making and assembling thereof.

According to the present invention,, on the photoinduction semiconductor wafer, provide a plurality of solder bumps by " formation of wafer salient point " or any other suitable technology as known in the art.Afterwards, the wafer that is formed with salient point is divided into the single chip that is used to form transducing part by scribing.

Substrate is to make separately.Described substrate can be configured to for example circular wafer or the flat board of rectangle.The same with the semiconductor wafer with a plurality of chips, described substrate will have a plurality of unit substrate.Each unit substrate becomes an assembled part, constitutes Electronic Packaging with transducing part after finishing making and encapsulation.The material that is used for substrate is preferably at the light wavelength place that the photoinduction device is responded transparent.In the visible spectrum part, Pyrex are examples that are used for the material of the enough transparencies of having of photoinduction device.The making of this substrate comprises the known any suitable method of technical staff be proficient in field of semiconductor fabrication that adopts, and forms the metal level of a composition at least by deposition and composition, with making solder bump pad and the interconnection line between solder bump pad.These solder bump pad are divided into two groups at least.Solder bump pad in first group is less relatively, and corresponding with the solder bump of photoinduction chip, is used to form interconnected with those photoinduction chips.Solder bump pad in second group is relatively large, and is used to form the interconnection of resulting encapsulation to external circuit itself, for example supports printed circuit board.On the metal level of composition, described substrate comprises that also the passivation layer of at least one composition protects thus the interconnection line that forms.The passivation layer of described composition has opening at described solder bump pad place.Preferably around the light-sensitive area, on the passivation layer of composition, described pad also comprises the dust-seal layer of composition, is used to prevent that dust particle from entering this zone.

Solder bump is arranged on the second set of solder bumps pad, so that resulting encapsulation is connected to external circuit.Be similar to the set-up mode of BGA or CSP solder ball, in this solder bump forming process, can use preformed solder ball.This process generally includes: scaling powder is applied on the solder bump pad, solder ball is placed on the solder bump pad that is applied with scaling powder, and substrate is heated to the typical reflux temperature of scolder so that solder ball melts, soaks on the solder bump pad downwards.

Then, be preferably and adopt the known suitable flip-chip mounting technique of technical staff be proficient in field of semiconductor fabrication, will be formed with salient point and the photoinduction chip of scribing be installed on the substrate.This process comprises: with continuous the picking up of each photoinduction chip-upside-down mounting-be placed into precalculated position of substrate, up to each unit substrate such as designed, be placed with all essential photoinduction chips thereon.Described picking up-upside-down mounting-put procedure generally includes: scaling powder is applied to welding region, afterwards substrate is heated to the typical reflux temperature of solder bump, to form the interconnection between unit substrate and the photoinduction chip.

Then big substrate is carried out scribing, so that each unit substrate is separated.Then, each substrate unit can be picked up-be placed in the preferred encapsulation medium, for example coil, manage or band and spool.

CLCC encapsulates the ceramic substrate that need be used to interconnect and is used for light transmissive glass cover, but encapsulation formed according to the present invention only need have the glass substrate of above two kinds of functions.The present invention has adopted batch processing in addition, and the wafer salient point that for example is used for photoinduction device wafer forms.The present invention has also adopted batch processing to make and assemble the substrate with a plurality of unit substrate.The result of this simplification and batch processing is that the present invention greatly reduces packaging cost.Different with more known encapsulation technologies before is, for example, the present invention adopts simple and replaces welded disc need being extended to scribe region, makes the wafer attenuation and remove the very complicated process of silicon with the metal of exposure scribe region through the flip-chip mounting technique that proves.In addition, such as the photoinduction chip is installed to flip-chip on the substrate install and be used for untight encapsulation solder bump use and feature such as layout provide in an easy manner the focal plane in the horizontal direction with vertical direction reliably and accurate guiding location.Autoregistration appears in the solder reflow process effectively.

Description of drawings

Fig. 1 is the generalized section of CLCC encapsulation that is used for the prior art of photoinduction device;

Fig. 2 is the generalized section of the photoinduction encapsulation of another prior art;

Fig. 3 A is before handling, the generalized section of the photoinduction semiconductor wafer of the not scribing in the one exemplary embodiment of the present invention;

Fig. 3 B has applied after the metal level of composition, the generalized section of the photoinduction semiconductor wafer of the not scribing in the one exemplary embodiment of the present invention;

Fig. 3 C is after pad forms, the generalized section of the photoinduction semiconductor wafer of the not scribing in the one exemplary embodiment of the present invention;

Fig. 4 illustrates the transmission of incident light from the air to glass and the illustrative schematic diagram of reflection that changes to high refractive index medium from the medium of low-refraction;

Fig. 5 be figure out owing on substrate, formed optical filter, the explanatory view of the example of photoinduction response change;

Fig. 6 A is in an one exemplary embodiment of the present invention, in the generalized section of the unit substrate of the scribing in certain stage of making;

Fig. 6 B adopts in another one exemplary embodiment of the present invention of a plurality of metal levels, in the generalized section of the unit substrate of the scribing in certain stage of making;

Fig. 7 is in an one exemplary embodiment of the present invention, in a series of generalized sections of the substrate of the not scribing in some stage of making;

Fig. 8 is in an one exemplary embodiment of the present invention, some a series of generalized section of the substrate of the not scribing in stage further of making;

Fig. 9 is in an one exemplary embodiment of the present invention, not a series of generalized sections of the flip-chip assembly of the photoinduction chip on the substrate of scribing;

Figure 10 is that it is shown as and exemplarily is installed on the printed circuit board according to the generalized section of the Electronic Packaging of one exemplary embodiment formation of the present invention;

Figure 11 illustrates to be used for forming the making of Electronic Packaging and the block diagram of number of assembling steps according to one exemplary embodiment of the present invention; And

Figure 12 illustrates to be used for according to the making of another one exemplary embodiment formation Electronic Packaging according to the present invention and the block diagram of number of assembling steps.

Embodiment

A kind of semiconductor wafer of photoinduction has a plurality of chips, and in the semiconductor wafer at other, each chip has the integrated circuit that forms in the front of described wafer.Each chip has a plurality of welded disc.The passivation layer that has composition on the front of described wafer is to protect the integrated circuit below it.There is opening in described passivation layer on described welded disc.Each such photoinduction chip has a light-sensitive area at least on the front.

Wafer salient point formation technology is well-known technology (as transferring IBM afterwards, being entitled as described in the 3rd, 292, No. 240 United States Patent (USP)s of " method of making miniature function element "), and this technology has obtained being extensive use of once occurring.Typical wafer salient point forms technology and comprises that at least the metal level of a composition makes the solder bump pad on the welded disc that is connected to wafer.The alloy that is used for solder bump pad is often referred to alloy under the salient point (UBM); and adopt sandwich construction that multiple function is provided usually; for example good adhesive force is on welded disc; the good diffusion that prevents the scolder diffusion stops; and to the good wettability of welding (and oxidation protection, if necessary).Can obtain to be used to deposit the various technology of UBM, comprise sputter, electroplate electroless-plating and similar techniques.

The welding material of scheduled volume is applied on the solder bump pad.There is several different methods to apply scolder-plating, soldering paste printing etc.Tin-lead that the welding material-congruent melting of several frequent uses is arranged in the wafer salient point forms, high concentration lead (plumbous part by weight at the tin-kupper solder more than 80%), and lead-free is (normally based on the scolder of tin, pure tin for example, Xi-Yin, tin-copper, tin-silver-copper etc.).

Described wafer salient point forms technology comprises that also thereby the typical reflux temperature that wafer is heated to scolder makes scolder be connected on the solder bump pad.The wafer salient point forms the passivation layer that can comprise a composition below the metal level of composition selectively at least, promptly so-called " passivation again ".The wafer salient point forms the interconnection metal traces that can also selectively comprise between welded disc and the solder bump pad, promptly so-called " reallocation ".This reallocation needs the passivation layer of another composition to protect interconnection metal traces usually.These multiple structures that are used for that the wafer salient point forms are to be proficient in the wafer salient point to form the technical staff in field known.

According to the present invention, the wafer that is formed with salient point is preferably used for making the Electronic Packaging of photoinduction device, but is not limited to any concrete structure, salient point formation technology or the welding material that uses in these wafer salient points form.In a preferred embodiment, after the wafer salient point formed, the height of the solder bump of photoinduction wafer was preferably and is lower than 100 microns.Form (being used to form a plurality of solder bumps 104) generalized section afterwards after the metal level that Fig. 3 A-Fig. 3 C shows photoinduction semiconductor wafer 100 before handling respectively, applied composition forms a plurality of solder bump pad 102 and at solder bump.

Before the wafer salient point forms, during or afterwards, if necessary, can adopt any suitable mode in the field of semiconductor fabrication, by mechanical lapping wafer 100 is thinned to certain thickness.The purpose of this reduction process will make an explanation in this part after a while.Preferably, the thickness of the wafer 100 behind the attenuate is about the 250-350 micron, all is available and thickness is about the 150-350 micron.After this, adopt known any suitable mode in the field of semiconductor fabrication once more,, described photoinduction wafer is carried out scribing to separate each chip 101 along scribe line 103.

Substrate is to make separately.Described substrate is preferably wafer or the flat type with big area, and its area enough is used for making semiconductor wafer have the mode of a plurality of chips to be similar to, and forms a plurality of unit substrate in batch process.Usually, the major requirement to backing material comprises: transparency, mechanical hardness and chemical stability.Selected backing material only transparent in certain wavelength or the wave-length coverage, so as with this optical transmission to the photoinduction device.Suitable backing material includes but not limited to: this type of infrared transparent materials of glass, quartz, sapphire, silicon or other.Interested wave-length coverage is depended in the selection of backing material, thereby the photoinduction device on feasible any one wavelength that is operated in ultraviolet ray, the visible or infrared light spectrum can benefit from the present invention.Need chemical resistance and mechanical stability to bear temperature and various treatment step in the manufacturing process, and the influence of opposing environment in the life expectancy of manufacturing device.The typical backing material that is used to be operated in the photoinduction device in the visible wavelength range is Pyrex.Owing to can obtain its chemistry and stability temperature originally with rational one-tenth, and it can obtain from many resources, so Pyrex are preferable material.

Can on two surfaces of described substrate, plate the thin film layer at least, to improve its light transmission.For example, can adopt antireflecting coating (ARC) or be versed in other known suitable coatings of technical staff of optical field.Use a purpose of coating to be to make institute's interior reflection of light loss of interested whole spectrum to minimize.Fig. 4 illustrates the reflection of light by substrate.

Similarly, can only on a surface of substrate, plate thin film at least, to improve or to reduce the optical transmission rate in the certain wavelengths scope.Can adopt any suitable technology known in the optical field to realize this " optically filtering ", now publish as the nineteen fifty-five Bart is fertile, " optical characteristics (Optical Properties of ThinSolid Films) of thin solid film " that O.S.Heavens showed, American Elsevier published in 1969, " thin film optical filter (the Thin-Film Optical Filters) " that H.A.Macleod showed, John Wiley published in 1976, " Film Optics; a kind of optical multilayer theory (Optics of Thin Films; an Optical Multilayer Theory) " that Z.Knittl showed, or Macmillan in 1987 publishes, the technology of being put down in writing in the books such as " user's manual of optical thin film (Optical Thin Film ' s User ' s Handbook) " that J.D.Rancourt showed.

Fig. 5 illustrates the example that adopts the filter that is placed on photoinduction device front to obtain adjusted photoresponse.In this special example, described filter is designed to have the sensitivity that can imitate eye and the photoinduction device that cuts off the intrinsic response of the silicon in ultraviolet ray (UV) and the region of ultra-red.In a preferred embodiment, big borosilicate wafer or panel are used as substrate, and its thickness preferably is about the 400-800 micron, if obtainable resource allows, and thickness even can be the 250-800 micron then.In addition in a preferred embodiment, on surface of described substrate or front and rear surfaces, plate thin film at least,, perhaps improve or the interior optical transmission rate of the interested wave-length coverage of low institute so that reflection loss is minimized.

With reference to Fig. 6 A-Fig. 8, the metal level 202 of at least one composition is applied on the front 204 of substrate 200 interconnection line 208 of making solder bump pad 206a, 206b and connecting described solder bump pad 206a, 206b.Then, the passivation layer 210 of at least one composition is applied on the metal level 202 of composition and protects the interconnection line 208 that forms thus.Solder bump pad 206a, 206b are divided into two groups.Solder bump pad 206a in first group is less relatively, to be used to form the interconnection with photoinduction semiconductor chip 101.Solder bump pad 206b in second group is relatively large, with resulting Electronic Packaging itself and external circuit or such as device interconnectings such as printed circuit boards.

Extensively adopt two kinds of methods to make solder bump pad, interconnection line and passivation.First method as shown in Figure 6A is to adopt the metal level 202 of a composition that solder bump pad 206a, 206b and interconnection line 208 are provided, and the passivation layer 210 that is formed with a composition on the suitable part of described metal level is protected interconnection line 208.Second method shown in Fig. 6 B is to adopt the metal level 212 of a composition to form interconnection line 214; adopt the passivation layer 216 of a composition to protect interconnect metallization lines part 214; apply the metal level that another has the composition of 218a and 218b part then, form solder bump pad 220a and 220b with metal level 212 part in its lower section.In a kind of in the back situation, realize interconnection between first and second metal levels 212,218a and the 218b by the opening on the passivation layer 216.In two kinds of selections, the metal level itself that is used for solder bump pad has sandwich construction usually, comprises bonding coat, is used to provide the good bonding with the material that is close to below; The layer with good wettability (and time oxide protective layer) if desired that is used for the good diffusion impervious layer of scolder and is used for welding material is similar to the structure of the UBM of the foregoing solder bump pad that is used to form the photoinduction wafer.

First kind of selection is both economical, because it only uses layer of metal layer 202; But on essence, the metal level of described interconnection comprises one deck diffusion barrier material, and it is still not unnecessary for interconnect metallization lines, but also has caused high diaphragm pressure.Because this diaphragm pressure can cause the layering of pressure transfer even film, so it is harmful to aspect reliability.Second kind of selection is owing to do not comprise diffusion impervious layer in the metal wire of interconnection, and be therefore better aspect reliability; But this selection needs metal level 212,218a and the 218b of a plurality of compositions, and this has just caused the cost of manufacture increase.Therefore, two main requirement are depended in the selection in these options usually, i.e. cost and reliability, and the two can change according to change of required application.

In the preferred embodiment of the first kind of selection that illustrates, the aluminium lamination that is about the 1-2 micron is used as adhesive layer, and the Ni-V layer that is about the 200-500 nanometer is used as diffusion impervious layer, and the copper layer that is about the 500-1000 nanometer is used as the wetting layer.These layers are deposited on the substrate continuously, thereby are formed on the metal level 202 at solder bump pad 206a and 206b place jointly, preferably deposit by sputter under the situation of not destroying vacuum state between every layer the deposition process.

In the preferred embodiment of the second kind of selection that illustrates, preferably adopt the method for sputter on substrate, to deposit the aluminium lamination of about 1-2 micron, to make interconnect metallization lines.By deposition continuously as the aluminium lamination that is about 200-2000 sodium rice of the metal wire adhesive layer of interconnection, form second kind of solder bump pad 220a and 220b in the selection as the nickel that the is about the 200-500 nanometer-V layer of diffusion impervious layer and as the copper layer that is about the 500-1000 nanometer of wetting layer.Preferably under the situation of not destroying vacuum state between every layer the deposition process, deposit by sputter.

In two kinds of selections, be preferably and adopt polymeric layer to be used as passivation layer 210 and 216.The thickness of polymer passivation layer preferably is about the 4-20 micron, and it can form by the known any suitable mode of the technical staff who is proficient in field of semiconductor fabrication.

With reference to Fig. 7-Fig. 8, it shows the generalized section of the substrate 200 (it is the form of sheet glass) of the not scribing of different production phases.By scribe line 203 substrate 200 is divided into a plurality of unit substrate 210, described unit substrate 210 has metal level 202, passivation layer 210 and the dust-seal layer 222 of the composition that is used to define solder bump 206a, 206b and transmission region 223.As shown in Figure 8, after metal level and passivation layer 202 and 210 formed, the dust-seal layer 222 of one deck composition was applied on the substrate 200 at least, thereby prevented dust particle arrival and shield light induction region.Can dispose the dust-seal layer 222 of composition, around the light-sensitive area of the transmission region 223 of resulting encapsulation, to form the structure of dust seal.The dust of any obstruct light all will cause the photoinduction error.Therefore, whether need this dust-seal layer depend on in the interested application to the required restriction of dust particle.In the preferred embodiment that illustrates, the thickness of dust-seal layer 222 is preferably less than 80 microns, and dust-seal layer 222 is preferably the employing polymeric material.

There is several different methods to make dust-seal layer 222.The most general method is to distribute epoxy resin or similar material.Another kind method is a coated polymeric layer and by utilizing photoetching process that it is carried out composition.According to the present invention, can adopt known these or any other the suitable method of technical staff of being proficient in semiconductor fabrication and encapsulation field.

Next, solder bump 224 is installed on the second set of solder bumps pad 206b that is formed on substrate 200 tops.In the preferred embodiment that illustrates, be preferably by silk screen printing scaling powder is applied on each suitable solder bump pad 206b, preformed solder ball 224 is placed on each solder bump pad 206b of second group with scaling powder then.Resulting substrat structure is heated to the distinctive reflux temperature of welding material, so that with 224 fusings of the solder ball placed and make them soak on the solder bump pad downwards.The height of solder bump 224 preferably (but and nonessential) greater than 250 microns.

Can adopt multiple welding material in the present invention.Tin-the kupper solder of congruent melting is common material.Because therefore the strictness of the eliminating lead that exists usually in semi-conductor industry restriction may extensively adopt lead-free solder in the future, for example pure tin, Xi-Yin, tin-copper and tin-silver-copper scolder.Use for high temperature, weight ratio is that leaded high lead content scolder 80% or more is the welding material of using always because plumbous have high melt point with and consume diffusion impervious layer in the less solder bump pad.The invention is not restricted to any specific welding material.

In case substrate 200 is made into aforesaid a plurality of unit substrate or assembled part 201, the photoinduction chip 101 that then will constitute the sensing part is installed on the assembled part 201 of substrate 200, preferably adopts suitable flip-chip assembling process known in the field.Schematic illustrations as Fig. 9, this flip-chip assembling process comprise each the photoinduction chip 101 that will have solder bump 104 pick up-precalculated position of each unit substrate 201 of upside-down mounting-be placed into substrate 200 on, on all suitable unit substrate 201, all be provided with their necessary photoinduction chips 101.A plurality of identical or inhomogeneous photoinduction chips 101 can be installed on the unit substrate 201.Also the active and/or passive chip (not shown) of other non-sensitization can be installed on the unit substrate 201 to constitute multi-chip module.

The convenience that the solder bump 104 of each semiconductor chip 101 and engaging of the solder bump pad 206a of relative set on each unit substrate 201 have guaranteed photoinduction chip 101 and unit substrate 201 and consistent accurate relative positioning.When being placed into photoinduction chip 101 on the unit substrate 201, preformed solder bump plays self aligned function with paired the engaging of the solder bump pad of admitting them.

The operation of described picking up-upside-down mounting-placement comprises scaling powder is applied on the solder bump 104 of photoinduction chip 110, is preferably by known suitable " dipping (the dipping) " technology in Flip-Chip Using field.Can adopt in the present invention based on water-soluble scaling powder of rosin or other suitable material.Also can adopt based on organic so-called " exempting to clean " scaling powder.Then described substrate is heated to the specific reflux temperature of welding material, so that melting solder 112 and between the first set of solder bumps pad 206a of substrate 200 and each photoinduction chip 101, form solder joint 104.In the preferred embodiment that illustrates, the height that connects the welded joint 104 of substrate 200 and semiconductor chip 101 is preferably and is lower than 80 microns.

At last, thus along scribe line 203 substrate 200 is diced into separative element substrate 201.Then, each Electronic Packaging 300 (having at least one unit substrate structure 201) that is produced picked up-be placed into be used for the preferred encapsulation medium packing and encapsulate, for example coil, manage or adhesive tape and spool.

With reference to Figure 10, can Electronic Packaging formed according to the present invention 300 be assembled on the pcb board 400 by adopting ball grid array (BGA) encapsulation technology, each unit substrate structure 201 is formed with the typical B GA encapsulation that has solder bump 224 at the periphery that encapsulates 300 very similar.This process generally includes: soldering paste is applied on the solder bump pad of relative PCB part 402, will encapsulate 300 afterwards and overturn and be installed on the pcb board 400.Thereby, solder bump 224 is placed on the corresponding bonding pad 402 that is applied with soldering paste on it.

Figure 11 with the formal specification of block diagram the making and the number of assembling steps of preferred embodiment of the encapsulation 300 that shows in the previous drawings to be discussed.Figure 12 with the formal specification of block diagram show in the process of the solder bump that forms each unit substrate, adopt the similar making and the number of assembling steps of another one exemplary embodiment of the encapsulation of a plurality of metal levels.

Shown in preferred embodiment in, the height of each the big welded contact that is formed by solder bump 224 (it is connected resulting encapsulation 300 with pcb board 400) is preferably more than the common elevation of the little welded contact that is formed by solder bump 104 (it is connected to photoinduction chip 101 on the unit substrate 201) and the thickness of photoinduction chip 101.This has just guaranteed to maintain the slit between photoinduction chip 101 and pcb board 400.Shown in preferred embodiment in, as previously mentioned, be preferably photoinduction semiconductor wafer 100 (photoinduction chip 101 formed by it) be thinned to about 250-350 micron (the 150-350 micron is available); The height that connects the little welded contact 104 of photoinduction chip 101 and unit substrate 201 is set to be less than about 80 microns; And the height that connects the big welded contact 224 of resulting encapsulation 300 and pcb board 400 is set to be higher than 250 microns.

New encapsulation among the present invention can be used for all types of optical sensors or the photo-detector by various technology (for example CCD or CMOS technology) made.The present invention can be used for using all spectra of imageing sensor, camcorder for example, digital stillcamera, PC camera, cell phone cameras, PDA and hand held camera, security cameras, toy, automobile, biometry or the like.The present invention also is applicable to the linear image array transducer, facsimile machine for example, scanner, barcode reader and scanner, employed linear image array transducer in the equipment such as digital copier.The present invention is applicable to the optical pickocff that encapsulation is non-image too, the four-quadrant diode of using in for example single diode or the mobile detector, optical power level transducer, location or tracking system or the like.

Although the present invention describes in conjunction with its specific forms and embodiment, but should be appreciated that, under the situation that does not deviate from the spirit and scope of the present invention, except that above discussion, can make various modifications of the present invention, for example, replace the element that specifically illustrates or describe with equal element, be independent of other feature and use some feature, and under the situation of the spirit and scope of the present invention that do not deviate from claims and limited, can put upside down or insert in some cases and make or the special merging of encapsulation step.

Claims (29)

1. the encapsulation of a photoinduction device comprises:

(a) assembled part comprises:

I. the substrate that constitutes by the material that can be fully sees through the light in the predetermined wavelength range;

Ii. the first metal layer of one deck at least that forms around the positive zone on described substrate; And

Iii. the passivation layer of one deck at least that on described the first metal layer, extends to form, described passivation layer is carried out composition, come to make respectively a plurality of first and second solder bump pad to limit a plurality of first and second recessed openings on described the first metal layer, each described first solder bump pad interconnects with described second solder bump pad at least;

(b) sensing part, comprise at least one photoinduction chip, described photoinduction chip forms a light-sensitive area at least on forward surface, so that the light in the described predetermined wavelength range is carried out opto-electronic conversion, described light-sensitive area is relative with the positive zone of described assembled part substrate, is formed with the solder bump pad of a plurality of and described light-sensitive area electric coupling on the described photoinduction chip; And

(c) a plurality of first welded contacts are used to connect described sensing part and assembled part, and each described first welded contact extends between described first solder bump pad of described solder bump pad of described sensing part and described assembled part.

2. the encapsulation of photoinduction device as claimed in claim 1 further comprises a plurality of second welded contacts, and it extends from described second solder bump pad, by one described second recessed opening of described assembled part, to be installed to external circuit.

3. the encapsulation of photoinduction device as claimed in claim 2, wherein each described second welded contact laterally extends to outside the described photoinduction chip of the described sensing part that is connected to this from described second bump pad.

4. the encapsulation of photoinduction device as claimed in claim 1, wherein said assembled part is included at least one dust-seal layer that the positive zone on the described substrate forms on every side, the horizontal expansion between described substrate and described photoinduction chip of described dust-seal layer is to be enclosed in the part of sealing therebetween.

5. the encapsulation of photoinduction device as claimed in claim 4, wherein said dust-seal layer is made of polymeric material.

6. the encapsulation of photoinduction device as claimed in claim 1, wherein said substrate is made of the Pyrex material.

7. the encapsulation of photoinduction device as claimed in claim 6, the thickness range of wherein said substrate are greatly between the 250-800 micron.

8. the encapsulation of photoinduction device as claimed in claim 4, wherein said substrate by thickness range greatly the Pyrex material between the 250-800 micron constitute.

9. the encapsulation of photoinduction device as claimed in claim 1 wherein is set to the light-sensitive area of described photoinduction chip the positive regional optical alignment with described substrate, to receive the light by described substrate.

10. the encapsulation of photoinduction device as claimed in claim 1, wherein said assembled part comprises at least partially in second metal level that forms on the described passivation layer, described second metal level is patterned at least in part and extends on the described first and second recessed openings, thereby makes the contact of first and second solder bump pad.

11. the encapsulation of photoinduction device as claimed in claim 1, wherein said substrate comprises and described positive opposing backside surface, the described front and back of described substrate is formed with film coating on one of at least, is used to change the optical transmission rate in the predetermined wavelength range that is passed through.

12. the encapsulation of photoinduction device as claimed in claim 4, wherein said substrate comprises and described positive opposing backside surface, the described front and back of described substrate is formed with film coating on one of at least, is used to change the optical transmission rate in the predetermined wavelength range that is passed through.

13. the encapsulation of photoinduction device as claimed in claim 1, each in first and second solder bump pad of the solder bump pad of wherein said sensing part and described assembled part all has the sandwich construction that comprises adhesive layer, diffusion impervious layer and welding soakage layer at least.

14. the method for packing of a photoinduction device comprises following steps:

(a) at least one photoinduction chip is set, described photoinduction chip is limited with at least one integrated light-sensitive area in its forward surface, is used for the light in the predetermined wavelength range is carried out opto-electronic conversion;

(b) on described photoinduction chip, form a plurality of first solder bumps that are electrically coupled to described light-sensitive area;

(c) unit substrate that is made of the material that sees through the light in the predetermined wavelength range fully is set at least;

(d) around the positive zone of described unit substrate, form the layer of metal layer at least;

(e) described metal level is provided with, to limit a plurality of first and second solder bump pad and a plurality of interconnection line, wherein each bar interconnection line extends between at least one first solder bump pad and at least one second solder bump pad;

(f) form the passivation layer that one deck extends at least on described metal level;

(g) described passivation layer is provided with, to limit a plurality of first and second recessed openings of aiming at described first and second solder bump pad respectively;

(h) with inverse manner described photoinduction chip is placed on the described unit substrate, in described first solder bump each all engages with the first recessed opening of a described passivation layer, to contact described first solder bump pad, the light-sensitive area of guiding described photoinduction chip thus makes the front regional alignment of itself and described unit substrate;

(i) described first solder bump is heated to its typical reflux temperature, with attached with first solder bump pad of described unit substrate.

15. the method for packing of photoinduction device as claimed in claim 14 further comprises by the described second recessed opening, and a plurality of second solder bumps are attached to step on described second solder bump pad respectively.

16. the method for packing of photoinduction device as claimed in claim 14 further is included in step (g) afterwards, forms the step of dust-seal layer around the positive zone of described unit substrate.

17. the method for packing of photoinduction device as claimed in claim 15 further comprises the step that is pre-formed described first and second solder bumps with solder ball structure, the diameter of wherein said second solder bump is bigger than the diameter of described first solder bump.

18. the method for packing of photoinduction device as claimed in claim 14, further comprise at least partially in the step that forms upper metal layers on the described passivation layer, described upper metal layers is set to extend at least in part on the described first and second recessed openings, thereby makes described first and second solder bump pad contact.

19. the method for packing of photoinduction device as claimed in claim 14 wherein integrally limits a plurality of described unit pad on substrate, (i) carries out scribing to described substrate afterwards in step, so that described unit substrate is separated from one another.

20. the method for packing of photoinduction device as claimed in claim 14 wherein integrally limits a plurality of described photoinduction chips on wafer, (h) carries out scribing to described wafer afterwards in step, so that described photoinduction chip is separated from one another.

21. the method for packing of photoinduction device as claimed in claim 20 is wherein carried out picking up continuously-upside-down mounting-placement operation, thereby described photoinduction chip is placed on one of corresponding described unit substrate respectively.

22. the method for packing of a photoinduction semiconductor device comprises following steps:

(a) at least one semiconductor chip is set, described semiconductor chip is limited with at least one integrated light-sensitive area in its forward surface, is used for the light in the predetermined wavelength range is carried out opto-electronic conversion;

(b) on described semiconductor chip, form a plurality of solder bump pad for the treatment of with the electric coupling of described light-sensitive area;

(c) a plurality of first solder bumps are attached to respectively on the described solder bump pad that forms on the described semiconductor chip;

(d) unit substrate that is made of the material that can see through the light in the predetermined wavelength range fully is set at least;

(e) around the positive zone of described unit substrate, apply the first metal layer at least;

(f) remove the part of described the first metal layer selectively, to limit a plurality of first and second solder bump pad and a plurality of interconnection line, wherein each bar interconnection line extends between at least one described first solder bump pad and at least one described second solder bump pad;

(g) form the passivation layer that one deck extends at least on described metal level;

(h) remove the part of described passivation layer selectively, to limit a plurality of first and second recessed openings of aiming at described first and second solder bump pad respectively;

(i) with inverse manner described semiconductor chip is placed on the described unit substrate, in described first solder bump each all engages with the first recessed opening of a described passivation layer, to contact described first solder bump pad, the light-sensitive area of guiding described semiconductor chip thus makes the front regional alignment of itself and described unit substrate;

(j) described first solder bump is heated to its typical reflux temperature, with attached with first solder bump pad of described unit substrate.

23. the method for packing of photoinduction semiconductor device as claimed in claim 22 further comprises by the described second recessed opening, and a plurality of second solder bumps are attached to step on described second solder bump pad respectively.

24. the method for packing of photoinduction semiconductor device as claimed in claim 22, further being included in step (h) is applied to the dust seal material to the small part passivation layer afterwards, and optionally remove the part of described dust seal material, to form the step of dust-seal layer around the described positive zone of described unit substrate.

25. the method for packing of photoinduction semiconductor device as claimed in claim 22 wherein integrally limits a plurality of described unit pad on substrate, (j) carries out scribing to described substrate afterwards in step, so that described unit substrate is separated from one another.

26. the method for packing of photoinduction semiconductor device as claimed in claim 22 wherein integrally limits a plurality of described semiconductor chips on wafer, (i) carries out scribing to described wafer afterwards in step, so that described semiconductor chip is separated from one another.

27. the method for packing of photoinduction semiconductor device as claimed in claim 26 is wherein carried out picking up continuously-upside-down mounting-placement operation, thereby described semiconductor chip is placed on one of corresponding described unit substrate respectively.

28. the method for packing of photoinduction semiconductor device as claimed in claim 22, further be included in step (c) and step (i) before, flux material be applied to the step on first solder bump pad of the solder bump pad of described semiconductor chip and described unit substrate respectively.

29. the method for packing of photoinduction semiconductor device as claimed in claim 22, further comprise and on described passivation layer, form second metal level at least in part, described second metal level is carried out composition, extend so that it is recessed on the openings described first and second at least in part, thereby make described first and second solder bump pad contact.

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