CN1862972A - TURBO coding method and coding apparatus - Google Patents
TURBO coding method and coding apparatus Download PDFInfo
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- CN1862972A CN1862972A CN 200510069111 CN200510069111A CN1862972A CN 1862972 A CN1862972 A CN 1862972A CN 200510069111 CN200510069111 CN 200510069111 CN 200510069111 A CN200510069111 A CN 200510069111A CN 1862972 A CN1862972 A CN 1862972A
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Abstract
The invention provides the TURBO coding methods, every bit coding process includes: the bit counter exports every count to maintain the three beats time period in turn; the two loop choosing setting chooses the first beat of the counter exported by the bit counter to serve as the reading dictate delivering to the interlacing address storage, the second beat and the third beat exported by the bit counter air served as the reading dictate delivering to the RAM, the output date by the interlacing address storage when it is in the fourth beat is served as the reading dictate to the RAM; the date exported by the ping-pong RAM during the fifths, sixth beat can be processed be the first counting module to produce the system digit and the first checkout digit, the date exported during the seventh beat can be processed by the second counting module to produce the second checkout digit. The invention also provides the corresponding coding setting. The invention can realize the coding method based on the flowing water, the process delaying of every input bit of the TURBO coding can be reduced, so the whole TURBO coding delaying can be reduced.
Description
Technical field
The present invention relates to the coding techniques field, be meant TURBO coding method and code device especially.
Background technology
Because the TURBO sign indicating number has stronger error-correcting performance, the channel coding schemes in 3 standards of representative 3GPP has all used the TURBO coding, is used for high-speed, high-quality communication service.In the schematic block diagram that downlink coding shown in Fig. 1 is handled, show the position of TURBO coding, the TURBO encoder receives data from prime processing module (CRC adds module), and the result behind the coding is exported to post processing module (rate-matched module).
Fig. 2 shows the schematic diagram of TURBO coding.The TC encoder mainly comprises 4 parts: TC control module, TC arithmetic element, TC interleaver and RAM.
The TC interleaver comprises an interleaving address feram memory, stores the interleaving address that precomputes, and the code block data of input read code block data after RAM just can obtain interweaving successively according to interleaving address.The data that RAM is used for before the received code are carried out buffer memory.The TC arithmetic element is mainly finished the coding of first component (or claiming first check digit) and second component (or claiming second check digit), the inner shift register group of 2 covers, 3 bits that adopt realize, specifically can be referring to the TC arithmetic element shown in the coder structure figure of the TURBO of Fig. 3.The TC controller is the control circuit of whole TC coding, and it finishes the State Control of whole cataloged procedure.
Fig. 3 shows the coder structure figure of the TURBO sign indicating number of 3GPP agreement (3GPP TS25.212) definition.For convenience, the circuit of the generation system position and first component coding is referred to as first computing module, the circuit that generates the second component coding is referred to as second computing module.Wherein, the initial value of each shift register (D) should all be 0 in the encoder.At the afterbody of code block, insert the tail bit to remove the state of encoder, the tail bit obtains (representing as dotted line among the figure) by feedback in the register.
With reference to the coding flow chart of Fig. 2 and Fig. 4, a TC cataloged procedure may further comprise the steps:
Step 401: after receiving the encoder enabling signal, the TC interleaver begins the calculating of interleaving address, after interleaving address is finished, by a complement mark notice TC control module.This process can think that the TC encoder is in initial condition (S0).
After step 402:TC control module is received the encoder enabling signal, begin to accept the data that prime issues, and write among the RAM.
Step 403:RAM waits for and receives 1 complete code block, change next step over to after having stored complete code block data among the RAM.Can think and receive that enabling signal is wait state (S1) to receiving complete code block process.
Step 404: begin to carry out the coding of a code block, comprise system bits processing, first component coding, second component coding.In this process, encoded bit number is counted, when the counting number reached code block length, the indication code block encoding finished, and enters next step.This process can be thought TC encoding state (S2).
Step 405: after a code block encoding process is finished, to the tail bit result output of this code block.In this process, the tail number of bits of output is counted, when having exported specific quantity tail bit, enter next step.This process can be thought tail bit output state (S3).
After tail bit output finishes, judge whether all code blocks all dispose (promptly judged whether treated the code block number that is disposed).If all code blocks are finished dealing with, encoder is got back to idle condition, and cataloged procedure finishes; If the code block of not handling is got back to reception and processing that step 403 is carried out next code block in addition.
Below the cataloged procedure in the step 404 is described.Referring to the logic realization TURBO coder structure figure shown in Fig. 3, during the TURBO encoding process input data transaction of 1 bit is become the output of 3 bits, its coding sequential chart is referring to shown in Figure 5, and after storing code block data among the RAM, the flow process of data output may further comprise the steps:
At first, the direct output system of reading of data position from RAM;
Secondly, reading of data and carry out first component coding and export first check digit from RAM;
At last, from the interleaving address memory of interleaver, search interleaving address, and with this interleaving address reading of data from RAM, and these data are carried out second component coding output second check digit.
TURBO encoding process process above analyzing needs 4 RAM of visit, and wherein 3 times is to read RAM, and 1 time is to read the interleaving address memory.Usually the result could export after reading of data needed 3 clock cycle from RAM, even therefore do not consider the scramble time of first component and second component, as shown in Figure 5,1 bit input data TURBO coding also needs 4 * 3=12 clock cycle.
The TURBO cataloged procedure will carry out interleaving treatment and TURBO coding to the data within the code block, for a code block, include a lot of bits, according to above-mentioned processing, under the more situation of input bit, the processing time-delay of a code block coding can be very big, brought bigger time-delay inevitably for whole downlink processing or up processing.The performance that bigger time-delay has further had influence on Base-Band Processing again is low.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of TURBO coding method and code device, realizes the coding method based on " flowing water ", reduces the processing time-delay of each input bit of TURBO coding, thereby reduces whole TURBO encoding time delay.
The invention provides the TURBO coding method, the coding step of each code block comprises: the coding step of each bit in the code block, the tail bit in code block after all bits of encoded end generate step; The coding step generation system position of described each bit, first check bit sum, second check digit; Each bits of encoded step comprises:
The 1st claps, and current bit figure place in the code block under it is read the interleaving address memory as the address of visit interleaving address memory;
The 2nd claps and the 3rd bat, claps described figure place with the 1st respectively and reads RAM as the address of visit RAM; Described RAM stores described code block;
The 4th claps, and the interleaving address memory is finished the response that reads instruction before 3 bats, exports interleaving address, and this interleaving address is read RAM as the address of visit RAM;
The 5th claps, and RAM finishes and claps the preceding response that reads instruction, dateout to 3;
The 6th claps, and RAM finishes and claps the preceding response that reads instruction, dateout to 3; And the 5th data of clapping RAM output are exported as system bits;
The 7th claps, and RAM finishes and claps the preceding response that reads instruction, the data after output interweaves to 3; And the 6th data of clapping RAM output are carried out first component coding generate the output of first check digit;
The 8th claps, and the 7th data of clapping RAM output is carried out the second component coding generate the output of second check digit.
Optionally, further comprise: clap the coding step that the back starts next bit in each bits of encoded initial 3 successively.
Optionally, further comprise: after cataloged procedure is received pause instruction, stop to start the coding of next bit, and finish the current coding step that is in the bit in the cataloged procedure.
Preferable, described RAM is a ping-pong ram, the different code blocks that encode are buffered in the ping-pong ram with ping-pong buffer mechanism.
Optionally, further comprise: when the RAM data in buffer also has N bit just to expire, send the data output that pause instruction suspends the prime module to the prime module, and also can continue to send N bit after making prime receive instruction.
Wherein, tail bit after all bits of encoded finish in code block generates step and comprises the step that starts the generation of tail bit, the step that starts the generation of tail bit is: write down the number of coded bit, when described number arrives code block length, start the tail bit and generate step.
The present invention also provides a kind of TURBO code device, comprise: second computing module of first computing module of the computing system position and first component coding, calculating second component coding, also comprise: bit counter is used for writing down the figure place of the bit of present encoding at its code block; The interleaving address memory stores interleaver matrix; RAM is used for the code block that buffer memory will be encoded; The bit counter output is connected to interleaving address memory read address input end, is also connected to an input of No. two selectors; Interleaving address memory read data output end is connected to another input of described No. two selectors; Described two road selector output ends are connected to described RAM and read address input end; Described RAM read data output is connected to the input of first computing module, second computing module respectively;
When carrying out each bits of encoded, each count value of bit counter output is kept clock cycle triple time; No. two selectors select the first count of each figure place of bit counter output to be sent to the interleaving address memory, second count triple time to be sent to ping-pong ram, and the interleaving address memory is sent to ping-pong ram in the 4th data of clapping output; Ping-pong ram is clapped the data of exporting the 5th, six and is received the processing generation system position and first check digit, handled generation second check digit in the 7th data of clapping output by the reception of second computing module by first computing module.
Preferable, described RAM is a ping-pong ram.Optionally, described ping-pong ram is 8 bit bit wides, and the 640 byte degree of depth rely on the high address to distinguish the RAM of table tennis.
Wherein, described ping-pong ram also comprises the reading and writing control circuit that connects ping-pong ram; The described control circuit of reading comprises: No. two selectors, two-way input connect high 10 signals that add up after 640 of high 10 signals in external write address, external write address respectively, and output is exported to ping-pong ram as writing address signal; Decoder, low 3 signals in input termination external write address, output is exported to the eight bit register group as writing address signal; The eight bit register group also connects the external write data-signal, and output is exported to ping-pong ram as write data signal; Described write control circuit comprises: No. two selectors, two-way input connect high 10 signals that add up after 640 of high 10 signals in external read address, external read address respectively, and output is exported to ping-pong ram as reading address signal; No. eight selectors, input connects the ping-pong ram output, and receives the control dateout of reading low 3 of address signal.
The present invention also provides a kind of TURBO coding method, and the corresponding codes circuit comprises: second computing module of first computing module of the computing system position and first component coding, calculating second component coding; Be used for writing down the bit counter of the bit of present encoding in the figure place of its code block; Store the interleaving address memory of interleaver matrix; Will the encode RAM of code block of buffer memory; The bit counter output is connected to interleaving address memory read address end, is also connected to an input of No. two selectors; Interleaving address memory read data output end is connected to another input of No. two selectors; Two road selector output ends are connected to described ping-pong ram and read the address end; Ping-pong ram read data output is connected to the input of first computing module, second computing module;
Described coding method comprises: the coding step of each bit in the code block, the tail bit in code block after all bits of encoded end generate step; Each bits of encoded step comprises:
Each count value that bit counter is exported is successively continuously kept clock cycle triple time;
No. two selectors select the first count of the data of bit counter output to be sent to the interleaving address memory as reading instruction, select the second count triple time of bit counter output to be sent to RAM, and the interleaving address memory is sent to RAM in the 4th data of clapping output as reading instruction as reading instruction;
Ping-pong ram is clapped the data of exporting the 5th, six and is received the processing generation system position and first check digit, handled generation second check digit in the 7th data of clapping output by the reception of second computing module by first computing module.
By said method as can be seen, the present invention adopts " flowing water " mechanism to reduce the encoding process time of each input bit, and the time-delay of TURBO encoding process is reduced.The time-out that the present invention also provides internal data flow " flowing water " to handle has guaranteed that " flowing water " recovers the continuity of back Data Stream Processing.
Under the prerequisite that above-mentioned internal data flow " flowing water " is handled, also realize by back level module pause function.Can send the time-out control signal when back level module resource is not enough, the TURBO encoder can suspend inner processing after receiving and suspending control, stops level dateout backward, and this specific character can alleviate the size of post processing module data buffering.
Also adopt ping-pong ram reception mechanism caching mechanism, reduced the stand-by period that TURBO encodes and handles between a plurality of code blocks.In order to reduce the piece number and the degree of depth of RAM, the present invention has finished by string and conversion process and has used the storage of the RAM of wider width to single bit data, has avoided use " elongated (bit wide is narrower, and the degree of depth is darker) " RAM, has saved area of chip simultaneously.
The present invention realizes that by ping-pong ram mechanism the TURBO encoder has the characteristic of accepting prime processing module processing " flowing water ", when ping-pong ram is full, send to prime automatically and suspend control signal, and do not require that the prime module suspends data output at once, the prime processing module can have a certain amount of output " flowing water ", suspend data output after a while again after promptly receiving halt signal, be convenient to be connected with the prime processing module.
Description of drawings
The schematic block diagram that Fig. 1 handles for downlink coding.
Fig. 2 is the schematic diagram of TURBO coding.
Fig. 3 is the coder structure figure of the TURBO sign indicating number of 3GPP protocol definition.
Fig. 4 is the coding flow chart.
Fig. 5 is prior art coding sequential chart.
Fig. 6 is the coding sequential chart of stream treatment of the present invention.
Fig. 7 is ping-pong ram and read-write control circuit figure.
Fig. 8 is the bits of encoded state machine diagram.
Fig. 9 is the realization circuit diagram of TC coding of the present invention.
Figure 10 is displacement control signal sequential chart.
Figure 11 is an encoding state machine schematic diagram.
Embodiment
For the time-delay that reduces the TURBO encoding process, the words that the processing of each bit time-delay is considered in the code block, not only to guarantee to export the shared cycle minimum of 3 bits of encoded that each bit generates, also to make continual continuous transmission between each bit stream as far as possible, form " flowing water " (promptly uninterrupted) control of inner each bit of code block.In addition, consider, also will guarantee the interrupted transmission between each code block as far as possible, form " flowing water " control of code block from each code block.
Still analyze referring to accompanying drawing 5, if the data behind the coding are serial output, export clock cycle of every bit stealing, owing to be output 3 bits, it is more satisfactory therefore taking 3 clock cycle after the encoding process of an input bit when output.From the sequential chart of accompanying drawing 5 as can be seen, Bit data coding needs visit RAM, the interleaving address memory of 1 visit interleaver altogether 3 times.Processing time for second check digit is the longest, at first will be with working as pre-treatment address lookup interleaving address memory, obtain interleaving address, need 3 clock cycle, visit RAM with interleaving address then, obtain the input data of second component coding, need 3 clock cycle, need 6 clock cycle altogether.And, all need 3 clock cycle for the processing of the system bits and first check digit.The present invention imports the digital coding processing with 1 bit and is divided into 3 bats (promptly taking 3 clock cycle), and first clock cycle is selected the result of interleaving address memory output, the value of the 2nd clock cycle and the 3rd clock cycle selection bit counter.And will visit RAM and visit interleaving address memory carries out parallel processing, and visit RAM is designed to " flowing water ", takies 3 clock cycle purposes as a result the time to reach the output of 1 bits of encoded.
Handle the coding schematic diagram below with reference to " flowing water " shown in the accompanying drawing 6 provided by the invention and describe, when having stored complete code block among the RAM, each bits of encoded adopts following steps in the code block:
Step 601: clap the 1st, inquiry interleaving address memory is promptly visited interleaving address memory, the address after being used to obtain to interweave with the value of bit counter as the reference address of interleaving address memory.
Step 602～603: clap and the 3rd bat the 2nd, remove to visit RAM as the reference address of RAM with the value of bit counter.
Step 604: the 4th claps the value of interleaving address memory output interleaving address, and removes to visit RAM with this value as the reference address of RAM.
Step 605: the 5th claps the RAM dateout, and these data corresponding 3 are clapped reading instruction of preceding (the 2nd clapping), and the data of reading are the data that do not interweave.
Step 606: the 6th claps the RAM dateout, and these data and the 5th are clapped identical, and corresponding is reading instruction of 3 bats preceding (the 3rd clapping).Clap the 6th, will handle the output system position to the 5th data of clapping RAM output simultaneously.
Step 607: the 7th claps the RAM dateout, and these data are reading instruction of 3 bats preceding (the 4th claps), are the data after interweaving.Clap the 7th, will handle the 6th data of clapping RAM output simultaneously, export first check digit.
Step 608: the 8th claps the data that the 7th bat RAM is exported handles, and exports second check digit.
Foregoing description be the processing procedure of a bit.In order to realize the uninterrupted flowing water step of handling between each bit, begin to carry out the processing of second bit in the 3 bat backs (promptly the 4th clapping) that first bit begins to handle; Begin to carry out the processing of the 3rd bit in the 3 bat backs (promptly the 7th clapping) that second bit begins to handle successively; Begin to carry out the processing of the 4th bit in the 3 bat backs (promptly the 10th clapping) that the 3rd bit begins to handle successively ... and the like, each 3 bat time of bit stealing.Corresponding, being understood that the coding result of second bit can be clapped output 9～11, the coding result of the 3rd bit can be clapped output 12～14, and the bit group behind each coding also takies 3 and claps.
See the cataloged procedure of a plurality of bits continuously, No. two selectors are selected the data of reading from the interleaving address memory at the first count of current bit, at second count with select the read address of the value of bit counter as ping-pong ram triple time.Here the action of the interleaving address memory that first count is selected promptly on a bit the 4th clap the action of selecting the interleaving address memory at it.
Can analyze, when each bit was imported continuously, per three cycles just can be exported the coding result of a bit, do not consider the output of tail bit, then code block (N that a comprises a bit) scramble time is 3 * N, and 12 * N of background technology will shorten very big time-delay relatively.From the angle of code block, the code block coding begins can have 5 time-delays of clapping to the output result, so the flowing water degree of depth is 5 clock cycle.When each code block also carried out flowing water control, when promptly Shu Ru code block was imported continuously, then each code block can be realized continuous output, and can not have the interval of 5 clock cycle between the code block.
The TURBO coding carries out according to code block, and for the transmission channel of big data quantity, the data that comprise a plurality of code blocks usually need be encoded.In order to realize the flowing water control of above-mentioned code block, the present invention need be designed to ping-pong structure with the RAM that TURBO encoder inside is used for buffer memory reception data, a processing that is used for current code block, another piece is used for the reception of next code block data, and the TURBO encoder can receive the data of the next code block of prime processing module (CRC adds module) output simultaneously when carrying out the coding of a code block like this.Below ping-pong ram of the present invention is described in detail.
The TURBO encoder is 1 bit bit wide from the data of prime processing module (CRC adds module) input, and the data volume of 1 code block maximum is 5114 bits.The buffer memory of data before the RAM of 2 5114 bits of needs is used to encode like this.Ping-pong ram structure as shown in Figure 7, ping-pong ram respectively is designed to store the data of 5120 bits, and wherein ping-pong ram is designed to the bit wide of 8 bits, and the degree of depth respectively is 640.This ping-pong ram can be designed to one physically, relies on the high address to distinguish table tennis.Do not adopt the single-bit bit wide during design, and single bit data string and convert 8 bit bit wides to, this is in order to reduce the degree of depth of RAM.
Ping-pong ram read-write control circuit as shown in Figure 7, the described control circuit of reading comprises: No. two selectors, the two-way input connects high 10 signals that add up after 640 of high 10 signals in external write address, external write address respectively, and output is exported to ping-pong ram as writing address signal; Decoder, low 3 signals in input termination external write address, output is exported to the eight bit register group as writing address signal; The eight bit register group also connects the external write data-signal, and output is exported to ping-pong ram as write data signal.
Described write control circuit comprises: No. two selectors, two-way input connect high 10 signals that add up after 640 of high 10 signals in external read address, external read address respectively, and output is exported to ping-pong ram as reading address signal; No. eight selectors, input connects the ping-pong ram output, and receives the control dateout of reading low 3 of address signal.
When writing data, determine to write low side (table tennis district) or high-end (pang the district) of RAM according to the table tennis sign.When writing data, at first single bit data is write in the registers group of 8 bits, specifically write in 8 registers which by the low 3 bits control that writes the address.Having write next bat of registers group, need write the content in the registers group among the RAM, the address of RAM is write high 10 bits of address and is controlled.In reading of data, select the low side of RAM or high-end according to table tennis sign.With the read address of high 10 bits of reading the address, select from RAM 1 bit of certain in the sense byte as the data of output with low 3 bits of reading the address simultaneously as RAM.
In DRP data reception process,,, ping-pong ram is all expired if encoding process is slower if the data rate that prime writes is very fast.If write new data this time again, can cause new data to cover the mistake of old data.In order to prevent that data from covering, when ping-pong ram is all expired, send 1 halt signal to prime, stop the data output of prime.Simultaneously, in order to keep certain " flowing water " surplus (as the surplus of 32 data) to prime, just send the time-out control signal when promptly will expire (also have 32 bit space can with) at ping-pong ram, when prime receives halt signal, 32 bits can be sent the back that finishes and suspend transmission like this.
By such scheme, can be implemented in the processing that suspends the prime module under the situation of inadequate resource, in order to reduce and the relevance of back level module, the TURBO coding is also wanted and can be suspended by back level module, is described below.We need regard the encoding process of 1 input bit as one " integral body ", and this " integral body " is a minimum unit that cannot be interrupted " flowing water ".If receive the halt signal of back level, could suspend current processing after must waiting until this " integral body " whole processed finishing, after just receiving the halt signal of back level, handle the coding of the current bit that has begun, and no longer the bit that does not begin to handle be encoded.
(1 bit input is exported 3 bits through the TC coding: system bits according to the TC coding characteristic, first check bit sum, second check digit), the TC encoding state is designed to comprise four sub-states: idle (Si), system bits is handled (Sa), and first check digit handles (Sb) and second check digit is handled (Sc).Referring to the bits of encoded state machine shown in Fig. 8, when carrying out the TC coding, be not suspended under the situation at the TC encoding state, state machine is at system bits (Sa), first check digit (Sb) and second check digit (Sc) cycling jump are finished dealing with up to the digital coding of a code block.And at each second check digit (Sc) state, need can judge whether to suspend, if be suspended then enter idle Si state, otherwise enter the Sa state.Under idle condition, if suspending, the back level cancels, encoder can jump to the Sa state again.TC encoding process state machine shown in the state transition See Figure 8.
Under idle condition, TC fgs encoder device does not have data output.We can be according to the state judgment data output effective marker of TC coding, and when idle condition effective marker marked invalid, other status indications are effective.Because having 5, encoding process claps " flowing water ", so when the output effective marker is judged, will consider this 5 influence of clapping " flowing water ".
Fig. 9 is the realization circuit of TC coding provided by the invention, and it finishes the coding (comprising the tail bit) of code block data.Mainly comprise: first computing module of the computing system position and first component coding, calculate second computing module of second component coding, the internal circuit of first computing module and second computing module identical with shown in Fig. 3 is so no longer good horse is stated.Also comprise bit counter, be used to write down when the bit place of pre-treatment figure place; The interleaving address memory stores interleaver matrix; Ping-pong ram provides data to write end and the address writes end, is used to receive the code block that will encode that higher level's module (CRC adds module) sends over and carries out buffer memory.The bit counter output is connected to interleaving address memory read address end, is also connected to an input of No. two selectors; Interleaving address memory read data output end is connected to another input of described No. two selectors; Described two road selector output ends are connected to described ping-pong ram and read the address end; Ping-pong ram read data output is connected to the input of first computing module, second computing module.
System bits output, first component output terminal, second component output are connected to the input of a triplexer, these three outputs are connected to the input of one four path multiplexer simultaneously with the feedback signal of second component, the output of described triplexer, four path multiplexers is connected to one two path multiplexer, and its output is exported to subordinate's module (rate-matched module).
Referring to the generation sequential of the displacement control signal shown in Figure 10, cataloged procedure is described simultaneously.When carrying out each bits of encoded, bit counter is counted the bit when pre-treatment, and clock cycle triple time is kept in each output of bit counter; Described No. two selectors control is sent to the interleaving address memory with the first count of bit counter output as the address of visiting the interleaving address memory, second count triple time of bit counter output is sent to ping-pong ram as the address of visit ping-pong ram, the interleaving address memory is sent to ping-pong ram in the 4th address after clapping the interweaving of output as the address of visit ping-pong ram; Ping-pong ram is the data bit that does not have through interweaving in the 5th, six data of clapping output, is received by first computing module and handles, and first computing module is clapped output the 6th, seven and obtained the system bits and first check digit; Ping-pong ram is the data bit that process interweaves in the 7th data of clapping output, is received by second computing module and handles, and second computing module is clapped output the 8th and obtained second check digit.
After all bit process of a code block finish, need output tail bit.Some is different for the processing method of output of tail bit and normal bit output, at first is the data of handling first component, and then handles the data of second component.When the tail bit is exported, do not need reading of data from ping-pong ram, the input of shift register is the feedback bits of self.When the shift register group of the first component correspondence generates the tail bit, output system position at first, export the operation result of this registers group then, after output finishes, this registers group displacement once, then handle next time, such process circulation 3 times, the content in this registers group is all handled.Then, by the shift register group generation tail bit of second component correspondence, process is identical with registers group A, and no longer good horse is stated, specifically can be referring to the displacement control signal sequential chart of Figure 10.
Whole cataloged procedure can be divided into 4 states: initial state (S0), wait state (S1), TC encoding state (S2) and tail bit output state (S3).Referring to the encoder state diagram shown in Figure 11.Be in initial condition at the back TC encoder that resets, after receiving the coding enabling signal, enter wait state.
When being in wait state, could break away from wait state after 2 conditions of needs satisfy simultaneously and jump to next state (TC encoding state): 1, the TC interleaving address calculates and finishes, and the TC interleaver is idle; 2, ping (pang) received the data of a whole code block among the RAM.
In TC encoding state inside a bit counter is arranged, encoded bit number is counted, when the counting number reaches code block length, jump to NextState (output of tail bit).Encoding process state inside comprises 4 sub-states again: idle (Si), system bits is handled (Sa), and first check digit handles (Sb) and second check digit is handled (Sc).(referring to Fig. 8).At the Sc state, bit counter adds 1, represents that a bit process finishes.As can be seen, generally per 3 clock cycle of bit counter count once.
In tail bit output state inside, a tail bit counter is arranged, the tail number of bits of output is counted, when having exported the individual tail bit of certain number (as 12), jump to next state.Next state is which state is judged according to a current treated code block counter.When if treated code block number equals the code block number of parameter configuration, all code blocks are handled in expression, jump to initial condition; Otherwise the code block that expression has been untreated in addition jumps to wait state.A code block counter is safeguarded under tail bit output state, enters tail bit output state at every turn, and a code block counter adds 1.
In these 4 states, S2 and S3 state need dateout, in order to be suspended by the back level, these two states all will support to suspend processing capacity theoretically, but consider the complexity that reduces control, for S3 state (tail bit output state), can be designed to not consider to suspend this situation.For the S3 state, fixedly take 12 clock cycle (because the appearance of this situation, the back level need be reserved 12 cushion spaces at least, prevents " flowing water " output) like this.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1, a kind of TURBO coding method, the coding step of each code block comprises: the coding step of each bit in the code block, the tail bit in code block after all bits of encoded end generate step; The coding step generation system position of described each bit, first check bit sum, second check digit; It is characterized in that each bits of encoded step comprises:
The 1st claps, and current bit figure place in the code block under it is read the interleaving address memory as the address of visit interleaving address memory;
The 2nd claps and the 3rd bat, claps described figure place with the 1st respectively and reads RAM as the address of visit RAM; Described RAM stores described code block;
The 4th claps, and the interleaving address memory is finished the response that reads instruction before 3 bats, exports interleaving address, and this interleaving address is read RAM as the address of visit RAM;
The 5th claps, and RAM finishes and claps the preceding response that reads instruction, dateout to 3;
The 6th claps, and RAM finishes and claps the preceding response that reads instruction, dateout to 3; And the 5th data of clapping RAM output are exported as system bits;
The 7th claps, and RAM finishes and claps the preceding response that reads instruction, the data after output interweaves to 3; And the 6th data of clapping RAM output are carried out first component coding generate the output of first check digit;
The 8th claps, and the 7th data of clapping RAM output is carried out the second component coding generate the output of second check digit.
2, method according to claim 1 is characterized in that, further comprises: clap the coding step that the back starts next bit in each bits of encoded initial 3 successively.
3, method according to claim 2 is characterized in that, further comprises: after cataloged procedure is received pause instruction, stop to start the coding of next bit, and finish the current coding step that is in the bit in the cataloged procedure.
4, method according to claim 1 is characterized in that, described RAM is a ping-pong ram, and the different code blocks that encode are buffered in the ping-pong ram with ping-pong buffer mechanism.
5, method according to claim 1, it is characterized in that, further comprise: when the RAM data in buffer also has N bit just to expire, send the data output that pause instruction suspends the prime module to the prime module, and also can continue to send N bit after making prime receive instruction.
6, method according to claim 1, it is characterized in that, tail bit after all bits of encoded finish in code block generates step and comprises the step that starts the generation of tail bit, the step that starts the generation of tail bit is: the number that writes down coded bit, when described number arrives code block length, start the tail bit and generate step.
7, a kind of TURBO code device comprises: second computing module of first computing module of the computing system position and first component coding, calculating second component coding, it is characterized in that, and also comprise:
Bit counter is used for writing down the figure place of the bit of present encoding at its code block;
The interleaving address memory stores interleaver matrix;
RAM is used for the code block that buffer memory will be encoded;
The bit counter output is connected to interleaving address memory read address input end, is also connected to an input of No. two selectors; Interleaving address memory read data output end is connected to another input of described No. two selectors;
Described two road selector output ends are connected to described RAM and read address input end; Described RAM read data output is connected to the input of first computing module, second computing module respectively;
When carrying out each bits of encoded, each count value of bit counter output is kept clock cycle triple time; No. two selectors select the first count of each figure place of bit counter output to be sent to the interleaving address memory, second count triple time to be sent to ping-pong ram, and the interleaving address memory is sent to ping-pong ram in the 4th data of clapping output; Ping-pong ram is clapped the data of exporting the 5th, six and is received the processing generation system position and first check digit, handled generation second check digit in the 7th data of clapping output by the reception of second computing module by first computing module.
8, device according to claim 7 is characterized in that, described RAM is a ping-pong ram.
9, device according to claim 8 is characterized in that, described ping-pong ram is 8 bit bit wides, and the 640 byte degree of depth rely on the high address to distinguish the RAM of table tennis.
10, device according to claim 9 is characterized in that, described ping-pong ram also comprises the reading and writing control circuit that connects ping-pong ram; The described control circuit of reading comprises:
No. two selectors, two-way input connect high 10 signals that add up after 640 of high 10 signals in external write address, external write address respectively, and output is exported to ping-pong ram as writing address signal;
Decoder, low 3 signals in input termination external write address, output is exported to the eight bit register group as writing address signal; The eight bit register group also connects the external write data-signal, and output is exported to ping-pong ram as write data signal;
Described write control circuit comprises:
No. two selectors, two-way input connect high 10 signals that add up after 640 of high 10 signals in external read address, external read address respectively, and output is exported to ping-pong ram as reading address signal;
No. eight selectors, input connects the ping-pong ram output, and receives the control dateout of reading low 3 of address signal.
11, a kind of TURBO coding method is characterized in that, the corresponding codes circuit comprises:
Second computing module of first computing module of the computing system position and first component coding, calculating second component coding; Be used for writing down the bit counter of the bit of present encoding in the figure place of its code block; Store the interleaving address memory of interleaver matrix; Will the encode RAM of code block of buffer memory;
The bit counter output is connected to interleaving address memory read address end, is also connected to an input of No. two selectors; Interleaving address memory read data output end is connected to another input of No. two selectors; Two road selector output ends are connected to described ping-pong ram and read the address end; Ping-pong ram read data output is connected to the input of first computing module, second computing module;
Described coding method comprises: the coding step of each bit in the code block, the tail bit in code block after all bits of encoded end generate step; Each bits of encoded step comprises:
Each count value that bit counter is exported is successively continuously kept clock cycle triple time;
No. two selectors select the first count of the data of bit counter output to be sent to the interleaving address memory as reading instruction, select the second count triple time of bit counter output to be sent to RAM, and the interleaving address memory is sent to RAM in the 4th data of clapping output as reading instruction as reading instruction;
Ping-pong ram is clapped the data of exporting the 5th, six and is received the processing generation system position and first check digit, handled generation second check digit in the 7th data of clapping output by the reception of second computing module by first computing module.
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