CN101034894A - Circuit and method for realizing the decoding - Google Patents
Circuit and method for realizing the decoding Download PDFInfo
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- CN101034894A CN101034894A CN 200710000464 CN200710000464A CN101034894A CN 101034894 A CN101034894 A CN 101034894A CN 200710000464 CN200710000464 CN 200710000464 CN 200710000464 A CN200710000464 A CN 200710000464A CN 101034894 A CN101034894 A CN 101034894A
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Abstract
The invention provides a realization decoding electric circuit, which includes: Data buffer unit and error correction unit; The data buffer unit, which used to receive the code word, and put it into the error correction unit after stating the symbol detention hypothesis cycle. The error correction unit, which used to receive states the symbol and states the symbol the wrong position and the wrong value, to state the symbol to carry on error correction processing. After the error correction processing symbol transmits. This electric circuit also includes: Decoding combinatory logic unit; This unit includes: First sub- part group, second sub- part group and third sub- part group; The number of first-part of the first sub- part group, second-part of the second sub- part group, third-part of the third sub- part group are separately act according to each sub- part the handling ability design. The number of second-part is less then the first-part and the third-part. The invention also provides a realization decoding the method; and through used this method and the electric circuit reduces the scale of decoded the electric circuit.
Description
Technical field
The present invention relates to decoding technique, the particularly a kind of circuit and method of decoding of realizing.
Background technology
Bo Si-Cha Dehuli-Huo Kun lattice nurse (BCH) sign indicating number is by rich this (Bose), Cha Dehuli (Chaudhuri) and Huo Kun lattice nurse (Hocquenhem) invention, so with the beginning letter of these three inventor's names this sign indicating number is named.
BCH code is a kind of cyclic code, utilizes division to carry out correction process.Reed-Solomon (RS) sign indicating number is a kind of of BCH code, this yard is taken as a kind of special BCH code, do not distinguish BCH code and RS sign indicating number in the present invention, is referred to as BCH code, error correcting capability and circuit easily realize because BCH code has preferably, therefore are widely used in communication system.Following mask body is introduced the circuit of realizing the BCH code decoding in the prior art.
Fig. 1 is first kind of electrical block diagram realizing the BCH code decoding in the prior art.As shown in Figure 1, this circuit comprises: sub-decoder 1, the sub-decoder m of sub-decoder 2......
If total m code word interweaves and constitute total encoding and decoding, each code word is a subcode of this m code word, and the sign indicating number type of the code word of being mentioned in present specification is the code word of same type.Fig. 2 is the structural representation of m code word in the data flow.As shown in Figure 2,
This m code word adopts the mode that interleaves to sort, and first code element of m code word of discharging is second code element of m code word then earlier, is arranged in order down, up to p+1 code element of m code word.
P+1 code element of this m code word is input to sub-decoder 1 respectively successively, the sub-decoder m of sub-decoder 2....M sub-decoder carries out decoding processing to m code word under the control of control circuit, then will be through m code word output of decoding processing.This shows, because the sign indicating number type of m code word is identical, sub-decoder 1, the circuit structure of the sub-decoder m of sub-decoder 2... is identical, so this circuit design scheme is very simple, but there is such problem:, therefore can make the scale of circuit huger, and the utilance of circuit resource is not high because each sub-decoder only is responsible for handling a code word.
Because in the such scheme, BCH code decoding circuit resource utilization is not high, introduce and second kind of more approaching scheme of the present invention below, realize the circuit of BCH code decoding.
Fig. 3 is second kind of electrical block diagram realizing the BCH code decoding in the prior art.As shown in Figure 3, this circuit comprises: first data buffer storage unit 300, second data buffer storage unit 320 and decoder 310.
Wherein, decoder 310 comprises: sub-decoder 1, the sub-decoder k of sub-decoder 2.....N represents the multiplexing number of k sub-decoder, just the number of the code word that can handle of each sub-decoder.M is the number that is input to the code word of decoding circuit, the number of the code word that comprises in the data flow of expression input.N equals the value of Rin divided by the carry integer of Rd.For example, Rin equals 9.6Mbps, and Rd equals 3Mbps, gets n so and equals 4, and wherein, Rin is the bandwidth of input traffic, and Rd represents the data bandwidth that each sub-decoder can be handled, the i.e. disposal ability of sub-decoder.
Because the multiplexing number of times of each sub-decoder is n, thus each sub-decoder will be successively to 1, a 2....n code word carries out decode operation.As can be seen from Table 1, code word interleaves ordering, to decode successively to this n code word, this scheme at first is stored in this n code word in first data buffer storage unit 300 successively, then according to (the 1st code element of subcode 0, the 2nd code element of subcode 0 ... p+1 code element of .. subcode 0), ... (the 1st code element of subcode n-1, the 2nd code element of subcode n-1 ... p+1 the code element of subcode n-1) order, therefrom reading n code word successively sends to sub-decoder and carries out decoding processing, code word after the decoding processing is outputed to second data buffer storage unit 320, after the group decoder is finished the decoding of this n code word, again this n is read from second data buffer storage unit 320 successively through the code word of decoding processing, be inserted in the data flow and export.
First data buffer storage unit 300 is used to receive and deposit the preceding code word of decoding.
Second data buffer storage unit 320 is used for receiving and depositing decoded code word.
Fig. 4 is the structural representation of each sub-decoder of decoding circuit shown in Figure 3.As shown in Figure 4, this circuit comprises: follow calculating formula cell S 401, iteration unit I402, ask errors present and improper value unit C403, error correction unit 404 and data buffer storage unit 405.
Follow calculating formula cell S 401, be used to receive code word, the code word that receives is carried out residue earlier calculate, calculate syndrome then, syndrome result of calculation is outputed to iteration unit I402.Here said residue is calculated and is meant: will be with input symbols as the multinomial of coefficient as by the formula of removing, obtain residue divided by primitive polynomial.So-called syndrome is meant: obtain after whole residues, the formula that the homogeneous power coefficient combination of each residue is obtained is called syndrome.
Iteration unit I402, be used to receive the syndrome result of calculation of syndrome cell S 401 outputs, adopt the coefficient of the method calculating error location polynomial of iteration, if coefficient all is 0, it is errorless that expression is input to each code element of code word of sub-decoder, otherwise the code element of expression input is wrong, obtains the value of corresponding error constant, the result of iterative computation is outputed to ask errors present and improper value unit C403.
Ask errors present and improper value unit C403, receive the result of the iterative computation of iteration unit I402 output, obtain the position and the improper value of wrong code element, errors present and improper value are sent to error correction unit 404.
Data buffer storage unit 405 is used to receive the code word that is input on this sub-decoder, will output to error correction unit 404 behind these codeword delay setting cycles.
From Fig. 3 and embodiment shown in Figure 4 as can be seen, all comprising one in each sub-decoder follows calculating formula cell S, iteration unit I and one to ask errors present and improper value unit C.If being input to the data bandwidth of decoder is 3.2Gbps, if the minimum of decoder can be handled 800Mbps, the number m=3.2Gbps/800Mbps=4 of the sub-decoder that needs so, promptly need 4 sub-decoders to carry out concurrent working, promptly entire decoder needs 4 to follow calculating formula cell S, 4 iteration unit I and 4 to ask errors present and improper value unit C.Because the circuit resource of iteration unit I is bigger, and much larger than the circuit resource of following calculating formula cell S and iteration unit I, so entire circuit is larger.
This shows, the scheme of the decoding circuit of available technology adopting, the circuit resource of whole decoding circuit is bigger.
Summary of the invention
Embodiments of the invention provide a kind of circuit of decoding realized, this decoding circuit can reduce circuit scale.
Embodiments of the invention provide a kind of method of decoding of realizing, this coding/decoding method can reduce circuit scale.
In order to reach above-mentioned first purpose, the embodiment of the invention provides a kind of circuit of decoding realized, this circuit comprises: data buffer storage unit and error correction unit;
Described data buffer storage unit is used to receive code word, postpones behind the setting cycle described code word to be outputed to error correction unit;
Described error correction unit is used to receive the errors present and the improper value of described code word and described code word, and described code word is carried out correction process, and described code word through correction process is sent;
It is characterized in that this circuit further comprises: the decoding combinatorial logic unit; Described decoding combinatorial logic unit comprises: the first subassembly group, the second subassembly group and the 3rd subassembly group;
The number of subassembly three in the number of subassembly two and the 3rd subassembly group in the number of subassembly one, the second subassembly group in the described first subassembly group, be respectively according to the design of the disposal ability of each subassembly, the number of described subassembly two is less than the number of described subassembly one and subassembly three respectively;
The described first subassembly group is used to receive code word, and described code word is carried out residue calculating and syndrome calculating, and the result of calculation that described residue is calculated and syndrome calculates is outputed to the second subassembly group;
The described second subassembly group is used to receive the described result of calculation that the first subassembly group is exported, and described result of calculation is carried out iterative computation, and described iterative computation result is exported to the 3rd subassembly group;
Described the 3rd subassembly group is used to receive described iterative computation result, obtains errors present and improper value, and described errors present and improper value are outputed to described error correction unit.
In order to reach second purpose of the present invention, the invention provides a kind of method of decoding of realizing, it is characterized in that, in decoding circuit, be provided with in advance: comprise subassembly one the first subassembly group, comprise the second subassembly group of subassembly two and comprise the 3rd subassembly group of subassembly three; The number of described subassembly two is less than the number of described subassembly one and subassembly three respectively;
The code word of described first subassembly group of received input is carried out residue calculating and syndrome calculating to described code word;
The described second subassembly group is carried out iterative computation according to the result of calculation that described residue is calculated and syndrome calculates to described code word;
Described the 3rd subassembly group is obtained the errors present and the improper value of described code word according to described iterative computation result;
According to errors present and improper value described code word is carried out correction process.
By technical scheme of the present invention, the decoding circuit that the embodiment of the invention provided comprises: decoding combinatorial logic unit, data buffer storage unit and error correction unit.In the present invention, the decoding combinatorial logic unit comprises: the first subassembly group, the second subassembly group and the 3rd subassembly group; The number of subassembly three in the number of subassembly two and the 3rd subassembly group in the number of subassembly one, the second subassembly group in the described first subassembly group, be respectively according to the design of the disposal ability of each subassembly, the number of described subassembly two is less than the number of subassembly one and subassembly three respectively;
As can be seen from the above technical solutions, the decoding circuit that the embodiment of the invention provided can carry out decoding processing to the code word that interweaves, and broken the notion of sub-decoder of the prior art, number and disposal ability according to the code word that is input to decoding circuit design the first subassembly group and the 3rd subassembly group, design the second subassembly group according to disposal ability and the number that is input to the code word of decoding circuit.Compare in the prior art, the situation that subassembly one, subassembly two and subassembly three numbers equate, in the present invention, the number of subassembly two will be respectively less than the number of subassembly one and subassembly three, again because the circuit resource of subassembly two is bigger, so the circuit resource of the decoding combinatorial logic unit of the embodiment of the invention is less than the circuit resource sum of all sub-decoders of decoding circuit in the prior art, therefore use technical scheme of the present invention to greatly reduce circuit scale.
Description of drawings
Fig. 1 is first kind of electrical block diagram realizing the BCH code decoding in the prior art;
Fig. 2 is the structural representation of m code word in the data flow;
Fig. 3 is second kind of electrical block diagram realizing the BCH code decoding in the prior art;
Fig. 4 is the structural representation of each sub-decoder in the decoding circuit shown in Figure 3;
Fig. 5 is the structural representation of first preferred embodiment of the realization BCH code decoding circuit of the embodiment of the invention;
Fig. 6 is the structural representation of second preferred embodiment of the realization BCH code decoding circuit of the embodiment of the invention;
Fig. 7 is the structural representation of the 3rd preferred embodiment of the realization BCH code decoding circuit of the embodiment of the invention;
Fig. 8 is the schematic flow sheet of the 4th preferred embodiment of method of the realization BCH code decoding of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with accompanying drawing.
Embodiments of the invention provide a kind of circuit and method of decoding of realizing, this decoding circuit comprises: decoding combinatorial logic unit, data buffer storage unit and error correction unit.In embodiments of the present invention, can carry out decoding processing to the code word that interweaves, and the notion that does not have sub-decoder, decoding combinatorial logic unit comprised syndrome computing unit S, the iteration unit I that carries out decoding processing that be useful on and ask errors present and improper value unit C.Wherein, the number of these unit is respectively: use the value of the number of the code word that is input to decoding circuit divided by the disposal ability gained merchant's of each unit carry integer, generally speaking, the number of syndrome computing unit S equals to ask the number of errors present and improper value unit C, and number greater than iteration unit I, the number that wherein is input to the code word of decoding circuit is meant, the number of code word, i.e. interleave depth in being input to one section interleaving data code stream of decoding circuit.
Fig. 5 is the structural representation of first preferred embodiment of the realization BCH code decoding circuit of the embodiment of the invention.
This decoding circuit comprises: decoding combinatorial logic unit 500, data buffer storage unit 510 and error correction unit 520.
This decoding combinatorial logic unit 500 comprises: the first subassembly group 501, the second subassembly group 502 and the 3rd subassembly group 503; Wherein, the number of subassembly 3 503 in the number of subassembly 2 502 and the 3rd subassembly group 503 in the number of subassembly 1, the second subassembly group 502 in the first subassembly group 501, all be respectively according to the design of the disposal ability of each subassembly, the number of subassembly 2 502 will be less than the number of subassembly 1 and subassembly 3 503 respectively.
The first subassembly group 501 is used to receive code word, and each code element of these code words is carried out residue calculating and syndrome calculating, and result of calculation is outputed to the second subassembly group 502.
The second subassembly group 502 is used to receive the result of calculation that the first subassembly group 501 is exported, and these result of calculations are carried out iterative computation, and the iterative computation result is outputed to the 3rd subassembly group 503.
The 3rd subassembly group 503 is used to receive the iterative computation result, obtains errors present and improper value, and errors present and the improper value of obtaining outputed to error correction unit 520.
Data buffer storage unit 510 is used to receive code word, postpones behind the setting cycle code word that receives to be outputed to error correction unit 520.
In the present embodiment, the reason that comprises data buffer storage unit 510 in decoding circuit is: because 500 pairs of code words that receive of decoding combinatorial logic unit are handled, the errors present and the improper value that calculate code word need the regular hour, the code word that makes error correction unit 520 receive errors present and improper value synchronously and need error correction must be input to data buffer storage unit 510 with code word earlier and carry out caching process.The setting cycle that needs to postpone is determined according to the processing speed of the number reconciliation code combination logical block 500 of the code word that is input to decoding circuit; data buffer storage unit 510 can be the same with the 26S Proteasome Structure and Function of the data buffer storage unit of prior art neutron decoder, and its circuit scale equals the data buffer storage unit scale sum in all sub-decoders substantially.The code word that is input to decoding circuit is divided into identical two-way, and one the tunnel is input to decoding combinatorial logic unit 500, and another road is imported into data buffer storage unit 510.The method that 520 pairs of code words of error correction unit are carried out correction process is: error correction unit 520 asks XOR to handle errors present and improper value that receives and the code word that needs correction process, this method of operation can be same as the prior art, for simplicity, do not give unnecessary details with regard to not doing here.
The decoding circuit that relates in the present embodiment comprises: decoding combinatorial logic unit 500, data buffer storage unit 510 and error correction unit 520.This decoding combinatorial logic unit 500 receives the code word of a plurality of Bose-Chaudhuri-Hocquenghem Codes that interweave that are input to decoding circuit, it is to be noted, each sub-decoder of the prior art receives only the single code word that is input on it at every turn, and the embodiment of the invention the code word that can handle be the code word of the Bose-Chaudhuri-Hocquenghem Code that interweaves.
In the embodiment shown in fig. 5, introduced the general structure of the decoding circuit that the embodiment of the invention provided.Decoding combinatorial logic unit 500 in the present embodiment further comprises caching control unit again, introduces the concrete structure and the function of decoding combinatorial logic unit 500 in the circuit shown in Figure 5 in ensuing embodiment.
Fig. 6 is the structural representation of second preferred embodiment of the realization BCH code decoding circuit of the embodiment of the invention.As shown in Figure 6, compare with decoding circuit shown in Figure 5, this decoding combinatorial logic unit 600 also comprises: caching control unit 604;
In the present embodiment, subassembly 1 can be syndrome computing unit S, and subassembly 2 502 can be iteration unit I, and subassembly 3 503 can be to ask errors present and improper value unit C.The number of subassembly 1, subassembly 2 502 and subassembly 3 503 equals to be input to the number of code word of decoding circuit respectively divided by the value of the carry integer of dealing with ability separately, and the number of general subassembly 1 equals the number of subassembly 3 503.The number of subassembly 2 502 equals to be input to the number of code word of decoding circuit divided by the value of the disposal ability gained merchant's of subassembly 2 502 carry integer, and respectively less than the number of subassembly 1 and subassembly 3 503.
In the embodiment shown in fig. 6, introduced the internal structure of decoding combinatorial logic unit in the decoding circuit.In ensuing embodiment, with subassembly 1 is syndrome computing unit S, subassembly 2 502 is iteration unit I, subassembly 3 503 is an example for asking errors present and improper value unit C, introduce and how to design the BCH code decoding circuit according to the number of the code word that is input to decoding circuit and the disposal ability of each subassembly, the internal structure to caching control unit 604 is described further in addition.
Fig. 7 is the structural representation of the 3rd preferred embodiment of the realization BCH code decoding circuit of the embodiment of the invention.As shown in Figure 7, this circuit comprises: decoding combinatorial logic unit 700, data buffer storage unit 710 and error correction unit 720.Wherein, decoding combinatorial logic unit 700 comprises: syndrome computing unit S701, iteration unit I702, ask errors present and improper value unit C703, S/I buffer 704, control unit 705 and the 3rd subassembly group buffer unit 706, here the 3rd subassembly group buffer unit 706 is C buffer unit 706.
In the present embodiment, for example, clock frequency f=100MHz, the bandwidth Rin=3.2Gbps=3200Mbps of input data, the data of this 3200Mbps are by 16 RS (255,239) intersymbol is inserted and is formed, so the shared bandwidth of each RS sign indicating number is 200Mbps, is input to the number m=16 of the code word of decoding circuit.Wherein, information code is 239 bytes, adds that the check code of 16 bytes comes to 255 bytes.Because syndrome computing unit S701 and ask errors present and each cycle of improper value unit C703 can handle the data of 1 byte, so Rd=8bit/T=8bit/ (1/100M) s=800Mbps, 800Mbps is 4 bandwidth that code word is shared, the disposal ability that is these two unit is 4 code words, so equate with the number of asking errors present and improper value unit C702 according to syndrome computing unit S701, and the number of code word that equals to be input to decoding circuit is divided by the value of disposal ability gained merchant's carry integer, therefore, syndrome computing unit S701 and ask the number of errors present and improper value unit C702 to equal respectively: 16/4=4 promptly needs 4 syndrome computing unit S701 and asks errors present and improper value unit C703.For the situation of correcting 8 mistakes, if being carried out iteration, a subcode needs 8 clock cycle, each clock week of iteration unit I702 can be handled the data of 32 bytes of 255/8 ≈, because syndrome computing unit S701 and ask errors present and each clock cycle of improper value unit C703 can only handle the data of 1 byte, so the disposal ability of iteration unit I702 is syndrome computing unit S701 or asks errors present and 32 times of improper value unit C703, is 32*4=128 code word; The number of code word that equals to be input to decoding circuit according to the number of iteration unit I702 is divided by the value of the disposal ability gained merchant's of iteration unit I602 carry integer, the number that is iteration unit I702 equals: 16/128 ≈ 0.125, get carry integer 1, so an iteration unit I promptly can finish the iterative computation of 16 RS (255,239) sign indicating number.Therefore this BCH code decoding circuit needs 4 sub-syndrome computing units: S1, S2, S3 and S4; 4 sons are asked errors present and improper value unit: C1, C2, C3 and C4, and 1 iteration unit I702.
Four sub-syndrome computing units of syndrome computing unit S701: S1, S2, S3 and S4 receive four code words respectively, and each code element of these code words is carried out residue calculating and syndrome calculating, and result of calculation is outputed to S/I buffer 704.
S/I buffer 704, be used to receive the result of calculation of syndrome computing unit S701 output, receive the control signal that control unit 705 sends, under the effect of control signal, the syndrome result calculated is outputed to iteration unit I702, also be used to receive the iterative computation result of iteration unit I702 output, the result of this iterative computation outputed to ask errors present and improper value list C703.Here it is to be noted: S/I buffer 704 can be for a buffer that is provided with separately, in order to save the inside that resource also can be integrated in syndrome computing unit S701 or iteration unit I702.
In the present embodiment, for example, syndrome computing unit S701 and ask the disposal ability of errors present and improper value unit C703 to be respectively 4 code words, the disposal ability of iteration unit I702 is about 128 code words, 16 RS that interweave (255,239) code word is made the as a whole syndrome computing unit S1 that is imported into, S2, on S3 and the S4, have only after S/I buffer 704 is finished and outputed to these four syndrome computing units to these 16 codeword codings, control unit 705 produces control signal, and notice iteration unit I702 reads by its discharging order these 16 code words that interleave ordering from S/I buffer 704.Equally, after carrying out iterative computation to these 16 code words, iteration unit I702 outputs to S/I buffer 704; Control unit 705 produces control signal, and notice asks errors present and improper value unit C703 to read from S/I buffer 704.It is pointed out that herein description just to a better embodiment of present embodiment, is not to be limitation of the invention.
The design of control unit 705 and S/I buffer 704 is very crucial, because sub-syndrome computing unit and son are asked errors present and improper value unit, unequal with the number of iteration unit, the disposal ability of iteration unit I702 will be respectively greater than sub-syndrome computing unit S701 and the sub disposal ability of asking errors present and improper value unit C703, the number of the iteration unit I702 that comprises in the decoding combinatorial logic unit will be respectively less than syndrome computing unit S701 and the number of asking errors present and improper value unit C703, so control signal that needs control unit 705 and S/I buffer 704 to send according to control unit 705, to syndrome computing unit S701, iteration unit I702 and ask the read-write of errors present and improper value unit C703 to cooperate each subelement is controlled could realize the normal consistency work of each described each unit of subassembly.
Iteration unit I702 is used for reading the syndrome result calculated from S/I buffer 704, and this result of calculation is carried out iterative computation, and the result of iterative computation is outputed to S/I buffer 704.
Ask errors present and improper value unit C703, be used for reading the result of iterative computation, obtain the errors present and the improper value of this code word, this errors present and improper value are outputed to C buffer unit 706 from S/I buffer 704.
Since C1, C2, C3 and C4 all can four code words of parallel computation errors present and improper value, whenever calculate an errors present and improper value, then this errors present and improper value are stored in C buffer unit 706, after C1, C2, C3 and C4 calculated the errors present of four code words and improper value and be stored in C buffer unit 706, this C buffer unit 706 outputed to error correction unit 720 with these errors presents and improper value.It is pointed out that processing described here also can adopt following mapping mode: whenever calculate the errors present and the improper value of a code word, 706 of this C buffer units output to error correction unit 720 with this errors present and improper value and carry out correction process.
Data buffer storage unit 710 is used to receive the code word that is input to decoding circuit, and according to the processing speed of decoding processing logical block 700, all after dates that postpone to set output to error correction unit 720 with the code word that receives.
In Fig. 5, Fig. 6 and embodiment shown in Figure 7, introduced the circuit of realizing the BCH code decoding, realize the idiographic flow of the method for BCH code decoding below with the specific embodiment introduction.
Fig. 8 is the schematic flow sheet of the 4th preferred embodiment of method of the realization BCH code decoding of the embodiment of the invention.As described in Figure 8, this method may further comprise the steps:
Step 810: subassembly one, subassembly two and subassembly three are set in each subassembly group in advance; And the number of the subassembly two that is provided with is respectively less than the number of subassembly one and subassembly three.
In this step, the first subassembly group, the second subassembly group and the 3rd subassembly group are set in decoding circuit; In the first subassembly group, subassembly one is set, subassembly two is set in the second subassembly group, in the 3rd subassembly group, subassembly three is set.Each subassembly of being mentioned is respectively: syndrome computing unit S, iteration unit I and ask errors present and improper value unit C.The number of each subassembly equals to be input to the number of code word of decoding circuit respectively divided by the disposal ability gained merchant's of each subassembly carry integer value, the disposal ability of general subassembly two will be respectively greater than the disposal ability of subassembly one and subassembly three, so the number of the subassembly two that is provided with will be respectively less than the number of subassembly one and subassembly three.
Step 820: the code word that receives is carried out residue calculating to the first subassembly group and syndrome calculates.
Step 830: the second subassembly group is carried out iterative computation according to the result of calculation that residue is calculated and syndrome calculates to code word.
Step 840: the 3rd subassembly group is obtained the errors present and the improper value of code word according to the iterative computation result.
Step 850:, the code word that receives is carried out correction process according to errors present and improper value.
In this step, ask XOR to handle the errors present that calculates and improper value and code word, this processing method can be same as the prior art, just do not do here for simplicity and do not give unnecessary details.
Because the speed of syndrome computing unit S, the processing speed of asking errors present and improper value C and iteration unit I is unequal, thus between the respective handling step, add caching process, can the code word that receive being carried out Synchronous Processing.The first subassembly group is carried out residue calculating and syndrome calculating to the code word that receives after, be after the step 820 and step 830 between, result of calculation is outputed to caching control unit carry out caching process, when the enough iteration unit I of result of calculation of residue calculating of depositing in the caching control unit and syndrome calculating carry out single treatment, the result of calculation of depositing in the caching control unit is outputed to iteration unit I, carry out the operation of step 830.Equally, owing to ask the disposal ability of the disposal ability of errors present and improper value unit C, so can also comprise the steps: that between step 830 and step 840 iteration unit I outputs to caching control unit with the result of iterative computation and carries out caching process less than iteration unit I.
It is to be noted, said code word is meant the code word that is input to the syndrome computing unit S in the decoding combinatorial logic unit in step 820, be meant to be input to data buffer storage unit the code word after data buffer storage unit postpones setting cycle in the code word described in the step 850.These two kinds of code words are identical in terms of content, and the decoding combinatorial logic unit receives the code word that is input on it, and calculates the errors present and the improper value of this code word, and error correction unit is carried out xor operation with these two kinds of code words then, exports correct code word.
Decoding circuit of the prior art comprises a plurality of sub-decoders, each sub-decoder all comprises: syndrome computing unit S, iteration unit I, one ask errors present and improper value unit C, a data buffer unit and an error correction unit, so syndrome computing unit S, iteration unit I in the decoding circuit and ask errors present and the number of improper value unit C equates, and the number of the most weak unit of computing capability has determined the number of sub-decoder among the three.
From embodiments of the invention as can be seen, because syndrome computing unit S, iteration unit I in the decoding circuit and ask errors present and improper value unit C handles code word according to the mode of streamline, so the unit of back relies on the unit of front, but do not influence the processing of unit, front.Broken the notion of sub-decoder in embodiments of the present invention, the decoding circuit that the embodiment of the invention provides comprises: decoding combinatorial logic unit, a data buffer unit and an error correction unit, and design the syndrome computing unit S in the decoding combinatorial logic unit and ask errors present and improper value unit C according to the disposal ability of each subassembly, design iteration unit I in the decoding combinatorial logic unit according to sign indicating number type, error correcting capability and the number that is input to the code word of decoding circuit.As can be seen, the number of iteration unit I will be less than syndrome computing unit S and the number of asking errors present and improper value unit C respectively in embodiments of the present invention, again because the circuit scale of iteration unit I much larger than the circuit scale of syndrome computing unit S with ask the circuit scale of errors present and improper value unit C, so use technical scheme of the present invention can reduce the scale of circuit greatly.
Realization decoding circuit and method that the embodiment of the invention provided mainly are circuit and the methods that designs at BCH code, have being equal to of same principle, the circuit that substitutes and method also within protection scope of the present invention for other.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1, a kind of circuit of decoding realized, this circuit comprises: data buffer storage unit and error correction unit;
Described data buffer storage unit is used to receive code word, postpones behind the setting cycle described code word to be outputed to error correction unit;
Described error correction unit is used to receive the errors present and the improper value of described code word and described code word, and described code word is carried out correction process, and described code word through correction process is sent;
It is characterized in that this circuit further comprises: the decoding combinatorial logic unit; Described decoding combinatorial logic unit comprises: the first subassembly group, the second subassembly group and the 3rd subassembly group; The number of subassembly three in the number of subassembly two and the 3rd subassembly group in the number of subassembly one, the second subassembly group in the described first subassembly group, be respectively according to the design of the disposal ability of each subassembly, the number of described subassembly two is less than the number of described subassembly one and subassembly three respectively;
The described first subassembly group is used to receive code word, and described code word is carried out residue calculating and syndrome calculating, and the result of calculation that described residue is calculated and syndrome calculates is outputed to the second subassembly group;
The described second subassembly group is used to receive the described result of calculation that the first subassembly group is exported, and described result of calculation is carried out iterative computation, and described iterative computation result is outputed to the 3rd subassembly group;
Described the 3rd subassembly group is used to receive described iterative computation result, obtains errors present and improper value, and described errors present and improper value are outputed to described error correction unit.
2, circuit according to claim 1 is characterized in that, described decoding combinatorial logic unit further comprises: caching control unit;
Described caching control unit is used to receive the result of calculation that the described first subassembly group is exported, and described result of calculation is exported to the described second subassembly group; Be used to receive the described iterative computation result of second subassembly group output, described iterative computation result is outputed to the 3rd subassembly group.
3, circuit according to claim 1 is characterized in that, described subassembly one comprises: syndrome computing unit S; Described subassembly two comprises: iteration unit I; Described subassembly three comprises: ask errors present and improper value unit C.
4, according to claim 2 or 3 described circuit, it is characterized in that described caching control unit comprises: S/I buffer unit and control unit;
Described S/I buffer unit is used to receive the result of calculation of described first subassembly group transmission and the control signal that control unit sends, and under the effect of control signal, described result of calculation is exported to the described second subassembly group; Be used to receive the iterative computation result that the second subassembly group sends, under the effect of control signal, described iterative computation result outputed to described the 3rd subassembly group;
Described control unit is used for generating control signal according to the disposal ability of described each subassembly, and described control signal is exported to described S/I buffer unit.
According to the described circuit of claim 1 to 3, it is characterized in that 5, described decoding combinatorial logic unit further comprises: the 3rd subassembly group buffer unit;
Described the 3rd subassembly group buffer unit is used to receive and preserve the errors present and the improper value of the output of the 3rd subassembly group, and described errors present and improper value are outputed to error correction unit.
According to the described circuit of claim 1 to 3, it is characterized in that 6, the number of described subassembly one equals the number of described subassembly three.
According to the described circuit of claim 1 to 3, it is characterized in that 7, the number of described subassembly one equals to be input to the number of code word of decoding circuit divided by the value of the disposal ability gained merchant's of described subassembly one carry integer;
The number of described subassembly three equals to be input to the number of code word of decoding circuit divided by the value of the disposal ability gained merchant's of described subassembly three carry integer.
According to the described circuit of claim 1 to 3, it is characterized in that 8, the number of described subassembly two equals to be input to the number of code word of decoding circuit divided by the value of the disposal ability gained merchant's of described subassembly two carry integer.
9, a kind of method of decoding of realizing is characterized in that, is provided with in decoding circuit in advance: comprise subassembly one the first subassembly group, comprise the second subassembly group of subassembly two and comprise the 3rd subassembly group of subassembly three; The number of described subassembly two is less than the number of described subassembly one and subassembly three respectively;
The code word of described first subassembly group of received input is carried out residue calculating and syndrome calculating to described code word;
The described second subassembly group is carried out iterative computation according to the result of calculation that residue is calculated and syndrome calculates to described code word;
Described the 3rd subassembly group is obtained the errors present and the improper value of described code word according to described iterative computation result;
According to errors present and improper value, described code word is carried out correction process.
10, method according to claim 9 is characterized in that, described code word is carried out residue is calculated and syndrome calculating after, described code word is carried out before the iterative computation, this method further comprises:
The result of calculation that described residue is calculated and syndrome calculates is carried out caching process.
According to claim 9 or 10 described methods, it is characterized in that 11, described code word is carried out obtaining before the errors present and improper value of described code word after the iterative computation, and this method further comprises:
Described iterative computation result is carried out caching process.
12, method according to claim 9 is characterized in that, described all code words that are input to decoding circuit are:
The code word of the Bo Si-Cha Dehuli that interweaves-Huo Kun lattice nurse Bose-Chaudhuri-Hocquenghem Code.
13, method according to claim 9 is characterized in that, described subassembly one comprises: syndrome computing unit S; Described subassembly two comprises: iteration unit I; Described subassembly three comprises: ask errors present and improper value unit C.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568604A (en) * | 2011-12-07 | 2012-07-11 | 记忆科技(深圳)有限公司 | BCH (Broadcast Channel) encoder and decoder |
| CN101692612B (en) * | 2009-05-27 | 2012-10-17 | 华为技术有限公司 | Multi-specification Reed-Solomon encoding and decoding method, device and system |
| CN105007286A (en) * | 2014-04-23 | 2015-10-28 | 苏宁云商集团股份有限公司 | Decoding method, decoding device, and cloud storage method and system |
| CN107040333A (en) * | 2016-02-03 | 2017-08-11 | 富士施乐株式会社 | Decoding apparatus, the information transmission system and coding/decoding method |
| CN107800439A (en) * | 2016-08-30 | 2018-03-13 | 马维尔国际贸易有限公司 | Low latency decoder for reed solomon code |
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2007
- 2007-02-07 CN CNB2007100004642A patent/CN100546206C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101692612B (en) * | 2009-05-27 | 2012-10-17 | 华为技术有限公司 | Multi-specification Reed-Solomon encoding and decoding method, device and system |
| CN102568604A (en) * | 2011-12-07 | 2012-07-11 | 记忆科技(深圳)有限公司 | BCH (Broadcast Channel) encoder and decoder |
| CN105007286A (en) * | 2014-04-23 | 2015-10-28 | 苏宁云商集团股份有限公司 | Decoding method, decoding device, and cloud storage method and system |
| CN105007286B (en) * | 2014-04-23 | 2018-12-28 | 苏宁易购集团股份有限公司 | Coding/decoding method and device and cloud storage method and system |
| CN107040333A (en) * | 2016-02-03 | 2017-08-11 | 富士施乐株式会社 | Decoding apparatus, the information transmission system and coding/decoding method |
| CN107040333B (en) * | 2016-02-03 | 2021-04-13 | 富士施乐株式会社 | Decoding device, information transmission system, and decoding method |
| CN107800439A (en) * | 2016-08-30 | 2018-03-13 | 马维尔国际贸易有限公司 | Low latency decoder for reed solomon code |
| CN107800439B (en) * | 2016-08-30 | 2023-01-13 | 马维尔亚洲私人有限公司 | Low delay decoder for Reed Solomon codes |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100546206C (en) | 2009-09-30 |
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