CN1862967A - Thin-oxide devices for high voltage i/o drivers - Google Patents
Thin-oxide devices for high voltage i/o drivers Download PDFInfo
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- CN1862967A CN1862967A CN 200610057345 CN200610057345A CN1862967A CN 1862967 A CN1862967 A CN 1862967A CN 200610057345 CN200610057345 CN 200610057345 CN 200610057345 A CN200610057345 A CN 200610057345A CN 1862967 A CN1862967 A CN 1862967A
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Abstract
An I/O driver includes a pull-down module and pull-up module. The pull-down module has one or more NMOS transistors serially coupled between ground and an output node. The pull-up module has one or more PMOS transistors serially coupled between a first voltage and the output node. The gates of the PMOS and NMOS transistors are controlled by a set of differential biases for selectively pulling the output node to the first voltage or ground. The differential biases are separately set for each of the transistors so that a voltage difference across each of the transistors does not exceed a predetermined value, thereby preventing the same from damage.
Description
Technical field
The invention relates to integrated circuit (IC) design, and be particularly to not have thick oxide layer element high pressure I/O (I/O) driver (I/Odriver) of (thick-oxide device).
Background technology
Semiconductor technology is just developing into how much (geometries) technology of profound micron that are less than 100 nanometers, integrates more sophisticated functionss more expeditiously in a single-chip.Though it is inferior 100 nano-components provide more sophisticated functionss and higher usefulness, also expensive.
Observe to find that when a transistorized raceway groove (channel) when length is enough little, because leakage current (leakage), even at (standby) state of awaiting orders, electric current is existence still.So supply voltage must descend to minimize this leakage current on relative scale ground.Yet the I/O voltage of conventional I/O driver still maintains the high-voltage level as 3.3V or 2.5V, to be compatible to the system that exists at present.In the prior art, the thick oxide layer element is normally used for I/O driver and thin oxide layer element and is used in other circuit that operate in (down-scaled) supply voltage on a small scale.Use the conventional I/O driver of thick oxide layer element in (fabrication) process of manufacturing, to need to add extra light shield (masks), make manufacture process become expensive and consuming time.For instance, generally in order in manufacture of semiconductor, to comprise the thick oxide layer element, must increase by four or five extra light shields to make these elements.Though attempted solving this problem, so all too complexity and restriction are too much on practice for the means of these trials.
Summary of the invention
In view of this, one of purpose of the present invention promptly provides a kind of integrated circuit (IC) design, and eliminating needs to use thick oxide layer circuit elements design technology in high pressure I/O driver.
The invention provides a kind of I/O driver, comprise a step-down (pull-down) and (pull-up) module that boosts.Pull-down module has one or more nmos pass transistor that in series couples between between an earth terminal and an output node.The module that boosts has one or more PMOS transistor that in series couples between between one first voltage and this output node.Control the grid (gate) of this PMOS and nmos pass transistor by one group differential bias voltage (differential bias), in order to optionally the voltage of this output node is pulled to first voltage or ground connection.For each transistor, set its differential bias voltage respectively, make can not surpass one set (predetermined) value across the pressure reduction between each transistor, avoid transistor to damage whereby.
Input/output driver of the present invention, using the P-type mos number of transistors on this boosts module is to depend on this first voltage.
Input/output driver of the present invention, this differential bias voltage comprises at least onely having the fixed-bias transistor circuit of this core voltage or comprise according to a voltage level of expecting on this output node, switches (switching) (swing) bias voltage that swings between a high-voltage value and a low voltage value.
Input/output driver of the present invention, when the voltage level of expecting on this output node switched to ground connection by this first voltage, this bias voltage that swings was switched to this high-voltage value or is switched to this low voltage value by this high-voltage value by this low voltage value.
The present invention also provides a kind of input/output circuitry, in order to input signal corresponding to one second voltage, export the output signal of one first voltage, this second voltage is lower than this first voltage, comprise: a pull-down module, its have at least one between between an earth terminal and an output node N type metal oxide semiconductor transistor of coupled in series; One module that boosts, its have at least one between between an I/O voltage and this output node the P-type mos transistor of coupled in series; One shift unit, it is in response to this input signal, optionally start (enabling) or forbid (disabling) this pull-down module and this module that boosts in order to produce one group of differential bias voltage, the voltage of this output node is pulled to this I/O voltage or ground connection, wherein for each this P-type mos transistor, this differential bias voltage is to set respectively, makes can not surpass a set value across the pressure reduction between each this P-type mos transistor, avoids whereby damaging.
Input/output circuitry of the present invention, the P-type mos number of transistors of using in this module that boosts are to depend on this I/O voltage.
Input/output circuitry of the present invention, this differential bias voltage comprises that at least one its voltage level is lower than the fixed-bias transistor circuit of this I/O voltage or comprises according to a voltage level of expecting on this output node, switches on the bias voltage that swings of one between a high-voltage value and a low voltage value.
Input/output circuitry of the present invention, when the voltage level of expecting on this output node switched to ground connection by this I/O voltage, this bias voltage that swings was switched to this high-voltage value or is switched to this low voltage value by this high-voltage value by this low voltage value.
Input/output circuitry of the present invention, this shift unit more comprises: one first P-type mos transistor is coupled to this I/O voltage; One first group (group), it has pressure drop (voltagedropping) the P-type mos transistor that at least one its grid is connected to its drain electrode (drain), and coupled in series is to this first P-type mos transistor drain; One the one N type metal oxide semiconductor transistor, it has a grid of being controlled by this input signal, and coupled in series is between transistorized this first group of this pressure drop P-type mos and ground connection; One second P-type mos transistor, it parallels with this first P-type mos transistor, be coupled to this I/O voltage, wherein the transistorized grid of this second P-type mos is coupled to this first P-type mos transistor drain, and the transistorized grid of this first P-type mos is coupled to this second P-type mos transistor drain; One second group, it has the pressure drop P-type mos transistor that at least one its grid is connected to its drain electrode, and coupled in series is to this second P-type mos transistor drain; And one the 2nd N type metal oxide semiconductor transistor, it has a grid of being controlled by this complementation (complement) input signal, coupled in series between transistorized this second group of this pressure drop P-type mos and ground connection, wherein this first and second P-type mos transistor drain and this pressure drop P-type mos transistorized this first and this second group this differential bias voltage is provided.
Input/output circuitry of the present invention, this shift unit more comprises: one the 3rd P-type mos transistor, its grid is coupled to its drain electrode; And one the 4th P-type mos transistor, its grid is coupled to its drain electrode, be coupled to the 3rd P-type mos transistor drain again, wherein the 3rd and the 4th P-type mos transistor receive from this pressure drop P-type mos transistorized this first with the complementary pair (pair) of the differential bias voltage of the drain electrode of this second group, and export a fixed-bias transistor circuit.
Input/output circuitry of the present invention, this shift unit more comprises: one first P-type mos transistor is coupled to this I/O voltage; One first group, it has at least one capacitor, and coupled in series is to the transistorized drain electrode of this first P-type mos, in order to receive this input signal; One second P-type mos transistor, it parallels with this first P-type mos transistor, be coupled to this I/O voltage, wherein the transistorized grid of this second P-type mos is coupled to this first P-type mos transistor drain, and the transistorized grid of this first P-type mos is coupled to this second P-type mos transistor drain; And one second group, it has at least one capacitor, coupled in series is to the transistorized drain electrode of this second P-type mos, and in order to receive a complementary signal of this input signal, wherein this first and second P-type mos transistor drain provides this differential bias voltage.
Input/output circuitry of the present invention, this shift unit more comprises: one first diode, it parallels with this first P-type mos transistor, is coupled to this I/O voltage; And one the 3rd P-type mos transistor, its grid is connected to its drain electrode, in series couples (serially coupled) to this first diode, is coupled to this first P-type mos transistor drain again.
The present invention provides a kind of input/output driver again, comprising: a pull-down module, its have at least one between between an earth terminal and an output node N type metal oxide semiconductor transistor of coupled in series; One first P-type mos transistor is coupled to an I/O supply voltage; One second P-type mos transistor, coupled in series is to this first P-type mos transistor; And one the 3rd P-type mos transistor, coupled in series is between this this output node of second P-type mos transistor AND gate, wherein this first, second and the transistorized grid of the 3rd P-type mos controlled by first, second and the 3rd bias voltage respectively, make each across this first, second and the transistorized pressure reduction of the 3rd P-type mos can not surpass a set value, avoid whereby this first, second and the 3rd P-type mos transistor damage.
Input/output driver of the present invention, when this output node is exported this I/O voltage, this first bias voltage approximates and adds this first P-type mos transistorized one critical (threshold) voltage of three times across the transistorized pressure drop of this first P-type mos, this second bias voltage approximates this I/O voltage and cuts across the transistorized pressure drop of this first P-type mos, cut transistorized critical voltage of this second P-type mos and the 3rd bias voltage again and approximate this I/O voltage and cut, cut the transistorized critical voltage of the 3rd P-type mos again across the transistorized pressure drop of this first P-type mos.
Input/output driver of the present invention, when this output node output 0V, this first bias voltage approximates this I/O voltage, this second bias voltage approximates this I/O voltage and cuts across the transistorized pressure drop of this first P-type mos, cuts the transistorized critical voltage of the 3rd P-type mos that transistorized critical voltage of this second P-type mos and the 3rd bias voltage approximate twice again.
I/O of the present invention (I/O) driver and circuit, the grid bias voltage of each thin oxide layer element allow it to operate under higher voltage and do not suffer the destruction of high pressure.This makes and can only come to make high pressure I/O driver in fact with the thin oxide layer element, so removed the required extra light shield of thick oxide layer element, also therefore provides cost savings and manufacturing time.
Description of drawings
Figure 1A to Fig. 1 C is 3 I/O driver architectures with thin oxide layer element that show according to the embodiment of the invention;
Fig. 2 A to Fig. 2 B is 2 shift unit frameworks that show according to the embodiment of the invention;
Fig. 3 is that a circuit diagram is the circuit of the I/O driver that shows that one group of differential bias voltage being produced by a shift unit according to having of the embodiment of the invention is controlled.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and cooperate appended diagram, it is as follows to be elaborated.
Figure 1A is that a schematic diagram is to show the I/O driver 100 that has the thin oxide layer element according to one of the embodiment of the invention.100 of shown I/O drivers are done in fact with the thin oxide layer element.In this example, thin oxide layer PMOS transistor 102 and 104 is in series put between one together with thin oxide layer nmos pass transistor 106 and 108 to have the I/O power supply supply of I/O voltage (VDDI) and the stacked structure between the ground connection.This transistor 106 and 108 is taken as a pull-down module jointly to move the voltage on the output node 110 to electronegative potential.Transistor 102 and 104 is taken as one jointly and boosts module so that the voltage on the output node 110 is risen to high potential.Its I/O voltage (VD DI) is to be higher than one to be used for the core voltage VDD C that core (core) circuit (not shown) operates.Suitable differential bias voltage is imposed on above-mentioned transistorized grid to keep higher I/O voltage.Above-mentioned differential bias voltage can be the fixed-bias transistor circuit as this core voltage, or switches on the swing of one between one first voltage and one second voltage bias voltage (swing bias), need look the needs of I/O design of Driver.Have the polarity chron identical with this I/O driver output signal if this swing bias voltage switches, when output signal became 1 by 0, this swing bias voltage switched to high-voltage value by low voltage value.Have the polarity chron opposite with this I/O driver output signal if this swing bias voltage switches, when output signal became 1 by 0, this swing bias voltage switched to low voltage value by high-voltage value.By suitably utilizing various differential bias voltages to control above-mentioned transistor, can guarantee can not surpass a set value across transistor 102 and 104 s' pressure reduction, this set value is to be used for keeping the normal of transistor operation, can not burn out because of excessive voltage.Can avoid transistor 102 and 104 to produce a High Pressure Difference thereon and destroyed like this because of this high I/O voltage VDDI strides.
For instance, be 1.0V and I/O voltage when being 1.8V if be designed to core voltage, transistor 104 and 106 is by clamped core voltage VDDC to 1.0V.When needs output logic 0, the grid of transistor 102 then is biased to 1.8V.The critical voltage of supposing transistor 102 is 0.4V, and when needs output logic 1, the grid of transistor 102 will be biased to the voltage that is lower than 1.4V, for example a 1.3V.Utilization applies suitable bias voltage on the grid of transistor 102, have only the sub-fraction of I/O voltage 1.8V can arrive on the source electrode of transistor 104.By the control of bias voltage, can be controlled under the set value across the pressure reduction of transistor 102, so can avoid transistor to be destroyed.In like manner, can be controlled under the set value across the pressure reduction of transistor 104, so can avoid transistor to be destroyed.
Because transistor 102 and transistor 104 quilts are bias voltage suitably, the high I/O voltage VDDI of 1.8V can be produced by output node 110.
Figure 1B shows the I/O driver 112 that has the thin oxide layer element according to one of the embodiment of the invention.In this example, thin oxide layer PMOS transistor 114,116 and 118 is in series put between one together with thin oxide layer nmos pass transistor 120,122 and 124 to have the I/O power supply supply of I/O voltage (VDDI) and the stacked structure between the ground connection.Transistor 120,122 and 124 is taken as a pull-down module jointly to move the voltage on the output node 126 to electronegative potential.Transistor 114,116 and 118 is taken as one jointly and boosts module to move the voltage on the output node 126 to high potential.Because I/O driver 112 has more transistor series together than I/O driver 110, its I/O voltage also may be higher.In other words, when the I/O value increased, the PMOS number of transistors was also along with increase in the module that boosts.For instance, if I/O driver 110 can be controlled the high voltage of a 1.8V, 112 of I/O drivers can be controlled higher voltage as 2.5V.Utilization applies suitable differential bias voltage to keep higher I/O voltage at above-mentioned transistorized grid.These grid voltages can be that a fixed-bias transistor circuit such as core voltage VDDC, a swing bias voltage switch and have the polarity identical with the output signal of this output node, or one the swing bias voltage switch and to have the polarity opposite with the output signal of this output node, decide on the needs of I/O design of Driver.The selectivity of above-mentioned three kinds of bias voltages is used can be in order to clamped thin oxide layer transistor between the operating space of a safety.
Transistor 114,116,118 and 124 is set up as switch.The function of I/O driver 112 is similar to I/O driver 100, accepts input and a more high-tension output is provided because all be.As embodiment,, impose on bias voltage on transistor 114 grids this moment and be provided in a side of approximately that (proximately) equals Vd+3|V when these I/O voltages of output node 126 output
Tp|, wherein Vd be across the pressure drop of transistor 114 and | V
Tp| be its critical voltage value.Be provided in a side of and approximate VDDI-Vd-|V and be applied to bias voltage on transistor 116 and 118 grids
Tp|.When output node 126 output 0V, be applied to bias voltage on transistor 114 grids and be provided in a side of and approximate VDDI, be provided in a side of and approximate VDDI-Vd-|V and be applied to bias voltage on transistor 116 grids
Tp|, and be applied to bias voltage on transistor 118 grids and be provided in a side of and approximate 2|V
Tp|.
For instance, if be designed to core voltage VDDC be 1.0V, I/O voltage be 2.5V, across the pressure drop of transistor 114 be 0.7V, with and critical voltage when being 0.4V, can come the element in the bias voltage I/O driver 112 by one group differential bias voltage.When needs output logic 0, the grid bias of transistor 114 is to 2.5V; When needs output logic 1, the grid of transistor 114 then is biased into 1.9V.When being output as logical zero,, therefore can avoid transistor 114 to be destroyed because the bias voltage on the transistor 114 and stride thereon pressure drop has only 1.8V will arrive at the source electrode of transistor 116.And no matter being output as logical zero or 1, transistor 116 all is biased in 1.4V.After another pressure drop, have only 1.2V can arrive at the source electrode of transistor 118, therefore can avoid transistor 116 to be destroyed.When needs output logic 0, the grid of transistor 118 can be biased into 0.8V; When needs output logic 1, the grid of transistor 118 then can be biased into 1.4V.Utilization applies suitable bias voltage on transistor 114,116 and 118, the pressure reduction on these PMOS transistors can be controlled in the safe range.For fear of the destruction of high pressure, the transistor in I/O driver 112 pull-down module is also by the value of foundation output signal institute bias voltage suitably.
Fig. 1 C shows the I/O driver 128 that has the thin oxide layer element according to one of the embodiment of the invention.Thin oxide layer PMOS transistor 130,132 and 134 is placed in one and boosts in the module, and a nmos pass transistor 136 series connection one nmos pass transistor 138 is placed in the pull-down module.Above-mentioned setting can allow the drain electrode of transistor 136 can keep a high voltage, makes that its source electrode can be by clamped to a low voltage.The back grid of transistor 136 (backgate) bias voltage can be set as very low, so that this element need be in other P trap (P-well).Utilize this high voltage device design, can allow must not use under the condition of extra nmos pass transistor in pull-down module, in the module that boosts, use the PMOS transistor, shown in Figure 1B.
Shown in Figure 1A to Fig. 1 C, the PMOS transistor that is used in the I/O driver is controlled by differential bias voltage, so that can not surpass a set value across each transistorized pressure reduction.This allows the above-mentioned transistor can be by the thin oxide layer manufacturing under the destruction that does not have high I/O voltage.
Fig. 2 A shows a shift unit (level shifter) 200, in order to produce the differential bias voltage according to the embodiment of the invention.Shift unit 200 can produce this differential bias voltage, in order to the transistor in suitable clamped I/O driver 100,112 and 128, shown in Figure 1A to Fig. 1 C.A PMOS transistor 202 is coupled to an I/O voltage source of supply with I/O voltage VDDI.One or more pressure drop PMOS transistor 206,210 and 214 is the drain electrodes that in series are coupled to transistor 202, and wherein the transistorized grid of each pressure drop PMOS is to be connected to its drain electrode.A nmos pass transistor, it has the grid of being controlled by an input signal D, is in series to be coupled between this transistor 214 and the ground connection.A PMOS transistor 204 is to be coupled to this I/O power supply and to be parallel to this transistor 202.The grid of transistor 204 is the drain electrodes that are coupled to transistor 202, and the grid of transistor 202 is the drain electrodes that are coupled to transistor 204.One or more pressure drop PMOS transistor 208,212 and 216 is the drain electrodes that in series are coupled to transistor 204, and wherein the transistorized grid of each pressure drop PMOS is to be connected to its drain electrode.A nmos pass transistor, it has the grid of being controlled by a complementary input signal DB, is in series to be coupled between transistor 216 and the ground connection.
Transistor 202 and 204 forms a mutual coupling (cross-coupled) frameworks, makes can fasten (latch) data during in switching as input signal D and DB.It should be noted that this complementary input signal DB is the anti-phase of input signal D.PMOS transistor 206,210 and 214 is to be configured to a diode arrangement (diode configuration), and PMOS transistor 208,212 and 216 is to be configured to another diode arrangement so that multiple pressure drop to be provided.It should be noted that on node 218 and 220 two charge members (leakers) can help to avoid voltage to drop to ground connection when transistor 202 or 204 is blocked.
Three kinds of different bias voltages can be from the shift unit 200 obtain.Node 220 can provide the bias voltage that has identical polar such as input signal D in order to clamped as 222 and 224; And node 218 can provide the bias voltage that has opposite polarity such as input signal DB in order to clamped as 226 and 228.A pair of PMOS transistor, wherein its grid is coupled to the output of its drain electrode and receiving node 222 and 226, and a fixed-bias transistor circuit R is provided.All the other nodes then provide the swing bias voltage according to input signal D thus to the switching of complementary input signal DB.
It should be noted that PMOS transistor 206,208,210,212,214 and 216 can be NMOS diode, PMOS diode, nmos pass transistor, P-N junction diode or its combination.If a nmos pass transistor is to connect as same diode, its grid is to be connected to its drain electrode.Similarly, if a PMOS transistor is to connect as same diode, its grid is to be connected to its drain electrode.
Fig. 2 B shows a shift unit 230, in order to produce the differential bias voltage according to the embodiment of the invention.PMOS transistor 244 is to be coupled to the I/O power supply with an I/O voltage VDDI.One or more capacitor 232,236 and 240 is the drain electrodes that in series are coupled to transistor 244, in order to receive an input signal D.A PMOS transistor 246 is to be coupled to this I/O power supply and to be parallel to PMOS transistor 244.The grid of transistor 246 is the drain electrodes that are coupled to transistor 244, and the grid of transistor 244 is the drain electrodes that are coupled to transistor 246.One or more capacitor 234,238 and 242 is the drain electrodes that in series are coupled to transistor 246, in order to the complementary signal of receiving inputted signal D.
A diode 252 is to be coupled to this I/O power supply and to be parallel to PMOS transistor 244.PMOS transistor 248 is in series to be coupled to diode 252, and its grid be connected to its drain electrode, be coupled to the drain electrode of transistor 244 again.Second diode 254 is to be coupled to this I/O power supply and to be parallel to PMOS transistor 246.PMOS transistor 250 is in series to be coupled to diode 254, and its grid be connected to its drain electrode, be coupled to the drain electrode of transistor 246 again.
It should be noted that above-mentioned shift unit 230 can produce this differential bias voltage, in order to suitably clamped as the transistor in the I/O driver among Figure 1A, Figure 1B and Fig. 1 C.To be a bootstrap (bootstrap) shift units be made up of six bootstrap nmos pass transistors 232,234,236,238,240 and 242 shift unit 230, and it can be regarded as capacity cell, provides any capacitance to determine its bias voltage.Nmos pass transistor 232,236 and 240 is at a stacked structure, and can be regarded as a bootstrap module, and nmos pass transistor 234,238 and 242 is also at a stacked structure, and can be regarded as another bootstrap module.Be coupled to high or low current potential according to node 256, input signal D also from low to high or highly switch to low.Transistor 244 and 246 be combined to form a mutual coupling structure to fasten a signal.Transistor 252 or 254 works together with transistor 248 or 250 1, so that the leakage path when node 256 or 258 suspension joints to be provided.Therefore, node 258 or 256 is exported a bias voltage and is controlled its I/O driver according to input signal D.
Shift unit 230 has several advantages.Shift unit 230 when allowing its bias voltage at random to produce according to capacity ratio, can be carried out quickly, and fixing critical voltage is easier than relying on.And it is when producing bias voltage, temperature independent.In addition, shift unit 230 is put less oxidative pressure (oxide stress) on element and have a less leakage current.The also shared same bodies of all MOS transistor (bulks) represent that it takies less zone.
It should be noted that as the MOS element among Fig. 2 B can be zero-Vt element, vague and general shape (depletion) element, N+ on the N-bulk mos capacitance device or P+ on P-bulk mos capacitance device.
Fig. 3 is a circuit 300 that shows according to the embodiment of the invention, and it has the I/O driver 302 by 304 bias voltages of shift unit.This I/O driver 302 is equivalent to the I/O driver 100 among Figure 1A, its thin oxide layer element one of them by 304 bias voltages of shift unit.Shift unit 304, except a few NMOS capacitor, its function mode is as the shift unit among Fig. 2 B 230.
Thin oxide layer PMOS transistor 306 and 308 is located at one and is boosted and be located in the pull-down module together with thin oxide layer nmos pass transistor 310 and 312 in the module.When transistor 312 can be driven by an inverter 314, transistor 308 and 310 grid were all clamped to core voltage VDDC, so allow it to swing between core voltage VDDC at 0V.The grid of transistor 306 is by the institute of the voltage on the node in the shift unit 304 316 bias voltage, so allow its change value according to input signal D to switch at a high voltage and a low-voltage intercropping.
Shift unit 304 runnings are similar to the bootstrap shift unit 230 among Fig. 2 B.In shift unit 304, capacitor 318,320,322 and 324 via comprise diode 326 and 328 and PMOS transistor 330 and 332 charge members initially charge to VDDI-VDDC.If output signal D is made as electronegative potential, a PMOS transistor 334 is closed, and PMOS transistor 336 is conductings at this moment, so high voltage VDDI arrives at node 316, therefore closes transistor 306.Simultaneously, this input signal D also drives the transistor 312 in inverter 314 and the conducting I/O driver 302.Transistor 306 and turn-on transistor 312 are closed in utilization, make that the output voltage on node 338 is 0V.When this output signal D switched from low to high, a node 340 was to boost to high potential and equal VDDI.Node 316 will be coupled to electronegative potential, and it equals VDDC.Then, the voltage on the node 316 will enough remove turn-on transistor 306, make that the node 338 in the I/O driver 302 can be promoted to high potential.
According to embodiments of the invention, multiple thin oxide layer element can be set as a tandem junction structure, and wherein each element is controlled by the suitable bias voltage that shift unit provides.The grid bias voltage of each thin oxide layer element allows it to operate under higher voltage and does not suffer the destruction of high pressure.This makes and can only come to make high pressure I/O driver in fact with the thin oxide layer element, so removed the required extra light shield of thick oxide layer element, also therefore provides cost savings and manufacturing time.
Above-mentioned exposure provides many different embodiment and example, in order to implement the various different characteristics of this exposure.Element in the specific examples and process are to be described to help to differentiate this exposure, and the present invention is not limited to this certainly.
Though the present invention by the preferred embodiment explanation as above, this preferred embodiment is not in order to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, should have the ability this preferred embodiment is made various changes and replenished, so protection scope of the present invention is as the criterion with the scope of claims.
Being simply described as follows of symbol in the accompanying drawing:
The 100:I/O driver
102,104: thin oxide layer PMOS transistor
106,108: the thin oxide layer nmos pass transistor
VDDI:I/O voltage
VDDC: core voltage
110: output node
The 112:I/O driver
114,116,118: thin oxide layer PMOS transistor
120,122,124: the thin oxide layer nmos pass transistor
126: output node
The 128:I/O driver
130,132,134: thin oxide layer PMOS transistor
136,138:NMOS transistor
200: shift unit
202,204:PMOS transistor
206,208,210,212,214,216: pressure drop PMOS transistor
D: input signal
DB: complementary input signal
218,220,222,224,226,228: node
R: fixed-bias transistor circuit
230: shift unit
232,234,236,238,240,242: capacitor
The 244:PMOS transistor
246,248,250:PMOS transistor
252,254: diode
256,258: node
300: circuit diagram
The 302:I/O driver
304: shift unit
306,308: thin oxide layer PMOS transistor
310,312: the thin oxide layer nmos pass transistor
314: inverter
316: node
318,320,322,324: capacitor
326,328: diode
330,332,334,336:PMOS transistor
338,340: node.
Claims (15)
1. input/output driver, one first voltage that it operates in the core voltage that is higher than core circuit comprises:
One pull-down module, its have at least one between between an earth terminal and an output node N type metal oxide semiconductor transistor of coupled in series; And
One module that boosts, its have at least one between between this first voltage and this output node the P-type mos transistor of coupled in series, control grid in this P-type mos and the N type metal oxide semiconductor transistor by at least one group of differential bias voltage, in order to optionally the voltage of this output node is pulled to this first voltage or ground connection
Wherein for each this P-type mos transistor, this differential bias voltage is to set respectively, makes can not surpass a set value across the pressure reduction between each this P-type mos transistor, avoids whereby damaging.
2. input/output driver according to claim 1 is characterized in that, using the P-type mos number of transistors on this boosts module is to depend on this first voltage.
3. input/output driver according to claim 1, it is characterized in that, this differential bias voltage comprises at least onely having the fixed-bias transistor circuit of this core voltage or comprise according to a voltage level of expecting on this output node, switches on the bias voltage that swings of one between a high-voltage value and a low voltage value.
4. input/output driver according to claim 3, it is characterized in that, when the voltage level of expecting on this output node switched to ground connection by this first voltage, this bias voltage that swings was switched to this high-voltage value or is switched to this low voltage value by this high-voltage value by this low voltage value.
5. an input/output circuitry in order to the input signal corresponding to one second voltage, is exported the output signal of one first voltage, and this second voltage is lower than this first voltage, comprising:
One pull-down module, its have at least one between between an earth terminal and an output node N type metal oxide semiconductor transistor of coupled in series;
One module that boosts, its have at least one between between an input/output voltage and this output node the P-type mos transistor of coupled in series;
One shift unit, it is in response to this input signal, optionally starts or forbids this pull-down module and this module that boosts in order to produce one group of differential bias voltage, and the voltage of this output node is pulled to this input/output voltage or ground connection,
Wherein for each this P-type mos transistor, this differential bias voltage is to set respectively, makes can not surpass a set value across the pressure reduction between each this P-type mos transistor, avoids whereby damaging.
6. input/output circuitry according to claim 5 is characterized in that, the P-type mos number of transistors of using in this module that boosts is to depend on this input/output voltage.
7. input/output circuitry according to claim 5, it is characterized in that, this differential bias voltage comprises that at least one its voltage level is lower than the fixed-bias transistor circuit of this input/output voltage or comprises according to a voltage level of expecting on this output node, switches on the bias voltage that swings of one between a high-voltage value and a low voltage value.
8. input/output circuitry according to claim 7, it is characterized in that, when the voltage level of expecting on this output node switched to ground connection by this input/output voltage, this bias voltage that swings was switched to this high-voltage value or is switched to this low voltage value by this high-voltage value by this low voltage value.
9. input/output circuitry according to claim 5 is characterized in that, this shift unit more comprises:
One first P-type mos transistor is coupled to this input/output voltage;
One first group, it has the pressure drop P-type mos transistor that at least one its grid is connected to its drain electrode, and coupled in series is to this first P-type mos transistor drain;
One the one N type metal oxide semiconductor transistor, it has a grid of being controlled by this input signal, and coupled in series is between transistorized this first group of this pressure drop P-type mos and ground connection;
One second P-type mos transistor, it parallels with this first P-type mos transistor, be coupled to this input/output voltage, wherein the transistorized grid of this second P-type mos is coupled to this first P-type mos transistor drain, and the transistorized grid of this first P-type mos is coupled to this second P-type mos transistor drain;
One second group, it has the pressure drop P-type mos transistor that at least one its grid is connected to its drain electrode, and coupled in series is to this second P-type mos transistor drain; And
One the 2nd N type metal oxide semiconductor transistor, it has a grid of being controlled by this complementary input signal, coupled in series between transistorized this second group of this pressure drop P-type mos and ground connection,
Wherein this first and second P-type mos transistor drain and this pressure drop P-type mos transistorized this first and this second group this differential bias voltage is provided.
10. input/output circuitry according to claim 9 is characterized in that, this shift unit more comprises:
One the 3rd P-type mos transistor, its grid is coupled to its drain electrode; And
One the 4th P-type mos transistor, its grid is coupled to its drain electrode, is coupled to the 3rd P-type mos transistor drain again,
Wherein the 3rd and the 4th P-type mos transistor receive from this pressure drop P-type mos transistorized this first with a complementary pair of the differential bias voltage of the drain electrode of this second group, and export a fixed-bias transistor circuit.
11. input/output circuitry according to claim 7 is characterized in that, this shift unit more comprises:
One first P-type mos transistor is coupled to this input/output voltage:
One first group, it has at least one capacitor, and coupled in series is to the transistorized drain electrode of this first P-type mos, in order to receive this input signal;
One second P-type mos transistor, it parallels with this first P-type mos transistor, be coupled to this input/output voltage, wherein the transistorized grid of this second P-type mos is coupled to this first P-type mos transistor drain, and the transistorized grid of this first P-type mos is coupled to this second P-type mos transistor drain; And
One second group, it has at least one capacitor, and coupled in series is to the transistorized drain electrode of this second P-type mos, in order to receiving a complementary signal of this input signal,
Wherein this first and second P-type mos transistor drain provides this differential bias voltage.
12. input/output circuitry according to claim 11 is characterized in that, this shift unit more comprises:
One first diode, it parallels with this first P-type mos transistor, is coupled to this input/output voltage; And
One the 3rd P-type mos transistor, its grid is connected to its drain electrode, in series is coupled to this first diode, is coupled to this first P-type mos transistor drain again.
13. an input/output driver comprises:
One pull-down module, its have at least one between between an earth terminal and an output node N type metal oxide semiconductor transistor of coupled in series;
One first P-type mos transistor is coupled to an I/O supply voltage;
One second P-type mos transistor, coupled in series is to this first P-type mos transistor; And
One the 3rd P-type mos transistor, coupled in series between this this output node of second P-type mos transistor AND gate,
Wherein this first, second and the transistorized grid of the 3rd P-type mos controlled by first, second and the 3rd bias voltage respectively, make each across this first, second and the transistorized pressure reduction of the 3rd P-type mos can not surpass a set value, avoid whereby this first, second and the 3rd P-type mos transistor damage.
14. input/output driver according to claim 13, it is characterized in that, when this output node is exported this input/output voltage, this first bias voltage equals to add across the transistorized pressure drop of this first P-type mos three times the transistorized critical voltage of this first P-type mos, this second bias voltage equals this input/output voltage and cuts across the transistorized pressure drop of this first P-type mos, cut transistorized critical voltage of this second P-type mos and the 3rd bias voltage again and equal this input/output voltage and cut, cut the transistorized critical voltage of the 3rd P-type mos again across the transistorized pressure drop of this first P-type mos.
15. input/output driver according to claim 13, it is characterized in that, when this output node output 0V, this first bias voltage equals this input/output voltage, this second bias voltage equals this input/output voltage and cuts across the transistorized pressure drop of this first P-type mos, cuts the transistorized critical voltage of the 3rd P-type mos that transistorized critical voltage of this second P-type mos and the 3rd bias voltage equal twice again.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/127,452 US7046067B2 (en) | 2004-03-24 | 2005-05-12 | Thin-oxide devices for high voltage I/O drivers |
| US11/127,452 | 2005-05-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1862967A true CN1862967A (en) | 2006-11-15 |
| CN100547927C CN100547927C (en) | 2009-10-07 |
Family
ID=37390310
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100573456A Active CN100547927C (en) | 2005-05-12 | 2006-03-10 | Input/output circuitry |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN100547927C (en) |
| SG (1) | SG127783A1 (en) |
| TW (1) | TWI294176B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188418B (en) * | 2006-11-16 | 2011-07-27 | 奇美电子股份有限公司 | Logic circuit including single type of transistor and its corresponding application circuit |
| CN109698688A (en) * | 2017-10-20 | 2019-04-30 | 立积电子股份有限公司 | Phase inverter |
| CN110212896A (en) * | 2019-07-16 | 2019-09-06 | 天津飞腾信息技术有限公司 | A kind of high pressure resistant low-power consumption start-up circuit |
| CN113393814A (en) * | 2020-03-13 | 2021-09-14 | 联阳半导体股份有限公司 | Gate driving circuit for providing high driving voltage |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5916168B2 (en) * | 2011-06-29 | 2016-05-11 | シナプティクス インコーポレイテッド | High voltage drivers using medium voltage devices |
| TWI461959B (en) * | 2012-04-26 | 2014-11-21 | Issc Technologies Corp | Output and input interface apparatus |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0774616A (en) * | 1993-07-06 | 1995-03-17 | Seiko Epson Corp | Signal voltage level converting circuit and output buffer circuit |
| US6054888A (en) * | 1998-10-02 | 2000-04-25 | Advanced Micro Devices, Inc. | Level shifter with protective limit of voltage across terminals of devices within the level shifter |
| US6130557A (en) * | 1999-04-26 | 2000-10-10 | Ati Technologies, Inc. | Three level pre-buffer voltage level shifting circuit and method |
| US6801064B1 (en) * | 2002-08-27 | 2004-10-05 | Cypress Semiconductor, Corp | Buffer circuit using low voltage transistors and level shifters |
-
2005
- 2005-08-25 SG SG200505444A patent/SG127783A1/en unknown
-
2006
- 2006-02-03 TW TW95103763A patent/TWI294176B/en active
- 2006-03-10 CN CNB2006100573456A patent/CN100547927C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101188418B (en) * | 2006-11-16 | 2011-07-27 | 奇美电子股份有限公司 | Logic circuit including single type of transistor and its corresponding application circuit |
| CN109698688A (en) * | 2017-10-20 | 2019-04-30 | 立积电子股份有限公司 | Phase inverter |
| CN109698688B (en) * | 2017-10-20 | 2022-11-11 | 立积电子股份有限公司 | Inverter with a capacitor having a capacitor element |
| CN110212896A (en) * | 2019-07-16 | 2019-09-06 | 天津飞腾信息技术有限公司 | A kind of high pressure resistant low-power consumption start-up circuit |
| CN113393814A (en) * | 2020-03-13 | 2021-09-14 | 联阳半导体股份有限公司 | Gate driving circuit for providing high driving voltage |
| CN113393814B (en) * | 2020-03-13 | 2022-08-30 | 联阳半导体股份有限公司 | Gate driving circuit for providing high driving voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200639999A (en) | 2006-11-16 |
| CN100547927C (en) | 2009-10-07 |
| TWI294176B (en) | 2008-03-01 |
| SG127783A1 (en) | 2006-12-29 |
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