CN1851901A - Method for making organic light-emitting-diode panel - Google Patents
Method for making organic light-emitting-diode panel Download PDFInfo
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- CN1851901A CN1851901A CN 200610077494 CN200610077494A CN1851901A CN 1851901 A CN1851901 A CN 1851901A CN 200610077494 CN200610077494 CN 200610077494 CN 200610077494 A CN200610077494 A CN 200610077494A CN 1851901 A CN1851901 A CN 1851901A
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Abstract
This invention discloses a processing method for organic diode panels including providing a panel to form a black matrix layer on said panel and a buffer insulation layer on said black matrix and then patternizing said matrix layer and the buffer insulation layer to form a display electrode and a film transistor on said buffer insulation layer.
Description
Technical field
A kind of method of making organic LED panel refers to that especially a kind of manufacturing has the method for the organic electroluminescence display panel of black-matrix layer (Black Matrix).
Background technology
Function advanced person's display gradually becomes the valuable feature of consumption electronic product now, and the effect that these new displays are brought into play can be strengthened the impression of user for integral product usually.Along with the progress of Display Technique, increasing electronic equipment such as mobile phone, PDA(Personal Digital Assistant), digital camera, computer screen or mobile computer screen all are equipped with the new display of high-resolution color screen.
Be different from the voltage decision pixel intensity that common on the market LCD utilization is added in liquid crystal pixel, (Organic Light Emitting Display, OLED) luminous intensity is by LED forward bias voltage drop electric current decision pixel intensity to organic light emitting display.Organic light emitting display is utilized the self-luminous technology, does not only need back lighting, can also provide than LCD response time faster.In addition, organic light emitting display even also have preferred reduced value and broad advantages such as visual angle.At present common active organic electroluminescent display device uses low temperature polycrystalline silicon (low temperature polycrystalline silicon, LTPS) display of technology manufacturing.
See also Fig. 1, Fig. 1 is the structural representation of the thin-film transistor (TFT) that is applied in traditional organic LED panel.Known techniques provides a glass substrate 102 earlier when making organic LED panel 100, and black-matrix layer (the Black Matrix) 101 that pre-sizing is set is on glass substrate 102.Deposit buffer insulation layer 104 and one deck amorphous silicon membrane (not shown) more in regular turn on black-matrix layer 101 and glass substrate 102, and via quasi-molecule laser annealing (excimer laser annealing, ELA) etc. technology makes this amorphous silicon membrane crystallization again (recrystallize) become polysilicon membrane.Then utilize and carry out the first lithography technology (photo-etching-process, PEP), to etch required semiconductor layer (semiconductor layer) pattern in polysilicon membrane, deposit gate insulator (gateinsulator) 108 afterwards again and be covered in semiconductor layer 106 and buffering insulating barrier 104 surfaces.
And then etch gate metal 110 by the metal deposition process and second lithography.Can utilize gate metal 110 as self-aligned (self-alignment) shielding subsequently, semiconductor layer 106 is carried out boron ion plasma injection technology, to form source electrode (source) 103 and drain electrode (drain) 105.Then deposit interbedded insulating layer (inter-layer dielectric, ILD) 112, and cover gate metal 110 and gate insulator 108, carry out the 3rd lithography again, in order to remove the part interlayer insulating film 112 and the gate insulator 108 of source electrode 103 and drain electrode 105 tops, to define interlayer hole (via hole) 115.And then carry out another metal deposition process, and and carry out the 4th lithography, on interlayer hole 115 surfaces, and be electrically connected source electrode 103 and drain electrode 105 respectively with the metal level 114 that etches holding wire, drain metal etc.Then deposit a smooth protective layer (planarization layer) 116 on metal level 114 and interlayer insulating film 112, and carry out the 5th lithography (PEP), to remove the partial protection layer 116 of metal level 114 tops that are electrically connected drain electrode 105.And then formation tin indium oxide (Indium Tin Oxide; ITO) transparent conductive film (not shown) is on protective layer 116; and carry out the 6th lithography; with the show electrode 118 that defines suitable size; form light-emitting diode 120 and cathodic metal layer (cathode metal layer) 122 in show electrode 118 surfaces more subsequently, promptly finish organic LED panel 100 in the known techniques.
General pixel can be divided into luminous zone 130 and non-light-emitting area 132, in simple terms, utilizes black-matrix layer 101 to stop that the zone of light is non-light-emitting area 132, and light transparent regional 130 then is the luminous zone.And the purpose of black-matrix layer 101 mainly is the light leak that prevents between pixel, and the comparative that increases color, and the luminous efficiency that can avoid using polaroid (Polarizer) to be produced is consumed problem.Be usually used in black-matrix layer 101 at present and be metallic film, because etching is easy, and good shading effect.Yet in the present technology, black-matrix layer 101 is made in the bottom, successively makes other each layer afterwards again.As shown in Figure 2, the known black-matrix layer 101 of Fig. 2 behind high-temperature technology with the schematic diagram of transistor difference that other each layer produces.In LTPS technology, because the high temperature of technology can make glass substrate shrink, particularly the temperature that is produced in the technology of crystallization again is particularly strong, therefore cause pattern can't cooperate, cause bit errors (misalignment) with the pattern of the TFT of follow-up making with the black-matrix layer made in advance.Though can utilize the glass substrate of tempering in advance to avoid this problem, the costing an arm and a leg of tempered glass, and be unfavorable for reducing cost.
Summary of the invention
In view of this invention provides a kind of manufacture method of active matric organic LED panel, to address the above problem.
The invention provides a kind of manufacture method of organic LED panel, comprise substrate is provided; Form black-matrix layer on this substrate, form buffer insulation layer on this black-matrix layer, this black-matrix layer of patterning and this buffer insulation layer simultaneously, and form and comprise show electrode and thin-film transistor on this buffer insulation layer.
The present invention provides a kind of manufacture method of organic LED panel in addition, it comprises provides substrate, form black-matrix layer on this substrate, form buffer insulation layer on this substrate, form semiconductor layer on this buffer insulation layer, while this black-matrix layer of patterning and this buffer insulation layer, and form show electrode on this semiconductor layer.
The present invention provides a kind of manufacture method of organic electroluminescence panel again, and comprising provides substrate, forms black-matrix layer on this substrate, forms buffer insulation layer on this black-matrix layer, forms grid level metal on this black-matrix layer; Simultaneously this black-matrix layer of patterning and this buffer insulation layer, the deposition gate insulator covers on this grid level metal and this buffer insulation layer, and forms semiconductor layer and show electrode on this gate insulator.
The invention provides a kind of organic LED panel, it comprises substrate, black-matrix layer, buffer insulation layer, thin-film transistor, show electrode and light-emitting diode.This black-matrix layer is arranged on this substrate, has first figure.This buffer insulation layer is covered on this black-matrix layer, has second graph, and this second graph is substantially equal to this first figure.This thin-film transistor and this show electrode be arranged at this buffer insulation layer on.This light-emitting diode is covered on this show electrode.
Description of drawings
Fig. 1 is the structural representation of the thin-film transistor (TFT) that is applied in traditional organic LED panel.
Fig. 2 by known black-matrix layer behind high-temperature technology with other each layer of transistor the schematic diagram of generation difference.
Fig. 3 to Figure 12 illustrates and is the process schematic representation according to the active matric organic LED panel of first embodiment of the invention.
Figure 13 to Figure 22 illustrates and is the process schematic representation according to the active matric organic LED panel of second embodiment of the invention.
Figure 23 to Figure 28 illustrates and is the process schematic representation according to the active matric organic LED panel (AMOLED) of third embodiment of the invention.
[primary clustering symbol description]
100 organic light emitting display, 102 substrates
101 black-matrix layer, 103 source electrodes
105 drain electrodes of 104 buffer insulation layers
106 semiconductor layers, 108 gate insulators
110 gate metals, 112 interlayer insulating films
114 metal levels, 115 interlayer holes
116 protective layers, 118 show electrodes
120 Organic Light Emitting Diodes, 122 cathodic metal layers
130 luminous zones, 132 non-light-emitting areas
200,300 organic light emitting display, 202,302 substrates
204,304 black-matrix layer, 213,313 source electrodes
206,306 buffer insulation layers, 215,315 drain electrodes
208,308 semiconductor layers, 210,310 gate insulators
211,311 gate metals, 212,312 interlayer insulating films
218,318 metal levels, 217,317 interlayer holes
220,320 smooth protective layer 222,322 show electrodes
224,324 Organic Light Emitting Diodes, 226,326 cathodic metal layers
250,350 luminous zones, 252,352 non-light-emitting areas
400 organic light emitting display, 402 substrates
404 black-matrix layer, 413 source electrodes
415 drain electrodes of 406 buffer insulation layers
408 semiconductor layers, 410 gate insulators
411 gate metals, 418 metal levels
420 smooth protective layer 422 show electrodes
424 Organic Light Emitting Diodes, 426 cathodic metal layers
450 luminous zones, 452 non-light-emitting areas
Embodiment
Fig. 3 to Fig. 9 illustrates and is the process schematic representation according to the active matric organic LED panel (AMOLED) 200 of first embodiment of the invention.As shown in Figure 3, at first provide a glass substrate 202 to be used as infrabasal plate, form black-matrix layer 204 again in glass substrate 202.Subsequently as shown in Figure 4, in depositing one deck buffer insulation layer 206 on the surface of black-matrix layer 204 and covering on the black-matrix layer 204.Then on buffer insulation layer 206, deposit one deck amorphous silicon membrane (not shown), and, make this amorphous silicon membrane recrystallize into polysilicon membrane by annealing processs such as excimer laser.Utilize first mask to come this polysilicon membrane (not shown) is carried out first lithography (PEP) then, can obtain the pattern of required semiconductor layer 208.Next, shown in the 5th figure.Utilize second mask that black-matrix layer 204 and buffer insulation layer 206 are carried out second lithography (PEP).
Then can on buffer insulation layer 206, produce thin-film transistor.Consult Fig. 6, at semiconductor layer 208 and buffering insulating barrier 206 surface deposition gate insulators 210.Carry out the second deposit metal films technology then, to form one deck second metallic film (not shown) in gate insulator 210 surfaces, and utilize the 3rd mask to carry out the 3rd lithography (PEP), obtain gate metal 211 with etching, as shown in Figure 6, can utilize gate metal 211 as the self-aligned shielding subsequently, semiconductor layer 208 is carried out boron ion ion implantation technology, in semiconductor layer 208, to form source electrode 213 and drain electrode 215.
See also Fig. 7, then deposit interbedded insulating layer (inter-layer dielectric, ILD) 212, and cover gate metal 211 and gate insulator 210, utilize the 4th mask to carry out the 4th lithography (PEP) again, in order to remove the part interlayer insulating film 212 and the gate insulator 210 of source electrode 213 and drain electrode 215 tops, until source electrode 213 and drain electrode 215 surfaces, to form a plurality of interlayer holes 217 respectively at drain electrode 215 and source electrode 213 tops.
Next, as shown in Figure 8, carry out another metal deposition process, and utilize the 5th mask to carry out the 5th lithography (PEP), on interlayer hole 217 surfaces, and be electrically connected source electrode 213 and drain electrode 215 respectively with the metal level 218 that etches holding wire, drain metal etc.Then; as shown in Figure 9; deposit smooth protective layer (planarization layer) 220 on metal level 218 and interlayer insulating film 212; and utilize the 6th mask to carry out the 6th lithography (PEP), with the partial protection layer 220 of metal level 218 tops that remove to be electrically connected drain electrode 215 and produce electrode interlayer hole 219 on metal level 218.
Then; as shown in figure 10; form tin indium oxide (Indium Tin Oxide again; ITO) transparent conductive film (not shown) is on protective layer 220; and utilize the 6th mask to carry out the 6th lithography (PEP); with the show electrode 222 that defines suitable size, and utilize show electrode 222 to electrically connect metal level 218 and source electrode 213.As Figure 11 and shown in Figure 12, be formed with OLED 224 and cathodic metal layer (cathode metal layer) 226 again in show electrode 222 surfaces subsequently, promptly finish organic LED panel 200 in the present embodiment.When organic LED panel 200 running, light can penetrate the luminous zone 250 of organic LED panel 200, but because black-matrix layer 204 stop that light can't penetrate non-light-emitting area 252.
Seeing also Figure 13 to Figure 22 illustrates and is the process schematic representation according to the active matric organic LED panel (AMOLED) of second embodiment of the invention.As shown in figure 13, at first provide a glass substrate 302 to be used as infrabasal plate, form black-matrix layer 304 again, in depositing one deck buffer insulation layer 306 on the surface of black-matrix layer 304 and covering on the black-matrix layer 304 in glass substrate 302.Subsequently as shown in figure 14, then on buffer insulation layer 306, deposit one deck amorphous silicon membrane (not shown), and, make this amorphous silicon membrane recrystallize into polysilicon membrane by annealing processs such as excimer laser.Utilize first mask to come this polysilicon membrane (not shown) is carried out first lithography (PEP) then, can obtain the pattern of required semiconductor layer 308.
Then, consult Figure 15, at semiconductor layer 308 and buffering insulating barrier 306 surface depositions one gate insulator 310.Carry out the second deposit metal films technology then, to form one deck second metallic film (not shown) in gate insulator 310 surfaces, and utilize second mask to carry out second lithography (PEP), obtain gate metal 312 with etching, as shown in figure 15, can utilize gate metal 312 as the self-aligned shielding subsequently, semiconductor layer 308 is carried out boron ion ion implantation technology, in semiconductor layer 308, to form source electrode 313 and drain electrode 315.
See also Figure 16, then deposit interbedded insulating layer (inter-layer dielectric, ILD) 312, and cover gate metal 311 and gate insulator 310, utilize the 3rd mask to carry out the 3rd lithography (PEP) again, in order to remove the part interlayer insulating film 312 and the gate insulator 310 of source electrode 313 and drain electrode 315 tops, until source electrode 313 and drain electrode 315 surfaces, to form a plurality of interlayer holes 317 respectively at drain electrode 315 and source electrode 313 tops, the 3rd lithography technology is also removed interlayer insulating film 312 and the gate insulator 310 that is positioned on the buffer insulation layer 306 in the lump simultaneously.
Next, as shown in figure 17, carry out another metal deposition process, and utilize the 4th mask to carry out the 4th lithography (PEP), on interlayer hole 317 surfaces, and be electrically connected source electrode 313 and drain electrode 315 respectively with the metal level 318 that etches holding wire, drain metal etc.
Next, as shown in figure 18, utilize the 5th mask that black-matrix layer 304 and buffer insulation layer 306 are carried out the 5th lithography (PEP), make the black-matrix layer 304 and the buffer insulation layer 306 that do not cover interlayer insulating film 312 and gate insulator 310 be removed.
Afterwards; as shown in figure 19; deposit smooth protective layer (planarization layer) 320 on metal level 318, interlayer insulating film 312 and substrate 302; and utilize the 6th mask to carry out the 6th lithography (PEP), with the partial protection layer 320 of metal level 318 tops that remove to be electrically connected drain electrode 315 and produce electrode interlayer hole 319 on metal level 318.Then; as shown in figure 20; form tin indium oxide (IndiumTin Oxide again; ITO) transparent conductive film (not shown) is on protective layer 320; and utilize the 7th mask to carry out the 7th lithography (PEP); with the show electrode 322 that defines suitable size, and utilize show electrode 322 to electrically connect metal level 318 and source electrode 313.As Figure 21 and shown in Figure 22, be formed with OLED 324 and cathodic metal layer (cathodemetal layer) 326 again in show electrode 322 surfaces subsequently, promptly finish organic LED panel 300 in the present embodiment.When organic LED panel 300 running, light can penetrate the luminous zone 350 of organic LED panel 300, but because black-matrix layer 304 stop that light can't penetrate non-light-emitting area 352 easily.
The second embodiment of the present invention is different from the first embodiment part and is, the step of patterning black-matrix layer is after forming metal level 317 (shown in Figure 17).So still possess on the luminous zone 350 of organic LED panel 300 of interlayer insulating film 212 and gate insulator 210, the second embodiment the not configuration of interlayer insulating film and gate insulator compared to the zone of the luminous zone 250 of the organic LED panel 200 of first embodiment.In addition, compared to known techniques, because of using the same same gold-tinted technology definition that is masked in, except that the size penalty (CD Loss) that etching causes, the graphics area size of the buffer insulation layer 206,306 of two embodiment is substantially equal to the area of black-matrix layer 204,304, the figure of the buffer insulation layer 206,306 of two embodiment is same as the figure of black-matrix layer 204,304, so buffering insulation layer 206,306 only be arranged at non-light-emitting area 252,352 on, and the setting of insulation layer 206,306 is not all cushioned in luminous zone 250,350.So when light passed the luminous zone, the effect of colour cast also can effectively be improved.
Figure 23 to Figure 28 illustrates and is the process schematic representation according to the active matric organic LED panel (AMOLED) 400 of third embodiment of the invention.As shown in figure 23, at first provide a glass substrate 402 to be used as infrabasal plate, form black-matrix layer 404 again on glass substrate 402.Subsequently as shown in figure 24, in depositing one deck buffer insulation layer 406 on the surface of black-matrix layer 404 and covering on the black-matrix layer 404.
Consult Figure 24, then carry out the first deposit metal films technology, forming one decks first metallic film (not shown)s, and utilize first mask to carry out first lithography (PEP), obtain gate metal 411 with etching in buffer insulation layer 406 surface.
Next illustrate as Figure 25, at grid level metal 411 and buffering insulating barrier 406 surface deposition gate insulators 410 (gate oxide).Then on buffer insulation layer 406, deposit one deck amorphous silicon membrane (not shown), and, make this amorphous silicon membrane recrystallize into polysilicon membrane by annealing processs such as excimer laser.Utilize second mask to come this polysilicon membrane (not shown) is carried out second lithography (PEP) then, can obtain the pattern of required semiconductor layer 408.Can carry out boron ion ion implantation technology to semiconductor layer 408 subsequently, in semiconductor layer 408, to form source electrode 413 and drain electrode 415.
Next, as shown in figure 26.Utilize the 3rd mask that black-matrix layer 404 and buffer insulation layer 406 are carried out the 3rd lithography (PEP).Because black-matrix layer 404 and buffer insulation layer 406 utilize same mask process to define, so the graphics area that black-matrix layer 404 and buffer insulation layer 406 produce about equally.
Next, as shown in figure 27, carry out another metal deposition process, on gate insulator 410 and semiconductor layer 408, deposit second metallic film (figure does not show) earlier, and utilize the 4th mask to carry out the 4th lithography (PEP), etching the metal level 418 of holding wire etc., and metal level 418 is electrically connected source electrode 413 and drain electrode 415 respectively.Then; deposit smooth protective layer (planarization layer) 420 on metal level 418; and utilize the 5th mask to carry out the 5th lithography (PEP), with the smooth protective layer 420 of part of metal level 418 tops that remove to be electrically connected drain electrode 415 and produce electrode interlayer hole 419 on metal level 418.
Then; as shown in figure 28; form tin indium oxide (Indium Tin Oxide again; ITO) transparent conductive film (not shown) is on smooth protective layer 420; and utilize the 5th mask to carry out the 5th lithography (PEP); with the show electrode 422 that defines suitable size, and utilize show electrode 422 to electrically connect metal level 418.Be formed with OLED 424 and cathodic metal layer (cathode metallayer) 426 again in show electrode 422 surfaces, promptly finish organic LED panel 400 in the present embodiment.When organic LED panel 400 running, light can penetrate the luminous zone 450 of organic LED panel 400, but because black-matrix layer 404 stop that light can't penetrate non-light-emitting area 452 easily.
Institute is old on vertical, owing to just carry out after the step that the present invention carries out patterning to black-matrix layer is waited until the step that recrystallizes into polysilicon membrane of finishing high temperature, so can avoid black-matrix layer pattern Yin Gaowen and with other situation of each layer generation bit errors, and the present invention do not need to use the glass substrate of tempering in advance, more can save the cost of manufacturing.In addition, compared to known techniques, the below of luminous zone of the present invention has been lacked one deck buffer insulation layer at least, so when light passed the luminous zone, the effect of colour cast also can effectively be improved.
The above person only is a preferred implementation of the present invention, and those of ordinary skills help the equivalence of doing according to spirit of the present invention and modify or variation, all are covered by in the claim.
Claims (28)
1. the manufacture method of an organic electroluminescence panel comprises:
Substrate is provided;
Form black-matrix layer on this substrate;
Form buffer insulation layer on this black-matrix layer;
While this black-matrix layer of patterning and this buffer insulation layer; And
Form thin-film transistor and show electrode on this buffer insulation layer.
2. manufacture method as claimed in claim 1, wherein this black-matrix layer of this patterning and this buffer insulation layer use same mask definition.
3. manufacture method as claimed in claim 1 wherein forms thin-film transistor and the show electrode step on this buffer insulation layer and comprises:
Form semiconductor layer on this buffer insulation layer;
The deposition gate insulator covers this semiconductor layer and this buffer insulation layer;
Form gate metal this gate insulator laminar surface in this semiconductor layer top;
Utilize this gate metal to do shielding this semiconductor layer is carried out the ion injection, to form source electrode and drain electrode in this semiconductor layer;
The deposition interbedded insulating layer, and cover this gate metal and this gate insulator;
This gate insulator of etching and this interlayer insulating film are to form a plurality of interlayer holes on this drain electrode and this source electrode;
Form metal level on the surface of these a plurality of interlayer holes;
Form protective layer on this metal level and this interlayer insulating film;
Form this show electrode in this protective layer surface; And
Form light-emitting diode on this show electrode.
4. manufacture method as claimed in claim 3, the method that wherein forms this metal level also comprises:
Form first metallic film in this substrate surface; And
This first metallic film of etching is to form the first metal layer.
5. manufacture method as claimed in claim 3, the method that wherein forms this semiconductor layer also comprises:
Deposit non-polysilicon membrane in this buffer insulation layer surface;
This non-polysilicon membrane is carried out crystallization processes again, is a polysilicon membrane so that this non-polysilicon membrane changes into; And
This polysilicon membrane of etching is to form this semiconductor layer.
6. manufacture method as claimed in claim 3, the method that wherein forms this gate metal also comprises:
Form second metallic film in this gate insulator laminar surface; And
This second metallic film of etching is to form this gate metal.
7. manufacture method as claimed in claim 3, the method that wherein forms this show electrode also comprises:
This protective layer of etching is to form the electrode interlayer hole on this metal level;
Form transparent conductive film in this protective layer and this layer on surface of metal; And
This transparent conductive film of etching is to form this show electrode.
8. manufacture method as claimed in claim 7, wherein this transparent conductive film be tin indium oxide and indium zinc oxide one of them.
9. the manufacture method of an active matric organic LED panel, it comprises:
Substrate is provided;
Form black-matrix layer on this substrate;
Form buffer insulation layer on this black-matrix layer;
Form semiconductor layer on this buffer insulation layer;
While this black-matrix layer of patterning and this buffer insulation layer; And
Form show electrode on this semiconductor layer.
10. manufacture method as claimed in claim 9, wherein this black-matrix layer of patterning and this buffer insulation layer use same mask definition.
11. manufacture method as claimed in claim 9 also comprises:
The deposition gate insulator covers this semiconductor layer and this buffer insulation layer;
This gate insulator laminar surface in this semiconductor layer top forms gate metal;
Utilize this gate metal to do shielding this semiconductor layer is carried out the ion injection, to form source electrode and drain electrode in this semiconductor layer;
The deposition interlayer insulating film, and cover this gate metal and gate insulator;
This gate insulator of etching and this interlayer insulating film are to form a plurality of interlayer holes on this drain electrode and this source electrode; And
Form metal level on the surface of these a plurality of interlayer holes.
12., wherein form the step of show electrode on this semiconductor layer and comprise as the manufacture method of claim 11:
Form smooth protective layer on this metal level and this interlayer insulating film; And
Form this show electrode in this smooth protective layer surface.
13. as the manufacture method of claim 11, the method that wherein forms this metal level also comprises:
Form first metallic film in this substrate surface; And
This first metallic film of etching is to form this metal level.
14. as the manufacture method of claim 11, the method that wherein forms this semiconductor layer also comprises:
Deposit non-polysilicon membrane in this buffer insulation layer surface;
This non-polysilicon membrane is carried out crystallization processes again, be polysilicon membrane so that this non-polysilicon membrane changes into; And
This polysilicon membrane of etching is to form this semiconductor layer.
15. as the manufacture method of claim 11, the method that wherein forms this gate metal also comprises:
Form second metallic film in this gate insulator laminar surface; And
This second metallic film of etching is to form this gate metal.
16. as the manufacture method of claim 11, the method that wherein forms this show electrode also comprises:
This protective layer of etching is to form the electrode interlayer hole on this metal level;
Form transparent conductive film in this protective layer and this layer on surface of metal; And
This transparent conductive film of etching is to form this show electrode.
17. as the manufacture method of claim 16, wherein this transparent conductive film be tin indium oxide and indium zinc oxide one of them.
18. the manufacture method of an organic electroluminescence panel comprises:
Substrate is provided;
Form black-matrix layer on this substrate;
Form buffer insulation layer on this black-matrix layer;
Form grid level metal on this black-matrix layer;
The deposition gate insulator covers on this grid level metal and this buffer insulation layer;
Form semiconductor layer on this gate insulator; And
While this gate insulator of patterning, this black-matrix layer and this buffer insulation layer.
19. as the manufacture method of claim 18, wherein this gate insulator of this patterning, this black-matrix layer and this buffer insulation layer use same mask definition.
20. as the manufacture method of claim 18, the method that wherein forms this gate metal also comprises:
Form first metallic film in this buffer insulation layer surface; And
This first metallic film of etching is to form this gate metal.
21. as the manufacture method of claim 18, it also comprises:
This semiconductor layer is carried out ion inject, to form source electrode and drain electrode in this semiconductor layer;
Form metal level on this semiconductor layer and this grid class F insulation layer;
Form smooth protective layer on this metal level and this grid class F insulation layer; And
Form this show electrode in this smooth protective layer surface.
22. as the manufacture method of claim 21, the method that wherein forms this metal level also comprises:
Form second metallic film in this substrate surface; And
This second metallic film of etching is to form this metal level.
23. as the manufacture method of claim 21, the method that wherein forms this show electrode also comprises:
This protective layer of etching is to form the electrode interlayer hole on this metal level;
Form transparent conductive film in this protective layer and this layer on surface of metal; And
This transparent conductive film of etching is to form this show electrode.
24. as the manufacture method of claim 23, wherein this transparent conductive film be tin indium oxide and indium zinc oxide one of them.
25. as the manufacture method of claim 18, the method that wherein forms this semiconductor layer also comprises:
Deposit non-polysilicon membrane in this buffer insulation layer surface;
This non-polysilicon membrane is carried out crystallization processes again, be polysilicon membrane so that this non-polysilicon membrane changes into; And
This polysilicon membrane of etching is to form this semiconductor layer.
26. an organic LED panel, it comprises:
Substrate;
Black-matrix layer is arranged on this substrate, has first figure;
Buffer insulation layer is covered on this black-matrix layer, has second graph, and this second graph is substantially equal to this first figure;
Thin-film transistor, be arranged at this buffer insulation layer on;
Show electrode, be arranged at this buffer insulation layer on; And
Light-emitting diode is covered on this show electrode.
27. as the organic LED panel of claim 26, wherein this thin-film transistor comprises semiconductor layer and grid level metal.
28. as the organic LED panel of claim 26, wherein this show electrode be tin indium oxide and indium zinc oxide one of them.
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| WO2019061886A1 (en) * | 2017-09-30 | 2019-04-04 | 武汉华星光电技术有限公司 | Display panel and manufacturing method therefor |
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| KR101942515B1 (en) | 2012-05-03 | 2019-01-28 | 삼성디스플레이 주식회사 | Organic light emitting display apparatus and method of manufacturing the same |
Family Cites Families (3)
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|---|---|---|---|---|
| TWI233759B (en) * | 2004-05-25 | 2005-06-01 | Univision Technology Inc | Organic light-emitting diode element and manufacturing method thereof |
| CN1700817A (en) * | 2005-04-29 | 2005-11-23 | 友达光电股份有限公司 | Method for making OLED |
| CN100553389C (en) * | 2005-09-29 | 2009-10-21 | 友达光电股份有限公司 | Organic LED display panel |
-
2006
- 2006-04-28 CN CNB2006100774949A patent/CN100372099C/en active Active
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| CN102576508A (en) * | 2009-10-08 | 2012-07-11 | 夏普株式会社 | Light emitting panel device wherein a plurality of panels respectively having light emitting sections are connected , and image display device and illuminating device provided with the light emitting panel device |
| WO2019061886A1 (en) * | 2017-09-30 | 2019-04-04 | 武汉华星光电技术有限公司 | Display panel and manufacturing method therefor |
| CN111048495A (en) * | 2018-10-11 | 2020-04-21 | 启端光电股份有限公司 | Light emitting diode display and method of manufacturing the same |
| CN111048495B (en) * | 2018-10-11 | 2021-11-26 | 启端光电股份有限公司 | Light emitting diode display and method of manufacturing the same |
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