CN1846355A - Delayed locked loop phase blender circuit - Google Patents
Delayed locked loop phase blender circuit Download PDFInfo
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- CN1846355A CN1846355A CNA2004800249381A CN200480024938A CN1846355A CN 1846355 A CN1846355 A CN 1846355A CN A2004800249381 A CNA2004800249381 A CN A2004800249381A CN 200480024938 A CN200480024938 A CN 200480024938A CN 1846355 A CN1846355 A CN 1846355A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00065—Variable delay controlled by a digital setting by current control, e.g. by parallel current control transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
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Abstract
Techniques and circuit configurations for fine phase adjustments, for example, in a delay-locked loop (DLL) circuit are provided. Multiple phase signals may be generated from a single current source by selectively coupling one or more delay elements to an output node of the current source. The delay elements may vary the timing of a signal generated by switching the current source.
Description
Background of invention
Technical field
Present invention relates in general to integrated circuit (IC)-components, and relate in particular to the delay lock loop that is used for integrated circuit (IC)-components.
Background technology
In integrated circuit miscellaneous (integrated circuit IC) device, utilize delay lock loop (Delay locked loop DLL) to make output signal and periodic input signal synchronous.In other words, the purpose of DLL is phase difference between input and output signal is adjusted into and approaches zero.Fig. 1 illustrates and is configured to make clock signal CK
OUTWith input clock signal CK
INSynchronous exemplary DLL circuit 100.
As illustrated, DLL circuit 100 comprises delay line 102, phase detectors 104, control logic 106 and phase blender 108 generally.Phase detectors 104 are CK
OUTPhase place and CK
INCompare, and produce signal according to the phase difference that is detected to control logic 106, described control logic 106 is adjusted delay line 102 and phase blender 108.Control logic 106 can comprise any suitable circuit, such as the register of shift register or any other type, comes pilot delay line 102 and phase blender 108 so that make CK
INBeing deferred to is enough to synchronous CK
OUTDegree.In other words, control logic 106 can pilot delay line 102 and phase blender 108, so that at CK
INAnd CK
OUTBetween delay be substantially equal to the multiples of their clock cycle.
Illustrated among Fig. 2, delay line 102 can comprise many delay blocks 110, the single unit delay of each delay block 110 expression.Can between each delay block 110, provide tap 112, make it possible to select CK
INDifference postpone version.For example, tap 112
1On signal V
1Corresponding to the CK that postpones a unit delay
INTherefore, can export the total delay of controlling by described delay line 102 from delay line 102 by selecting suitable tap 112.In typical case, unit delay equals the propagation delay of employed one or two inverter in delay block 110.
Unfortunately, for high-speed applications, this unit delay time may be too rough (greatly) and can not provide and make CK
INAnd CK
OUTAbundant synchronous desired phase resolution.Thereby phase blender 108 can be configured to the phase place adjustment that provides trickleer than the unit delay of the delay line 102 that is allowed.As illustrated, phase blender 108 can be taked respectively early and slow phase delay signal V
EAnd V
LAs input, they differ a unit delay in typical case.For example, V
EAnd V
LCan be respectively from the adjacent taps 112 of delay line 102
iWith 112
I+1 Obtain.Phase blender 108 generation output signals (for example, are CK in this case then
OUT), described output signal has at signal V
EAnd V
LPhase place between centre (or " mixing ") phase place.
Fig. 3 A illustrates the exemplary circuit arrangement of phase blender 108, and described phase blender 108 is configured to produce four signals that phase approximation differs 90 °.In other words, illustrated among Fig. 3 B, described signal is according to the T/4 equal distribution, and wherein T is an employed unit delay in delay line 102, and it makes V
EAnd V
LSeparate.For example, can export via the signal that switch 150 is selected to be wanted by in 106 controls of the control logic shown in Fig. 1.As illustrated, signal V
BL2, V
BL2And V
BL3Can be by mixing V to 130 via corresponding mixing inverter
EAnd V
LProduce, each mixes inverter and is used for receiving signal V early to comprising
EInverter 130
EBe used to receive slow signal V
LInverter 130
LWhen these outputs that mix inverter 130 arrive comparator 140
1-3Threshold level the time, produce output signal V
BL2, V
BL2And V
BL3
With reference to 130 transistor being represented can describe the phase signal that produces mixing with the corresponding time sequence figure of Fig. 4 B at the mixing inverter shown in Fig. 4 A.At T1, V
EAnd V
LAll be low, connect inverter 130
EWith 130
LPMOS transistor PE and PL, and turn off inverter 130
EWith 130
LNmos pass transistor NE and NL.As a result, (anti-phase) output V
BL1Be initially logic high.
At T2, signal V early
EBe changed to effectively, turn off PE and connect NE, and PL keep connecting.Thereby, determine V by the transistor conduct resistance (current drives) of PL and NE
BL1Voltage level.At T3, at V
EA unit delay after being changed to effectively, V
LBe changed to effectively, turn off PL and connect NL, thereby V
BL1Drive and be complete logic low.Though not shown, yet work as V
EAnd V
LBe changed to when invalid, similarly switch.For example, work as V
EBe changed to when invalid, connect PE and turn off NE, and NL keep connecting, and determines V by the conducting resistance (current drives) of PE and NL
BL1Voltage level.At last, V
LIt is invalid to be changed to, and connect PL and turn off NL, thereby V
BL1Turn back to complete logic high.
In general, inverter 130 early
EDrive current with respect to slow inverter 130
LStrong more, at V
BL1And V
EBetween delay more little.Thereby each mixes inverter 130 relative drive current is realized different phase signals can to change (for example, by changing the ratio of device widths).As an example, in order to produce only than V
EThe V of slow T/4
BL1, inverter 130 early
EDevice widths should be greater than slow inverter 130
LDevice widths.Compare V in order to produce
EThe V of slow T/2
BL2, early the device widths with slow inverter should be close to identical.Compare V in order to produce
EThe V of slow 3 T/4
BL3, slow inverter 130
LDevice widths should be greater than inverter 130 morning
EDevice widths.
Though this type of hybrid circuit provides trickle phase place adjustment to the signal from delay line 102, yet described circuit has many shortcomings.For example, determine to mix the size of inverter so that produce the task that the phase signal with the resolution that required may be a difficulty with enough precision.As illustrated among Fig. 3 A, each phase place is mixed inverter and is had one or more current sources (for example, PE and PL) and the comparator 140 of oneself thereof to 130 in addition.Though illustrated example only has four outputs, practical application can have several more outputs or several cascaded stages.As a result, a large amount of inverter and comparators may consume a large amount of electric currents.
In view of the above, need a kind of improvement technology and circuit arrangement that is used for the signal that the DLL circuit is produced is carried out trickle adjustment.
Summary of the invention
The embodiment of the invention provides improvement technology and the circuit arrangement that is used for the signal that the DLL circuit is produced is carried out trickle adjustment generally.
Embodiment provides the phase hybrid circuit that is used to be created on the phase place with respect to the different a plurality of signals of phase signal morning.Phase hybrid circuit comprises the current source with shared output node, one or more delay element and one or more switch generally, described one or more switch is used for one or more delay elements are coupled to selectively the shared output node of described current source, wherein depends in the voltage level needed time below the threshold level that is reduced to of described shared output node after morning, phase signal was changed to effectively in one or more delay elements which is coupled to described shared output node.
Another embodiment provides the phase hybrid circuit that is used to be created on the phase place with respect to the different a plurality of signals of phase signal morning.Phase hybrid circuit comprises the current source with shared output node and control input generally, has comparator with the input of the shared output node coupling of described current source, a plurality of delay elements, be used for being changed to when effective path of current from described shared output node when phase signal early, and a plurality of switches, be used for one or more delay elements are coupled to the output node of described current source selectively so that the voltage level that changes at described shared output node according to the electric current by described path is reduced to the needed time below the threshold level, described control input is used for forbidding described current source when effective when the slow phase signal of trailing phase signal morning is changed to.
Another embodiment provides and has been used to produce the output delay of output signal locking loop of aiming at input signal.Delay-locked loop circuit comprises generally and is used to provide the delay line that postpones the phase signal of one or more unit delays with respect to input signal, be used to produce and have by morning that described delay line provided and the phase hybrid circuit of the blended phase signals of phase place between the phase signal late, described phase hybrid circuit comprises current source and is used for being coupled to selectively one or more delay elements of the shared output node of described current source, wherein after described morning, phase signal was changed to effectively, depend in one or more delay elements which is coupled to described shared output node in the voltage level needed time below the threshold level that is reduced to of described shared output node, and control logic is configured to monitor the time lag (skew) between input and output signal, and produce one or more control signals according to described time lag the morning that provides to described phase hybrid circuit and signal late are provided, and one or more delay elements are coupled to described shared output node selectively.
Another embodiment provides dynamic random access memory (DRAM) device, comprises one or more memory elements and delay-locked loop circuit generally, is used to make the data output from one or more memory elements synchronous with clock signal.Delay-locked loop circuit comprises (i) delay line generally, (ii) phase hybrid circuit, described phase hybrid circuit comprises current source and is used for being coupled to selectively one or more delay elements of the shared output node of described current source, wherein be changed to effectively by phase signal morning that described delay line provided after, depend in one or more delay elements which is coupled to described shared output node in the voltage level needed time below the threshold level that is reduced to of described shared output node, described delay-locked loop circuit also comprises (iii) control logic, be configured to monitor the time lag between input and output signal, and produce one or more control signals according to described time lag and select by described delay line, and one or more delay elements are coupled to described shared output node selectively to signal morning that described phase hybrid circuit provided.
Another embodiment provides to be used to produce to have in the morning signal and the slow method of the phase signal of the intermediate phase between the signal phase.Described method comprise generally when signal early be changed to when effective by one or more switches described morning signal be coupled to the control input of described one or more switches so that be current supplying path from the shared output node of current source, and closed one or more switch is so that be coupled to one or more delay elements selectively the shared output node of described current source, wherein according to electric current, which in closed one or more switch the voltage level of the shared output node needed time below the threshold level that is reduced to depend on.
Description of drawings
Reference is illustrated embodiment in the accompanying drawings, and the specific descriptions of being summarized above can obtaining of the present invention can obtain and understand the above-named feature of the present invention, advantage and purpose thus in detail.
Yet therefore and be not intended to and limit the scope of the invention, should be noted that accompanying drawing only illustrates exemplary embodiments of the present invention and, the present invention also allows other same effectively embodiment.
Fig. 1 illustrates exemplary delay lock loop (DLL) circuit.
Fig. 2 illustrates the exemplary delay line according to prior art.
Fig. 3 A-3B illustrates exemplary DLL blender circuit and corresponding sequential chart according to prior art respectively.
Fig. 4 A-4B illustrates the right illustrative diagram and the corresponding sequential chart of inverter of the DLL blender circuit of Fig. 3 respectively.
Fig. 5 illustrates exemplary dynamic random access memory (DRAM) device that utilizes dynamic locking ring (dynamic lockedloop DLL) circuit according to the embodiment of the invention.
Fig. 6 is used to utilize the DLL circuit of Fig. 5 to make the flow chart of the synchronous exemplary operation of input and output signal.
Fig. 7 A-7B illustrates the exemplary DLL blender circuit according to the embodiment of the invention.
Fig. 7 C illustrates the exemplary sequential chart corresponding to the DLL blender circuit of Fig. 7 A-7B.
Fig. 8 illustrates the exemplary DLL blender circuit according to another embodiment of the present invention.
Embodiment
Embodiments of the invention provide generally and have been used for for example carrying out improvement technology and the circuit arrangement that fine phase is adjusted at delay lock loop (DLL) circuit.Be better than as utilizing one or more different current sources to produce each fine setting phase signal (each of Fig. 1 mixed inverter to transistor PE and PL in 130) in the prior art, embodiments of the invention can produce a plurality of phase signals from the single current source.In order to produce signal with out of phase, can be coupled to current source to different delay elements selectively, described delay element is used to change by switching the timing of the signal that described current source produces.As a result, circuit arrangement of the present invention can be easier to design, be easy to make, take up an area of littler and consumption electric current still less.
As used herein, term current source general reference is used to the electric current that provides necessary so that produce the device of any kind of signal, such as being coupled to source current line (for example, V
DD) switching transistor (for example, PFET or NFET).Can in various application, utilize technology as described herein and circuit arrangement to adjust the phase place of the signal that produces.Yet for the ease of understanding, following description will be the embodiment that utilizes technology in the DLL circuit of dynamic random access memory (DRAM) and circuit arrangement as specific embodiment, but does not limit applied example.
Exemplary DRAM device
Fig. 5 illustrates exemplary dynamic random access memory (DRAM) device 500 that utilizes dynamic locking ring (DLL) circuit 510 according to the embodiment of the invention.The typical case of DRAM standard require to be from the data of memory array 540 when the rising edge (and the trailing edge in the double data rate device) of the clock signal that externally provides (CLK) at output line DQ[0:N] go up available.Sometimes, DRAM may be provided for the data strobe signal DQS that shows that data can be used, and described data strobe signal DQS also should be synchronous with CLK.
Being used to make a synchronous method of DQ or DQS and CLK can be to utilize CLK to make drive circuit 530 synchronous on clock.Yet a plurality of elements may strengthen the phase delay between the CLK of the CLK of device input and arrival drive circuit 530, such as input buffer 502 and the interconnection line that is used for propagating by device 500 CLK.The variation of manufacturing process, temperature and operational clock frequency can strengthen further delay.Thereby, directly utilize CLK to come clock synchronization drive circuit 530 may cause undesired time lag between CLK and DQ or DQS signal, described time lag may reduce effective dateout window.
Yet DLL circuit 510 can be used for postponing to make DQS and DQ signal and CLK signal Synchronization by introducing artificial CLK.Thereby DLL circuit 510 can be used for by making data output and the output clock CK that is used for clock synchronization drive circuit 530
OUTThe rising and falling edges of (with the CLK homophase) is synchronous, increases effective dateout window.As illustrated, DLL circuit 510 can comprise delay line 512, phase detectors 504 and control logic 506.Just as the DLL circuit of routine, delay line 512 can comprise a string rough relatively unit delay and can be used for carrying out the coarse phase adjustment, and phase blender 520 can be used for carrying out trickleer phase place adjustment.
Described the operation of DLL circuit 510 and phase blender 530 with reference to figure 6, Fig. 6 illustrates the flow chart that is used to make the synchronous exemplary operation of input and output signal 600.For example, can be during the initialization sequence of DLL (for example, power up or finish self-refresh mode) come executable operations 600 so that pilot delay line 512 and phase blender 530 via control logic 506.Executable operations 600 is come CK continuously
OUTCarry out " runtime " and adjust, for example compensate because the variation of the CLK frequency that variations in temperature caused or the variation of its delay.
Under any circumstance, in step 602, operation 600 is by monitoring at CK
INAnd CK
OUTBetween time lag (phase difference) beginning.For example, control logic 506 can monitor the one or more signals that produced by phase detectors 504, and described signal is used to be illustrated in CK
INAnd CK
OUTBetween phase difference.In step 604, adjust coarse delay be created on the phase place prior to be later than CK
INMorning and slow signal.For example, control logic 506 can produce one or more control signals and selects the adjacent taps of delay line 512 so that early and slow signal V
EAnd V
L(for example, one of phase phasic difference postpones unit) is fed to phase blender 530.
In step 606, one or more delay elements are coupled to the common points of current source selectively have on early and slow signal or the CK of phase place between them so that produce
OUTFor example, phase blender 520 can comprise one or more delay elements 526, and described delay element 526 can be coupled to the shared output node 526 of current source 522 selectively.As below describing in more detail, delay element 524 can be used for changing at signal V morning
EAfter being changed to effectively, arrive the needed time of threshold value switching voltage levels of comparator 528 at the voltage level of common points 526.
If CK
INAnd CK
OUTBe aligned, as determine (for example, according to the feedback from phase detectors 504) in step 608, so in step 610, DLL is considered to lock.Otherwise operation 600 turns back to step 606, changes one or more delay elements 524 of the common points 526 that is coupled to current source 520.Can repetitive operation 606-608, up to CK
INAnd CK
OUTBe aligned.For some embodiment, can pass through at first producing minimum delay (for example, CK
OUTWith signal VE homophase morning) one or more delay elements 524 be coupled to common points 526, and postpone up to CK so that increase at each delay element 524 that is coupled that changes
INAnd CK
OUTBe aligned, finely tune.
Exemplary DLL blender circuit
For example, Fig. 7 B illustrates as phase signal V morning
EBe changed to the phase blender 720 when effective, wherein switch S E is closed so that provide current path by transistor NE.Fig. 7 C illustrates when switch S E is closed signal V early
E(702), slow signal V
L(704) and (anti-phase) mixed signal V
BL1706 exemplary sequential chart.As illustrated, at time T 1, V
EAnd V
LIt is invalid to be changed to, and does not have current path ground connection and common points 726 to be precharged to V
DDWhen early signal VE was changed to effectively (line 702) in time T 2, NE provided the current path from common points 726 to ground.Thereby, at time T 3 slow signal V
LBefore being changed to effectively, V
BL1Voltage level be the function of effective connection resistance of PL and NE.In case signal is changed to effectively late, turn-off PL so and connect NL, make common points 726 discharges by NE and NL.
Thereby the size of PL, NL and the NE output capacitance of common points 726 (and) will determine V
BL1With the crossing time of the switching threshold voltage of comparator 140.In view of the above, can select the size of PL, NL and NE to endeavour to ensure when switch S E is closed CK
OUTBe to aim at the phase place of signal VE early.For some embodiment, can select the size of transistor 150 to change each transistorized effective resistance to make great efforts to produce CK with even distribution phase
OUT(for example, corresponding in the blended voltage signals shown in Fig. 3 B, each is 90 °).
In other words, can select the size of N1-N3 to endeavour to ensure when distinguishing Closing Switch S1, S2 and S3 CK
OUTBe relative respectively signal V early
EThe phase place that postpones 90 °, 180 ° and 270 °.As illustrated, because effectively transistor resistance is inversely proportional to channel width generally, so transistorized width can reduce (for example, NE=2 * N1=4 * N2=8 * N3) gradually from NE to N3.Certainly, for some embodiment, can be coupled to common points to a plurality of transistors 150 simultaneously so that all obtain desired timing for any given phase delay.In other words, can select transistorized size to produce the desired switching time of comparator 140 with the effective resistance that causes parallel transistor.
By comparison, the circuit arrangement of DLL blender 720 is compared the assembly that has still less and much simple with the circuit arrangement of the DLL blender 120 of Fig. 3 A.As a result, can in identical or less circuit area, provide further fine setting (for example, the blended phase signals more than four).Can be by interpolation extra transistor 150 or by cascade multi-level mixer circuit 720, for example each continuous level provides trickleer phase resolution, and additional blended phase signals is provided.In addition, by utilizing single current source 722 and single comparator 140, DLL blender 720 can consume the electric current that obviously lacks than the DLL blender 120 of routine.
As previously mentioned, the switching time of the common points 726 of current source 722 can also be by its output capacitance decision, and described output capacitance comprises the input capacitance of comparator 140 and any other electric capacity on the described common points 726 generally.Thereby, can also change CK by the electric capacity that changes common points 726
OUTPhase place.
Fig. 8 illustrates exemplary DLL blender circuit 820, wherein by selectively one or more capacitors 170 being coupled to the common points 826 of current source 822, changes the electric capacity on described common points 826.In other words, one or more capacitors 170 that can be coupled selectively are so that change as signal V morning
EBe changed to when effective via NE with ought be after a while signal V late
LBe changed to when effective discharge rate via the common points 826 of NE and NL.
Thereby the size that can select capacitor 170 (CE and C1-C3) is to endeavour to ensure V
BL1The time of intersecting with the switching threshold of comparator 140 is corresponding to desired phase signal (for example, the V of Fig. 3 B
BLEAnd V
BL1-V
BL3).As illustrated, in order to produce mixed signal V the earliest
BLE(for example, with signal V morning
EHomophase), when Closing Switch SE, CE can be minimum capacitor 170.Similarly, can increase the size of C1-C3 gradually to endeavour to ensure when distinguishing Closing Switch S1, S2 and S3 CK
OUTBe with respect to signal V morning
EThe phase place that postpones 90 °, 180 ° and 270 °.Certainly, for some embodiment, can be coupled to common points to a plurality of capacitors 170 simultaneously so that obtain desired timing for any given phase delay.In other words, can select the value of capacitor 170 so that the desired switching time of effective parasitic capacitance (it adds) generation comparator 140.
Capacitor 170 can be the capacitor of any suitable type, and exact type can depend on employed type on the device that utilizes hybrid circuit 820.For example, if described device is the DRAM device, can uses so with the technology of capacitor (for example, zanjon or the stacked capacitor) same type of memory cell and make capacitor, this can reduce the cost of whole system.In addition, for some embodiment, the delay element of phase hybrid circuit can comprise capacitor and the transistorized combination that can be coupled to common current source according to any suitable combination, so that as a plurality of phase place mixed signals of generation described here.
Sum up
By one or more delay elements being coupled to selectively the common points of hybrid circuit, embodiments of the invention can use the single current source to be created in to differ on the phase place a plurality of mixed signals of one or more reference signals.Thereby, for each mixed signal, comparing design with the conventional hybrid circuit that utilizes one or more independent current sources and implement according to the phase hybrid circuit of the embodiment of the invention can be more simple, and can occupy less circuit area, thereby consumes electric current still less.
Though above at be the preferred embodiments of the present invention, yet under the situation that does not break away from base region of the present invention, can also design other and further embodiment of the present invention, and scope of the present invention is determined by claim subsequently.
Claims (27)
1. phase hybrid circuit that is used to be created on the phase place with respect to the different a plurality of signals of phase signal morning comprises:
Current source has shared output node;
One or more delay elements; With
One or more switches, be used for described one or more delay elements are coupled to selectively the shared output node of described current source, wherein after described morning, phase signal was changed to effectively, depend in one or more delay elements which is coupled to described shared output node in the voltage level needed time below the threshold level that is reduced to of described shared output node.
2. phase hybrid circuit as claimed in claim 1, wherein one or more delay elements comprise at least one transistor, be used in response to morning phase signal be changed to the current supplying path of effectively coming for from the shared output node of described current source.
3. phase hybrid circuit as claimed in claim 2, wherein at least one transistor comprises a plurality of transistors with different sizes.
4. phase hybrid circuit as claimed in claim 3 wherein selects the phase place of transistorized size so that a plurality of signals to differ the phase place that equates basically each other.
5. phase hybrid circuit as claimed in claim 1, wherein one or more delay elements comprise at least one capacitor with the shared output node coupling of described current source.
6. phase hybrid circuit as claimed in claim 5, wherein at least one capacitor comprises a plurality of capacitors with different capacitances.
7. phase hybrid circuit as claimed in claim 6 wherein selects the phase place of capacitor value so that a plurality of signals to differ the phase place that equates basically each other.
8. phase hybrid circuit that is used to be created on the phase place with respect to the different a plurality of signals of phase signal morning comprises:
Current source has shared output node and control input, and described control input is used for forbidding described current source when effective when the slow phase signal of trailing phase signal morning is changed to;
Comparator has the input with the shared output node coupling of described current source;
A plurality of delay elements;
Be used for when described morning phase signal be changed to when effective path of current from shared output node; With
A plurality of switches are used for one or more delay elements are coupled to selectively the output node of described current source, so that the voltage level that changes described shared output node according to the electric current by described path is reduced to the needed time below the threshold level.
9. phase hybrid circuit as claimed in claim 8 wherein is used for path of current and comprises at least one transistor, and described transistor reception phase signal morning is as input.
10. phase hybrid circuit as claimed in claim 9, wherein at least one transistor is a delay element that is coupled to the shared output node of described current source via one of switch.
11. phase hybrid circuit as claimed in claim 9, wherein at least one transistor comprises that nmos pass transistor and described current source comprise the PMOS transistor.
12. phase hybrid circuit as claimed in claim 9 wherein is used for path of current and also comprises at least one transistor, described transistor receives slow phase signal as input.
13. phase hybrid circuit as claimed in claim 8, wherein one or more delay elements are configured to produce phase place and differ a plurality of signals of equal phase basically each other.
14. one kind is used to produce the output delay of output signal locking loop of aiming at input signal, comprises:
Delay line is used to provide the phase signal that postpones one or more unit delays with respect to input signal;
Phase hybrid circuit, be used to produce and have by morning that described delay line provided and the blended phase signals of phase place between the phase signal late, described phase hybrid circuit comprises that current source and being used for is coupled to one or more delay elements of the shared output node of described current source selectively, wherein depends in the voltage level needed time below the threshold level that is reduced to of shared output node after described morning, phase signal was changed to effectively in one or more delay elements which is coupled to described shared output node; With
Control logic, be configured to monitor the time lag between described input and output signal, and produce one or more control signals so that select according to described time lag, and one or more delay elements are coupled to described shared output node selectively to morning and slow signal that phase hybrid circuit provided.
15. delay-locked loop circuit as claimed in claim 14, wherein said control logic also is configured to:
(a) determine whether input and output signal is aimed in the tolerance of being accepted;
(b) if not, revise one or more control signals so so that different one or more delay elements are coupled to described shared output node; And
(c) repeating step (a)-(b) is aligned in the tolerance of being accepted up to described input and output signal.
16. delay-locked loop circuit as claimed in claim 14, wherein:
Described phase hybrid circuit also comprises comparator, has the input node with the shared output node coupling of described current source; And
Described threshold level is the threshold level of described comparator.
17. delay-locked loop circuit as claimed in claim 16 wherein produces output signal on the output node of comparator.
18. a dynamic random access memory (DRAM) device comprises:
One or more memory elements; With
Delay-locked loop circuit, be used to make data output synchronous with clock signal from one or more memory elements, comprise (i) delay line, (ii) phase hybrid circuit, described phase hybrid circuit comprises current source and is used for being coupled to selectively one or more delay elements of the shared output node of described current source, wherein be changed to effectively by phase signal morning that described delay line provided after, depend in one or more delay elements which is coupled to described shared output node in the voltage level needed time below the threshold level that is reduced to of described shared output node, described delay-locked loop circuit also comprises (iii) control logic, be configured to monitor the time lag between input and output signal, and produce one or more control signals so that select by described delay line according to described time lag, and one or more delay elements are coupled to described shared output node selectively to signal morning that described phase hybrid circuit provides.
19. DRAM device as claimed in claim 18, wherein one or more delay elements comprise a plurality of transistors with different sizes.
20. DRAM device as claimed in claim 18, wherein one or more delay elements comprise a plurality of capacitors.
21. DRAM device as claimed in claim 20, wherein a plurality of capacitors belong to the type identical with the capacitor that is utilized in memory element.
22. one kind is used to produce the method that has at the morning signal and the phase signal of the intermediate phase of slow signal phase, comprises:
When morning signal be changed to when effective by one or more switches described morning signal be coupled to the control input of described one or more switches so that be current supplying path from the shared output node of current source; And
Closed one or more switches are so that be coupled to one or more delay elements selectively the shared output node of described current source, wherein according to described electric current, the needed time was depended on which closure in one or more delay elements below the voltage level of described shared output node was reduced to threshold level.
23. method as claimed in claim 22 also comprises when slow signal is changed to when effective described slow signal is coupled to the control input of described current source so that forbid described current source.
24. method as claimed in claim 22, wherein one or more delay elements comprise one or more transistors.
25. method as claimed in claim 24, wherein one or more switches comprise one or more transistors.
26. method as claimed in claim 22, wherein one or more delay elements comprise one or more capacitors.
27. method as claimed in claim 22, wherein:
Described slow signal is trailed signal early according to unit delay; And
The inhibit signal that described switch and delay element are configured to provide and early signal differs the mark of unit delay on phase place, wherein said mark depend on closed which switch.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/696,920 | 2003-10-30 | ||
| US10/696,920 US20050093594A1 (en) | 2003-10-30 | 2003-10-30 | Delay locked loop phase blender circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1846355A true CN1846355A (en) | 2006-10-11 |
Family
ID=34550227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004800249381A Pending CN1846355A (en) | 2003-10-30 | 2004-09-30 | Delayed locked loop phase blender circuit |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20050093594A1 (en) |
| EP (1) | EP1634375B1 (en) |
| JP (1) | JP2007502067A (en) |
| KR (1) | KR100817962B1 (en) |
| CN (1) | CN1846355A (en) |
| DE (1) | DE602004004533T2 (en) |
| WO (1) | WO2005048455A1 (en) |
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- 2004-09-30 CN CNA2004800249381A patent/CN1846355A/en active Pending
- 2004-09-30 WO PCT/EP2004/010941 patent/WO2005048455A1/en active IP Right Grant
- 2004-09-30 EP EP04787070A patent/EP1634375B1/en not_active Expired - Fee Related
- 2004-09-30 KR KR1020067008287A patent/KR100817962B1/en not_active IP Right Cessation
- 2004-09-30 DE DE602004004533T patent/DE602004004533T2/en not_active Expired - Fee Related
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| CN103066999A (en) * | 2011-10-20 | 2013-04-24 | 爱思开海力士有限公司 | Phase mixer and delay locked loop including same |
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| CN106502298B (en) * | 2016-12-20 | 2017-11-14 | 中国电子科技集团公司第五十八研究所 | One kind is applied to current generating circuit in low pressure phase interpolator |
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| CN107888166B (en) * | 2017-11-30 | 2021-11-05 | 北京大学深圳研究生院 | Multi-phase non-overlapping clock signal generation circuit and corresponding method |
| WO2023273748A1 (en) * | 2021-06-29 | 2023-01-05 | 澜起电子科技(昆山)有限公司 | Delay apparatus and delay control method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2005048455A1 (en) | 2005-05-26 |
| JP2007502067A (en) | 2007-02-01 |
| US20050093594A1 (en) | 2005-05-05 |
| EP1634375B1 (en) | 2007-01-24 |
| KR100817962B1 (en) | 2008-03-31 |
| KR20060067976A (en) | 2006-06-20 |
| DE602004004533D1 (en) | 2007-03-15 |
| EP1634375A1 (en) | 2006-03-15 |
| DE602004004533T2 (en) | 2007-11-15 |
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