CN1841659A - Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires - Google Patents
Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires Download PDFInfo
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- CN1841659A CN1841659A CNA2006100549495A CN200610054949A CN1841659A CN 1841659 A CN1841659 A CN 1841659A CN A2006100549495 A CNA2006100549495 A CN A2006100549495A CN 200610054949 A CN200610054949 A CN 200610054949A CN 1841659 A CN1841659 A CN 1841659A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
- H02G3/00—Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
- H02G3/00—Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
- H02G3/02—Details
- H02G3/04—Protective tubing or conduits, e.g. cable ladders or cable troughs
- H02G3/0437—Channels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
- H02G3/00—Installations of electric cables or lines or protective tubing therefor in or on buildings, equivalent structures or vehicles
- H02G3/30—Installations of cables or lines on walls, floors or ceilings
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Abstract
The present invention provides silicon nano wires, a semiconductor device including the silicon nano wires, and a method of manufacturing the silicon nano wires. The method includes: forming microgrooves having a plurality of microcavities, the microgrooves forming a regular pattern on a surface of a silicon substrate, forming a first doping layer doped with a first dopant in the silicon substrate, and forming a second doping layer doped with a second dopant between the first doping layer and a surface of the silicon substrate; forming a metal layer on the silicon substrate by depositing a material which acts as a catalyst to form nano wires on the silicon substrate; forming the catalysts by heating the metal layer so that the metal layer within the microgrooves on the surface of the silicon substrate is agglomerated; and growing the nano wires between the catalysts and the silicon substrate using a thermal process.
Description
Technical field
The present invention relates to a kind of silicon nanowires, a kind of semiconductor device of this silicon nanowires and method of making this silicon nanowires of comprising, more specifically, the present invention relates to a kind of nano wire and manufacture method thereof with p-n junction structure, wherein, the size and the distribution in the nucleation zone that is used to form nano wire when forming silicon nanowires, have accurately been controlled.
Background technology
Nano wire has obtained broad research at present, and is to use such as the next-generation technology in the multiple device of optics, transistor and memory device.The material of use in traditional nano wire comprises silicon, zinc oxide and gallium nitride, and they all are emitting semiconductors.Traditional nano wire manufacturing technology has obtained developing fully to be used to change the length and the width of nano wire.
In traditional nano luminescent device, used the nano luminescent device of quantum dot or use quantum dot.The organic EL device of use quantum dot has high radiation recombination efficient but the charge carrier injection efficiency is low.Use the GaN LED of quantum well to have higher radiation recombination efficient and charge carrier injection efficiency.Yet, because in the crystallization architectural difference of GaN LED and the general defective that Sapphire Substrate caused, thereby the production cost of GaN LED is higher, makes to be difficult to produce in batches GaN LED.Use the nano luminescent device of nano wire to have very high radiation recombination efficient and higher charge carrier injection efficiency.In addition, the manufacturing process of nano luminescent device is simple and can form the crystallization structure (crystallization structure) of nano luminescent device to have the structure that almost is similar to substrate, thereby produces the nano luminescent device easily in batches.
Figure 1A is the cross-sectional view that gas-liquid-solid (VLS) method is shown to 1D, and they are conventional methods of making nano wire.
With reference to Figure 1A, at first provide substrate 11.This substrate 11 is general silicon substrate.
With reference to Figure 1B, by the metal that apply such as Au on the top of substrate 11 form metal level 12 thereafter.
Then with reference to figure 1C, in the structure of about 500 ℃ of following heat treatment gained.As a result, the material in metal level 12 is condensed into piece, thereby forms catalyst 13.Catalyst 13 big or small irregular, promptly they have at random size.
After forming catalyst 13 as mentioned above, form nano wire 14 at catalyst 13 under as the situation in nucleation zone, shown in Fig. 1 D.By will be for example silane (compound of silicon and hydrogen) be fed to catalyst 13, luring the silicon nucleation of silane in the position that forms catalyst 13, thereby form nano wire 14.When constantly providing silane, nano wire 14 can constantly be grown from the bottom of catalyst 13, shown in Fig. 1 D.
As mentioned above, the amount such as the material gas of silane that is provided by control suitably can easily form the nano wire of Len req.Yet the growth of nano wire may be subjected to the restriction of catalyst diameter and distribution, thereby is difficult to accurately control the thickness and the distribution of nano wire.In addition, can carry out aforesaid nano wire doping by mixing supply gas and dopant material, but can not form nano wire with p-n junction structure.
Summary of the invention
The invention provides a kind of silicon nanowires with p-n junction structure, comprise the semiconductor device of this silicon nanowires and the method for making this silicon nanowires, wherein the diameter by the control silicon nanowires and distribute and make the p-n junction structure have required size and distribution.
According to an aspect of the present invention, provide a kind of method of making silicon nanowires.This method comprises: form the micro-groove (microgrooves) with a plurality of microcavitys (microcavities), the pattern of this micro-groove formation rule on surface of silicon substrate; In silicon substrate, form first doped layer of first dopant that mixes; And second doped layer that between first doped layer and surface of silicon substrate, forms second dopant that mixes; The material that plays catalyst action by deposit is forming metal level to form nano wire on silicon substrate on the silicon substrate; Form catalyst by heating this metal level, thereby make the metal level in the micro-groove on surface of silicon substrate be condensed into piece (agglomerated); And use thermal process grow nanowire between catalyst and silicon substrate.
The formation of micro-groove can comprise: thus form the micro-groove structure by the surface of silicon oxide substrate to form silicon oxide layer; And by removing silicon oxide layer exposure micro-groove structure.
The formation of metal level can comprise at least a transition metal of coating.
This metal level can comprise at least a transition metal of selecting from be made of Au, Ni, Ti or Fe one group.
The growth of nano wire can comprise that temperature and the atmosphere pressures by control execution thermal process forms nano wire between catalyst and silicon substrate.
Thermal process can be carried out under the temperature of the eutectic temperature that is higher than catalyst and silicon substrate (eutectic temperature).
This method may further include by carrying out on the side of oxidation technology at nano wire after forming nano wire and forms oxide layer.
First dopant can be a p-type dopant, and second dopant can be a n-type dopant.
First dopant can be a n-type dopant, and second dopant can be a p-type dopant.
In the growth of nano wire, can form nano wire with p-n junction structure, wherein growth first doped region along with nano wire is connected with nano wire with second doped region.
According to a further aspect in the invention, provide a kind of semiconductor device, having comprised: Semiconductor substrate has the surface that is formed with the micro-groove with a plurality of microcavitys on it; Nano wire forms in each micro-groove on substrate and extends upward from Semiconductor substrate, and has the p-n junction structure that wherein forms first doped region and second doped region; And the metallic catalyst that on an end of each nano wire, forms.
The micro-groove of can formation rule on Semiconductor substrate arranging and distributing with microcavity.
Silicon nanowires may further include the oxide layer that forms on the side of nano wire.
Silicon nanowires may further include the intermediate layer that forms between the nano wire that forms perpendicular to micro-groove.
Metallic catalyst can comprise at least a transition metal.
Metallic catalyst can comprise at least a transition metal of selecting from be made of Au, Ti, Ni or Fe one group.
Semiconductor device can comprise: do not form first electrode that forms on the zone of nano wire on its of Semiconductor substrate; And second electrode that on nano wire, forms.
According to another aspect of the invention, provide a kind of silicon nanowire structure, having comprised: the p-n junction structure that wherein forms first doped region and second doped region; And the metallic catalyst on an end of each nano wire.
Description of drawings
By being described in detail with reference to the attached drawings one exemplary embodiment of the present invention, its above-mentioned feature and advantage with other will become more obvious, wherein:
Figure 1A is the cross-sectional view that the method for traditional manufacturing nano wire is shown to 1D;
Fig. 2 is the cross-sectional view of the silicon nanowires that forms on Semiconductor substrate according to embodiments of the invention;
Fig. 3 A is that the cross-sectional view of making the method for nano wire according to embodiments of the invention is shown to 3D;
Fig. 3 E illustrates when to by the cross-sectional view of Fig. 3 A to the diameter of the nano wire of the method manufacturing shown in the 3D is further carried out oxidation technology time control nano wire;
Fig. 4 A is that the cross-sectional view of method that according to embodiments of the invention manufacturing has the nano wire of p-n junction structure is shown to 4D;
Fig. 5 comprises the cross-sectional view to the exemplary semiconductor device of the nano wire with p-n junction structure of the method manufacturing shown in the 4D by Fig. 4 A;
Fig. 6 A is to make the afm image have to the substrate surface of the similar grade micro-surface structure shown in Fig. 3 A to 6D; And
Fig. 6 E is the curve chart of surface roughness that is illustrated in the cross section of the substrate shown in Fig. 6 D.
Embodiment
Describe according to silicon nanowires of the present invention in more detail, comprise the semiconductor device of this silicon nanowires and make the method for this silicon nanowires referring now to accompanying drawing, there is shown one exemplary embodiment of the present invention.In the accompanying drawings, for clear length and the size exaggerated.
Before explanation formation has the silicon nanowires of p-n junction structure, the structure and the manufacture method thereof of nano wire will be described.Fig. 2 is the cross-sectional view of the nano wire 22 that forms on Semiconductor substrate according to embodiments of the invention.With reference to figure 2, in the surface of substrate 21, form the micro-groove that comprises a plurality of microcavitys (microcavities).In micro-groove, form vertically grown nano wire 22, and on an end of each nano wire 22, form catalyst 23.The micro-groove that forms in the surface of substrate 21 is formed up to required width, and according to the size of micro-groove and the size and the distribution of the decision nano wire 22 of formation on substrate 21 that distributes.The method that forms the micro-groove that comprises microcavity in the surface of substrate 21 will together be described with the method for making nano wire 22 after a while.
Fig. 3 A is that the cross-sectional view of making the method for nano wire according to embodiments of the invention is shown to 3D.
With reference to figure 3A, at first, be provided at the substrate 31 that has micro-groove in its surface.This micro-groove with width d is formed in the substrate 31.Formation as described below has the micro-groove of microcavity.
At first, on the surface of silicon substrate 31, carry out dry oxidation technology, wherein will form have microcavity micro-groove on the surface of silicon substrate 31, to form silicon oxide layer (SiO
2) (not shown).By at oxygen (O
2) and chlorine (Cl
2) dry oxidation technology under the atmosphere carries out oxidation technology, and can also add nitrogen (N
2) with the pressure in the control process chamber.Long duration under about 1150 ℃ high temperature is carried out dry oxidation technology (that is a few to tens of hour).As selection, can utilize wet oxidation process to form silicon oxide layer.Pressure in the process chamber is determined by oxygen and nitrogen, and can add chlorine with the ratio littler than oxygen.
Chlorine improves oxidation rate during dry oxidation technology.That is, chlorine promotes at silicon oxide layer and as the reaction or the diffusion of the oxidant at the interface between the substrate 31 of silicon layer.In addition, the sodium in chlorine capture and neutralization (neutralizes) oxide layer, and absorption (getter) metal impurities and the stacking fault (stacking faults) that prevents from silicon layer.Because the accumulation of gaseous oxidation product, the excess chlorine that surpasses threshold concentration causes forming extra phase (phases) between oxide layer and the silicon layer, thereby makes interface (SiO between oxide layer and the silicon layer
2/ Si) more coarse.
Because chlorine causes the silicon oxide layer of substrate 31 and the interface between the silicon layer more coarse, form micro-groove, thereby high-quality silicon oxide layer can be formed.When by etch process removing substrate 31 lip-deep silicon oxide layers, form as shown in Figure 3A the micro-groove structure that comprise microcavity thereafter.
6A is the afm image that injects the substrate surface of the different chlorine of measuring to 6D.Fig. 6 A shows respectively to 6D and inject 0,80,160 and the chlorine of 240sccm in process chamber.Along with the increase of injecting amount of chlorine, it is more coarse that the surface becomes, thereby increase the width d of micro-groove.
Fig. 6 E illustrates to inject the 240sccm chlorine curve chart of the surface roughness of substrate cross section afterwards.Shown in center, left side and the distortion of right side cross section, but obtained having the micro-groove surface of the decorative pattern (illumination) of the groove of rule and several nm as can be seen.That is, the micro-groove that forms with the interval of several nm can have micro-cavity structure.
As mentioned above, in substrate 31, after formation has the micro-groove of regularly arranged microcavity, on the top of substrate 31, form metal level 32, shown in Fig. 3 B.This metal level 32 is made by the material that can play catalyst action, will grown nano wire to form.This material can be the transition metal such as Au, Ni, Ti or Fe.This metal level 32 is formed the thickness of several nm thinly, and depend on the shape on the surface of the substrate 31 that forms for 32 times at metal level, have the micro-groove that comprises more regularly arranged microcavity, as substrate 31.
Then, with reference to figure 3C, heating of metal layer 32 is to cause the cohesion of metal level 32.If with metal level 32 be heated to about 500 ℃ just enough, as in the prior art.Because heating, the material of formation metal level 32 condense upon in the substrate 31 lip-deep micro-grooves and form the catalyst 33 of nano-scale.In other words, the micro-groove that beginning forms in the surface of substrate 31 is to be used for the formed position of control catalyst 33 and the size of catalyst 33, forms this catalyst 33 by cohesion metal level 32.As a result, the size that the zone that forms catalyst 33 is limited by micro-groove and the size by micro-groove can control catalyst 33.
Thereafter, with reference to figure 3D, nano wire 34 is formed at the place that catalyst 33 forms, and this catalyst 33 plays the effect in nucleation zone.Be higher than under the eutectic temperature temperature of (being about 363 ℃ under the situation at Au), luring the Si nucleation in the micro-groove of the substrate 31 that forms catalyst 33 into, forming nano wire 34 thus.By control temperature, atmosphere pressures and the time, nano wire 34 can grow into required length.For example, temperature range can be at 500 to 1100 ℃, and pressure limit can be at 100Torr to standard atmospheric pressure.
Therefore, can control the thickness of nano wire 34 by the micro-groove that in the surface of substrate 31, forms required size, and nano wire can be with width growth uniformly with microcavity.
With reference to figure 3E, can additionally carry out the width of oxidation technology with control nano wire 34.That is, when after forming nano wire 34, carrying out oxidation technology, quickened the formation of silicon oxide layer 35, especially on the side of nano wire 34, thereby made the thickness of nano wire 34 can be controlled.
Describe a kind of method that according to embodiment of the invention manufacturing comprises the semiconductor device of silicon nanowires referring now to Fig. 4 A to 4D, this method has been used the method to the manufacturing nano wire of 3E description with reference to figure 3A.
With reference to figure 4A, first doped layer 41 is formed on the substrate, is formed with the micro-groove that comprises microcavity on this substrate, and second doped layer 42 is formed on the top of first doped layer 41 then.If first doped layer, 41 doping p-type dopants, second doped layer, 42 Doped n-type dopant then, vice versa.Thereby,, form first and second doped layers 41 and 42 by p-type and n-type dopant are injected in the diverse location of the substrate that wherein forms micro-groove.
Thereafter, with reference to figure 4B, metal level 43 is formed on second doped layer 42.This metal level 43 can be formed with the material that forms nano wire by playing catalyst action.In more detail, this material can be the transition metal such as Au, Ni, Ti or Fe.
Then,, heat of cohesion and the assembly of this metal level 42, thereby in having the micro-groove of microcavity, form catalyst 44 to impel metal level 42 with reference to figure 4C.This catalyst 44 is formed in the micro-groove, thereby the size of catalyst 44 and the width and the formation zone that distribute and be limited to micro-groove.
Thereafter, with reference to figure 4D, by luring the element silicon nucleation into and catalyst 44 is heated to above the temperature of eutectic temperature that the place that forms catalyst 44 in micro-groove forms nano wire.For example, can in 500 to 1100 ℃ temperature range, carry out this technology.The nano wire region of the dopant distribution of second doped layer 42 below the catalyst 44 that nano wire will form, with form second nano wire 42 '.Then, if nano wire constantly grow, just the dopant of first doped layer 41 is injected into second nano wire 42 ' the bottom, thereby form first nano wire 41 '.As a result, in nano wire, form the p-n junction structure.
Fig. 5 is the cross-sectional view of exemplary semiconductor device, and this semiconductor device comprises the nano wire with p-n junction structure to the method manufacturing shown in the 4D by Fig. 4 A.
With reference to figure 5, between nano wire, form photoresist layer 55 with the p-n junction structure shown in Fig. 4 D by the deposit photoresist.Formation to the p-n junction nano wire shown in the 4D, forms first electrode 56 as Fig. 4 A on another part of substrate 51 on the part of substrate 51, and forms second electrode 57 on the top of nano wire.This structure can be used in utilizing the nano luminescent device of nano wire, and has the advantage of very high radiation recombination efficient and higher charge carrier injection efficiency, as described in the description of above-mentioned prior art.
According to the present invention, be formed with therein on the substrate of micro-groove and make nano wire with microcavity, by the size and the distribution of control micro-groove, can make the width of the nano wire that will form and distribute to be limited to the width and the distribution of micro-groove.The p-n junction diode of nanometer size can easily be formed in the nano wire by the method for using nano wire constructed in accordance, this p-n junction diode can be used as nano luminescent device or electronic device, and this electronic device has very high radiation recombination efficient and the higher charge carrier injection efficiency of p-n junction structure can be provided.
Although the present invention has been carried out special demonstration and explanation with reference to one exemplary embodiment of the present invention, but should be understood that, those of ordinary skill in the art can be under the situation of the spirit and scope of the present invention that do not deviate from claim definition, and wherein embodiment is made variation on various forms and the details.
Claims (20)
1. method of making silicon nanowires, described method comprises:
Formation has the micro-groove of a plurality of microcavitys, the pattern of described micro-groove formation rule on surface of silicon substrate, in described silicon substrate, form first doped layer of first dopant that mixes, and between described first doped layer and described surface of silicon substrate, form second doped layer of second dopant that mixes;
Play catalyst action on described silicon substrate, to form metal level by deposit at the material that forms nano wire on the described silicon substrate;
Form described catalyst by heating described metal level, thereby make the interior described metal level cohesion of described micro-groove on the described surface of silicon substrate; And
Use the thermal process described nano wire of between described catalyst and described silicon substrate, growing.
2. the method for claim 1, the formation of wherein said micro-groove comprises:
By the described surface of silicon substrate of oxidation forming silicon oxide layer, thereby form the micro-groove structure; And
Expose described micro-groove structure by removing described silicon oxide layer.
3. the method for claim 1 wherein forms described metal level and comprises at least a transition metal of coating.
4. method as claimed in claim 3, wherein said metal level comprise at least a transition metal of selecting from the group of being made of Au, Ni, Ti or Fe.
5. the method for claim 1, the described nano wire of wherein growing comprise that temperature and the atmosphere pressures of carrying out described thermal process by control form described nano wire between described catalyst and described silicon substrate.
6. the method for claim 1 is wherein carried out described thermal process under the temperature of the eutectic temperature that is higher than described catalyst and described silicon substrate.
7. the method for claim 1 further comprises by carrying out on the side of oxidation technology at described nano wire after forming described nano wire forming oxide layer.
8. the method for claim 1, wherein said first dopant is a p-type dopant, and described second dopant is a n-type dopant.
9. the method for claim 1, wherein said first dopant is a n-type dopant, and described second dopant is a p-type dopant.
10. the method for claim 1, wherein in the growth of described nano wire, described nano wire forms has the p-n junction structure, and the growth along with described nano wire is connected with described nano wire wherein said first doped region with described second doped region.
11. a silicon nanowires comprises:
The p-n junction structure is formed with first doped region and second doped region therein; And
Metallic catalyst on an end of each described nano wire.
12. silicon nanowires as claimed in claim 11, wherein said metallic catalyst are at least a of transition metal.
13. silicon nanowires as claimed in claim 12, wherein said metallic catalyst are select from the group of being made up of Au, Ni, Ti and Fe at least a.
14. a semiconductor device comprises:
Semiconductor substrate has the meticulous regular texture that comprises a plurality of microcavitys on the part surface of described Semiconductor substrate;
Nano wire forms in each described micro-groove and extends upward from described Semiconductor substrate, and has the p-n junction structure that wherein is formed with first doped region and second doped region; And
The metallic catalyst that on the end of each described nano wire, forms.
15. semiconductor device as claimed in claim 14, wherein said micro-groove with microcavity is to arrange regularly and distribution is formed on the described Semiconductor substrate.
16. semiconductor device as claimed in claim 14 further is included in the oxide layer that forms on the side of described nano wire.
17. semiconductor device as claimed in claim 14 further is included in the intermediate layer that forms between the described nano wire that forms perpendicular to described micro-groove.
18. semiconductor device as claimed in claim 14, wherein said metallic catalyst comprises at least a transition metal.
19. semiconductor device as claimed in claim 18, wherein said metallic catalyst comprise at least a transition metal of selecting from the group of being made of Au, Ti, Ni or Fe.
20. semiconductor device as claimed in claim 14 further comprises:
First electrode is formed on its of described Semiconductor substrate and does not form on the zone of described nano wire; And
Second electrode that on described nano wire, forms.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20050016184 | 2005-02-25 | ||
| KR16184/05 | 2005-02-25 | ||
| KR9821/06 | 2006-02-01 |
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| Publication Number | Publication Date |
|---|---|
| CN1841659A true CN1841659A (en) | 2006-10-04 |
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ID=37030603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CNA2006100549495A Pending CN1841659A (en) | 2005-02-25 | 2006-02-27 | Silicon nano wires, semiconductor device including the same, and method of manufacturing the silicon nano wires |
Country Status (2)
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| KR (1) | KR100723418B1 (en) |
| CN (1) | CN1841659A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101643196A (en) * | 2008-08-05 | 2010-02-10 | 三星电子株式会社 | Nanowire comprising silicon rich oxide and method for producing the same |
| CN107230679A (en) * | 2016-03-23 | 2017-10-03 | 格罗方德半导体公司 | High density memory cells structure |
| CN107799387A (en) * | 2016-09-06 | 2018-03-13 | 中国科学院上海微系统与信息技术研究所 | A kind of method and structure that silicon nanowires is prepared on the polysilicon layer of doping |
| CN111162141A (en) * | 2019-12-20 | 2020-05-15 | 燕山大学 | Preparation method of multi-junction nanowire solar cell |
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| KR100799570B1 (en) * | 2006-06-15 | 2008-01-31 | 한국전자통신연구원 | Fabrication method of silicon nanotube using doughnut type catalytic metal layer |
| KR100822745B1 (en) * | 2006-12-05 | 2008-04-17 | 한양대학교 산학협력단 | Semiconductor nanowire by porous nanotemplate, a method for manufacturing thereof, and a semiconductor device comprising the same |
| KR100960391B1 (en) * | 2007-12-26 | 2010-05-28 | 포항공과대학교 산학협력단 | Method for manufacturing nanodevice and device for manufacturing the same |
| KR101132268B1 (en) * | 2010-07-27 | 2012-04-02 | 재단법인대구경북과학기술원 | Flxible photovoltaic device and fabrication method thereof |
| KR101938010B1 (en) * | 2012-11-22 | 2019-01-14 | 전북대학교산학협력단 | Manufacturing method of diode |
| KR102395778B1 (en) | 2015-09-10 | 2022-05-09 | 삼성전자주식회사 | Method of forming nanostructure, method of manufacturing semiconductor device using the same and semiconductor device including nanostructure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101008294B1 (en) * | 2001-03-30 | 2011-01-13 | 더 리전트 오브 더 유니버시티 오브 캘리포니아 | Methods of fabricating nanostructures and nanowires and devices fabricated therefrom |
| KR100388433B1 (en) * | 2001-10-15 | 2003-06-25 | 한국과학기술연구원 | Fabricating method of metallic nanowires |
| JP2004319675A (en) | 2003-04-15 | 2004-11-11 | Matsushita Electric Ind Co Ltd | Carbon nanotube inductor and its manufacturing method |
| JP2004359478A (en) | 2003-06-02 | 2004-12-24 | Univ Waseda | Method for controlling form/position of fibrous carbon, fibrous carbon element position-controlled using the method, and device using the element |
-
2006
- 2006-02-01 KR KR1020060009821A patent/KR100723418B1/en not_active IP Right Cessation
- 2006-02-27 CN CNA2006100549495A patent/CN1841659A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101643196A (en) * | 2008-08-05 | 2010-02-10 | 三星电子株式会社 | Nanowire comprising silicon rich oxide and method for producing the same |
| CN107230679A (en) * | 2016-03-23 | 2017-10-03 | 格罗方德半导体公司 | High density memory cells structure |
| CN107799387A (en) * | 2016-09-06 | 2018-03-13 | 中国科学院上海微系统与信息技术研究所 | A kind of method and structure that silicon nanowires is prepared on the polysilicon layer of doping |
| CN111162141A (en) * | 2019-12-20 | 2020-05-15 | 燕山大学 | Preparation method of multi-junction nanowire solar cell |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060094862A (en) | 2006-08-30 |
| KR100723418B1 (en) | 2007-05-30 |
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