KR20060094862A - Silicon nano wire, semicondutor device comprising silicon nano wire and manufacturing method of silicon nano wire - Google Patents

Abstract

The present invention relates to a silicon nanowire, a semiconductor device comprising silicon nanowires and a method for producing silicon nanowires. (A) forming a horseshoe bend comprising a plurality of microcavity forms regularly formed on a silicon substrate surface; (B) depositing a catalytic material for forming nanowires on the substrate to form a metal layer; (C) heating the metal layer to agglomerate the metal layer in fine curvature of the substrate surface to form a catalyst; And (d) growing nanowires between the catalyst and the substrate. The method provides a silicon nanowire manufacturing method including a silicon nanowire and a silicon nanowire manufactured thereby.

Description

Silicon nano wire, semicondutor device comprising silicon nano wire and manufacturing method of silicon nano wire

1A to 1D are views illustrating a nanowire manufacturing method according to the prior art.

2 is a view showing the structure of the silicon nanowires formed on a semiconductor substrate according to the present invention.

3a to 3d is a view showing a nanowire manufacturing method according to the present invention.

3E is a view showing an example of further performing an oxidation process for adjusting the diameter of the nanowires manufactured in FIGS. 3A to 3D.

Figures 4a to 4d is a view showing a nanowire manufacturing method comprising a p-n junction structure according to the present invention.

FIG. 5 is a diagram illustrating a structure of a semiconductor device including nanowires having a p-n junction structure manufactured by FIGS. 4A to 4D.

6A to 6D are AFM images measured on the surface of a substrate with a fine surface structure adjusted as shown in FIG. 3A.

FIG. 6E is a graph measuring surface roughness of the specimen shown in FIG. 6D.

<Description of Symbols for Main Parts of Drawings>

11, 21, 31, 51 ... substrate 12, 32, 43 ... metal layer

13, 23, 33, 44, 54 ... Catalyst 14, 22, 34, ... Nanowire

35 Oxide layer 41 First doping layer

42 ... doping layer 41 ', 52 ... type 1 wire

42 ', 53 ... Type 2 Wire 55 ... Interlayer

56 ... First electrode 57 ... Second electrode

The present invention relates to a silicon nanowire, a semiconductor device comprising a silicon nanowire and a method of manufacturing the same. More particularly, the size and distribution of nucleation regions for forming nanowires when forming silicon nanowires The present invention relates to a nanowire and a method for manufacturing the same, including a pn junction structure with precise control.

Nanowires are currently being widely studied in the field of nanotechnology, and are the next generation technologies widely applied to various fields such as optical devices such as lasers, transistors, and memory devices. Current materials used in nanowires include silicon, zinc oxide and gallium nitride, which are light emitting semiconductors. Current nanowire manufacturing process technology has advanced to the extent that nanowire length and width can be controlled.

In the case of conventional nano light emitting devices, nano light emitting devices using quantum dots or quantum dots have been used. The organic EL using quantum dots has a very high radial recombination efficiency but a very low carrier injection efficiency. In the case of GaN LEDs using quantum wells, radiative recombination efficiency and carrier injection efficiency are relatively high, but defects due to differences in crystal structure from conventional sapphire substrates are very difficult to produce in large areas, and manufacturing costs are relatively expensive. There are disadvantages. However, in the case of a nano-light emitting device using nanowires, the radial recombination efficiency is very high and the carrier injection efficiency is relatively high. In addition, the manufacturing process is simple and can be formed to have almost the same crystal structure as the substrate, there is an advantage that it is easy to form a large area.

1A to 1D are diagrams illustrating a Vapor-Liquid-Solid (VLS) method, which is a method of manufacturing nanowires according to the prior art.

Referring to FIG. 1A, first, a substrate 11 is prepared. The substrate 11 uses a widely used silicon substrate.

Then, referring to FIG. 1B, a metal such as Au is coated on the substrate 11 to form the metal layer 12.

Next, referring to FIG. 1C, when the heat treatment process is performed at about 500 ° C., the material of the metal layer 12 is agglomerated to form the catalyst 13. The catalysts 13 formed at this time are not constant in size, but have random sizes.

After the catalyst 13 is formed as described above, the nanowire 14 is formed with the catalyst 13 in the nucleation position as shown in FIG. 1D. Herein, the nanowires 14 are formed by supplying silane (SiH ₄ ), which is a silicon hydrogen compound, to the catalyst 13 to induce nucleation of Si element of silane at the catalyst 13 at a process temperature. By continuously supplying the silane, nanowires can continuously grow under the catalyst 13 as shown in FIG. 1D.

As described above, the nanowires can be easily formed in a desired length by appropriately adjusting the supply amount of a source gas such as silane. However, since the nanowires can be grown limited to the diameter of the catalyst 13 and its distribution, it is difficult to control the exact thickness and its distribution. In addition, such a nanowire doping is possible by adding a doping material by mixing with a feed gas, but there is a problem that cannot be formed by a p-n junction structure.

The present invention is to solve the problems of the prior art, including the silicon nanowires, silicon nanowires including a pn junction structure that is controlled by the growth of the diameter and distribution of the silicon nanowires to control the precise size and distribution as a result An object of the present invention is to provide a semiconductor device and a silicon nanowire manufacturing method.

In the present invention, to achieve the above object,

 (A) forming a fine bend comprising a plurality of microcavity forms regularly formed on the surface of the silicon substrate, and between the first doped region and the first doped region and the substrate surface doped with a first type dopant in the substrate; Forming a second doped region doped with a second type dopant in the second doped region;

(B) depositing a catalytic material for forming nanowires on the substrate to form a metal layer;

(C) heating the metal layer to agglomerate the metal layer in fine curvature of the substrate surface to form a catalyst; And

(D) growing a nanowire between the catalyst and the substrate by a heat treatment; provides a method for producing silicon nanowire comprising a.

In the present invention, the (a) step,

Oxidizing the surface of the substrate to form a silicon oxide layer to form a fine curved structure; And

And removing the silicon oxide layer to expose the fine curved structure.

In the present invention, the metal layer of the step (b) is characterized in that formed by applying at least one of the transition metal.

In the present invention, the metal layer is characterized in that it comprises at least one material of Au, Ni, Ti or Fe.

In the present invention, the step (d) is characterized in that to form a nanowire between the catalyst and the substrate by adjusting the process temperature and the atmospheric pressure.

In the present invention, the heat treatment of the step (d) is characterized in that it is carried out at a temperature range above the eutectic temperature of the catalyst and the substrate.

In the present invention, after the nanowire is formed, the step of performing an oxidation process further comprises the step of forming an oxide layer on the side of the nanowire.

In the present invention, the first type dopant is a p-type dopant, and the second dopant is an n-type dopant.

In the present invention, the first type dopant is an n-type dopant, and the second type dopant is a p-type dopant.

In the present invention, the step (d) is,

While growing the nanowires, the nanowires are formed in a p-n junction structure in which a first type doping region and a second type doping region are bonded to the nanowires.

In the present invention,

A semiconductor substrate having a fine curved structure including a plurality of microcavity shapes in a portion of the surface;

A nanowire formed above the substrate in the fine curved structure, wherein a first doped region and a second doped region are formed to have a p-n junction structure;

It provides a semiconductor device comprising; a metal catalyst formed at the end of the nanowires.

In the present invention, the micro-curve including the microcavity shape is formed with a regular arrangement and distribution on the surface of the substrate.

In the present invention, the oxide layer formed on the side of the nanowire; characterized in that it further comprises.

In the present invention, it characterized in that it further comprises a photoresist layer formed between the nanowires formed in the vertical direction from each of the fine curved structure.

In the present invention, the metal catalyst includes at least one material of a transition metal, and specifically, Au, Ni, Ti, or Fe may be used.

In the present invention, the semiconductor substrate includes a first electrode formed in a region where the nanowires are not formed and a second electrode formed on the nanowire.

In the present invention,

The present invention provides a nanowire having a p-n junction structure composed of a first doped region and a second doped region and having a metal catalyst formed at an end thereof.

Hereinafter, a semiconductor device including a silicon nanowire, a silicon nanowire, and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. It should be noted, however, that the length and size of the drawings are exaggerated for the purpose of explanation of the invention.

First, in order to form a silicon nanowire including a p-n junction structure, the structure of the nanowire with a shear system and a method of manufacturing the same will be described. 2 is a view showing the structure of a nanowire formed on a semiconductor substrate according to the present invention. Referring to FIG. 2, fine bends including a plurality of micro cavities are formed on the surface of the substrate 21. Each fine bend includes nanowires 22 grown in a vertical direction, and a catalyst 23 is formed at an end of each nanowire 22. Here, the width of the fine bend formed on the surface of the substrate 31 is formed to a desired size, the size and distribution of the nanowire 22 formed on the substrate 21 is determined according to the size and distribution of the fine bend. The method of forming the fine bend including the microcavity shape on the surface of the substrate 31 will be described in detail in the manufacturing process to be described later.

3a to 3d is a view showing a nanowire manufacturing method according to the present invention.

Referring to FIG. 3A, first, a substrate 31 including fine bends including a plurality of microcavity shapes is provided on a surface thereof. The substrate 31 is formed with a plurality of fine bends having a width of d. Referring to the formation process of the fine bend including the micro-cavity form as follows.

First, a silicon oxide layer (SiO ₂ ) (not shown) is formed on a surface of a silicon substrate by performing a dry oxidation process on a surface on which microcavities in the form of microcavities of the silicon substrate 31 are to be formed. Here, the oxidation process is performed by a dry oxidation process under an oxygen (O ₂ ) and chlorine (Cl ₂ ) gas atmosphere, and nitrogen (N ₂ ) may be further added to adjust the pressure in the process chamber. The process temperature at this time is about 1150 degreeC high temperature, and is performed for a long time (several to several tens of hours). It may also be made by a wet oxidation process. The pressure in the process chamber is determined by oxygen (O ₂ ) and nitrogen (N ₂ ), and chlorine (Cl ₂ ) gas may be included in a smaller proportion than oxygen (O ₂ ) gas.

Here, chlorine (Cl ₂ ) gas increases the oxidation rate during the dry oxidation process. In other words, the chlorine gas promotes the reaction or diffusion of oxidants at the interface between the silicon oxide layer and the silicon layer corresponding to the substrate 31. In addition, the chlorine gas traps and neutralizes the contamination of sodium in the oxide layer and removes metallic impurities and stacking faults from the silicon layer. The presence of chlorine above the threshold concentration leads to the formation of additional phases between the oxide layer and the silicon layer due to the accumulation of gaseous oxidation products. This makes the interface (SiO ₂ / Si) between the oxide layer and the silicon layer rougher.

Therefore, the chlorine as described above allows the interface between the silicon oxide layer and the silicon layer of the substrate 31 to be formed more roughly to obtain more reliable fine defect bending, and to form a high quality silicon oxide layer. Thereafter, when the silicon oxide layer on the surface of the substrate 31 is removed by an etching process, as shown in FIG. 3A, a fine defect bending structure including a microcavity shape may be obtained.

6a to 6d are AFM images of the surface according to the amount of chlorine gas introduced. 6A to 6D show that chlorine is injected into the process chamber at a flow rate of 0sccm, 80sccm, 160sccm and 240sccm, respectively, and the surface roughness increases as the amount of chlorine is increased so that the width (d) of the fine bend gradually increases. Able to know.

6E is a graph showing the surface roughness of the cross section after introducing chlorine gas at a flow rate of 240 sccm. Although the center region and the left and right sides are distorted, it can be seen that a fine curved surface having a roughness of several nm with relatively regular spacing is obtained. That is, it can be seen that the fine curvatures with the interval of several nm have the microcavity structure with the interval of several hundred nm.

As described above, a fine bend having a microcavity shape having a regular arrangement on the substrate 31 is formed, and then a metal layer 32 is formed on the substrate 31 as shown in FIG. 3B. In this case, the metal layer 32 may use a material that may serve as a catalyst for forming nanowires to be grown later, and may use transition metals such as Au, Ni, Ti, and Fe. At this time, the metal layer 32 is formed thin in a nm size, and according to the surface shape of the substrate 31 below the metal layer 32 is also formed in a fine curved form including a micro cavity having a relatively regular arrangement.

Next, as shown in FIG. 3C, heat is applied to the metal layer 32 to induce agglomeration of the metal layer 32. At this time, it is sufficient to maintain the heating temperature of about 500 degrees Celsius as described in the prior art, and by heat treatment, the material of the metal layer 32 is agglomerated in fine bends on the surface of the substrate 31 to form a nano-sized catalyst (33 ) To form a structure. That is, the fine bending that was initially formed on the surface of the substrate 31 is used to control the position and size of the catalyst 33 formed by agglomerating the material layer 32, thereby forming a region of the catalyst 33. The size of the catalyst 33 may be controlled according to the size of the fine bend.

Next, as shown in FIG. 3D, the nanowires 34 are formed with the catalyst 33 in the nucleation position. Here, the nanowires 34 catalyze the Si element of the substrate 31 at a temperature higher than the eutectic temperature (about 363 degrees Celsius in the case of Au) to the catalyst 33 formed in the fine bend of the substrate 31. Induced by nucleation at the) position. At this time, by appropriately adjusting the temperature, atmospheric pressure and time it is possible to grow the length of the nanowire 34 by the desired length. For example, the temperature range is 500 degrees Celsius to 1100 degrees Celsius, and the pressure range is adjustable from 100 Torr to atmospheric pressure.

As a result, by forming microcavities in the form of microcavities having a desired size on the surface of the substrate 31, the thickness of the nanowires 34 can be controlled and can be grown to a relatively homogeneous width.

3E, in order to control the width of the nanowires 34, an oxidation process may be additionally performed. That is, when the nanowire 34 is formed and then subjected to an oxidation process, in particular, the formation of the silicon oxide layer 35 on the side of the nanowire 34 may be promoted to adjust the thickness of the nanowire 34.

Next, a manufacturing process of a semiconductor device including a silicon nanowire according to the present invention applying the nanowire manufacturing process described with reference to FIGS. 3A to 3E will be described with reference to FIGS. 4A to 4D.

Referring to FIG. 4A, the first doped layer 41 is first formed on the substrate formed on the surface of the fine bending including the microcavity shape, and the second doped layer 42 is formed thereon. Here, if the first type doping layer 41 is a region doped with a p-type dopant, the second type doping layer 42 means a region doped with an n-type dopant, on the contrary, the first doping layer 41 If the region is doped with the n-type dopant, the second doped layer 42 means a region doped with the p-type dopant. As a result, it can be seen that the first type doping layer 41 and the second type doping layer 42 are formed by injecting p-type and n-type dopants into different positions on the substrate having fine bends.

Next, as shown in FIG. 4B, the metal layer 43 is coated on the second type doped layer 42. Here, the metal layer 43 is preferably a catalyst material for promoting the formation of nanowires, specifically, a transition metal such as Au, Ni, Ti or Fe may be used.

Next, referring to FIG. 4C, heat treatment is performed at about 500 degrees Celsius to promote agglomeration and agglomeration of the metal layer 43 to form the catalyst 44 in the fine bend including the microcavity form. At this time, the catalyst 44 is formed in the fine bends and the size and distribution of the catalysts 44 are limited by the width of the fine bends and the formation region thereof.

Next, referring to FIG. 4D, the Si elements of the substrate 41 induce nucleation at the catalyst 44 position by heating the catalyst 44 formed in the fine bend to a temperature higher than the eutectic temperature. Form a wire. For example, the temperature ranges from 900 degrees Celsius to 1100 degrees Celsius. At this time, the dopant of the second doped layer 42 is distributed in the nanowire region formed under the tip 44 medium to form the second type nanowire 42 ′. When the nanowire is continuously grown, the dopant of the first doped layer 41 is injected into the lower region of the second type nanowire 42 ', thereby forming the first type nanowire 41'. As a result, p-n junctions are formed on the nanowires themselves.

FIG. 5 is a diagram illustrating an embodiment of a semiconductor device including a nanowire having a p-n junction formed by the above-described processes of FIGS. 4A to 4D.

Referring to FIG. 5, the photoresist layer 55 is formed by applying, for example, a photoresist as an intermediate layer to the nanowire having the p-n junction shown in FIG. 4D. A pn junction nanowire as shown in FIGS. 4A to 4D is formed on a portion of the substrate 51, and a first electrode 56 is formed on another portion of the substrate 51. 57) can be seen. The device can be driven by applying a DC power supply through the first electrode 56 and the second electrode 57, and the electrons and holes injected through each of them are recombined at the p-n junction and light is generated. Such a form may be used as a nano light emitting device using nanowires, and as described in the related art, the radial recombination efficiency is very high and the carrier injection efficiency is relatively high.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

According to the present invention, by manufacturing a nanowire on a substrate having a fine bend including a microcavity shape whose size and distribution is controlled, by limiting the width and distribution of the formed nanowire to the shape and distribution of the fine bend There is an advantage to manufacture. It is possible to provide a nano-sized pn junction diode that can be used as a nano light emitting device or an electronic device having a very high radial recombination efficiency and a relatively high carrier injection efficiency by forming a pn junction structure in a nanowire by applying this. There is this

Claims (20)

(A) forming a fine bend comprising a plurality of microcavity forms regularly formed on the surface of the silicon substrate, and between the first doped region and the first doped region and the substrate surface doped with a first type dopant in the substrate; Forming a second doped region doped with a second type dopant in the second doped region; (B) depositing a catalytic material for forming nanowires on the substrate to form a metal layer; (C) heating the metal layer to agglomerate the metal layer in fine curvature of the substrate surface to form a catalyst; And (D) growing a nanowire between the catalyst and the substrate by a heat treatment; silicon nanowire manufacturing method comprising a. The method of claim 1, Step (a), Oxidizing the surface of the substrate to form a silicon oxide layer to form a fine curved structure; And Removing the silicon oxide layer to expose the fine curved structure. The method of claim 1, The metal layer of the step (b) is silicon nanowire manufacturing method, characterized in that formed by applying at least one of the transition metal. The method of claim 3, wherein The metal layer is a silicon nano wire manufacturing method, characterized in that it comprises at least one of Au, Ni, Ti or Fe. The method of claim 1, The step (d) is a method for producing silicon nanowires, characterized in that to form a nanowire between the catalyst and the substrate by adjusting the process temperature and the atmospheric pressure. The method of claim 1, The heat treatment of the step (d) is a silicon nanowire manufacturing method, characterized in that carried out at a temperature range above the eutectic temperature of the catalyst and the substrate. The method of claim 1, And forming an oxide layer on the side of the nanowire by performing an oxidation process after the nanowire is formed. The method of claim 1, Wherein the first type dopant is a p-type dopant and the second dopant is an n-type dopant. The method of claim 1, Wherein said first type dopant is an n-type dopant and said second type dopant is a p-type dopant. The method of claim 1, The (d) step is, While growing the nanowires, silicon nanowires manufacturing method characterized in that the nanowires are formed in a p-n junction structure in which the first type doped region and the second type doped region are bonded. In silicon nanowires, A silicon nanowire having a p-n junction structure consisting of a first doped region and a second doped region, wherein a metal catalyst is formed at an end thereof. The method of claim 11, The metal catalyst is a silicon nano wire, characterized in that it comprises a material of at least one of transition metals. The method of claim 12, The metal catalyst is a silicon nano wire, characterized in that it comprises at least one material of Au, Ni, Ti or Fe. A semiconductor substrate having a fine curved structure including a plurality of microcavity shapes in a portion of the surface; A nanowire formed above the substrate in the fine curved structure, wherein a first doped region and a second doped region are formed to have a p-n junction structure; And And a metal catalyst formed at an end of the nanowire. The method of claim 14, The micro-curve including the microcavity shape is formed with a regular arrangement and distribution on the surface of the substrate The method of claim 14, And an oxide layer formed on the side of the nanowires. The method of claim 14, And an intermediate layer formed between the nanowires formed in the vertical direction from each of the fine curved structures. The method of claim 14, The metal catalyst is a semiconductor device, characterized in that it comprises at least one material of the transition metal. The method of claim 18, The metal catalyst is a semiconductor device, characterized in that it comprises at least one material of Au, Ni, Ti or Fe. The method of claim 14, And a second electrode formed on the nanowire, wherein the first electrode is formed in a region where the nanowires are not formed.

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