CN1833269A - Circuit for signal amplification and use of the same in active matrix devices - Google Patents

Abstract

An amplification circuit comprises a capacitor arrangement (42) and a switching arrangement. The capacitor arrangement has a first capacitor (C2) which has a voltage-dependent capacitance and a second capacitor (C1) (which may also be voltage-dependent). The circuit is operable in two modes, a first mode in which the input voltage is provided to one terminal of at least the first capacitor, and a second mode in which the switching arrangement causes charge to be redistributed between the first and second capacitors such that the voltage across the first capacitor changes to reduce the capacitance of the first capacitor, the output voltage being dependent on the resulting voltage across the first capacitor. The invention uses a voltage controlled capacitance in combination with charge sharing between capacitors, which has the result of providing a voltage amplification characteristic. This arrangement can thus be used for the amplification of an analogue voltage, or the boosting of a fixed level (i.e. digital voltage). Thus, the circuit of the invention can be used for level shifting or amplification, for example for use in the pixels of an active matrix array device.

Description

Be used for circuit that signal amplifies and in the application of active matrix apparatus

Technical field

The present invention relates to amplify or booster circuit, particularly utilize the amplification or the booster circuit of capacitive couplings effect.Foregoing circuit is used in particular in the active matrix array device.

Background technology

Active matrix array device has obtained using widely in multiple application.For example, active matrix array device equipment has been used as sensor, storer and display device, for example active matrix array liquid crystal (LC) display device, perhaps active matrix organic light-emitting diode (OLED) display.

In general, active matrix array device typically comprises a plurality of data conductor (for example row), and above-mentioned data conductor is aligned to a plurality of address conductors (for example going) and intersects.The two is connected matrix array elements at each place, point of crossing and address conductors and data conductor of address conductors and data conductor.Unit in the active matrix apparatus comprises switch, typically has the form of thin film transistor (TFT) (TFT), is used for selectively data-signal being switched to the remainder of this unit, for example display pixel, sensor unit or memory cell.

These unit typically comprise the capacitive element of stored charge, and this electric charge depends on data level.

Refresh rate in these devices (no matter being display, sensor, storer or other device) generally requires matrix unit switch conducting or disconnection fast, and this transfers the voltage level that is used for the switching transistor switch has been forced enough requirement fast.There has been the various supply voltage that is used to raise to make them be suitable for the circuit of oxide-semiconductor control transistors.And signal amplification in the pixel has been proposed with various form.

Thereby be suitable for being integrated in the pixel/unit of array apparatus or the signal amplification circuit that is suitable for the boosted voltage level still has demand to having a few components.

Summary of the invention

According to the present invention, a kind of amplifying circuit is provided, comprising:

Input end provides input voltage to this input end;

Capacitor arrangement;

Construction of switch;

Wherein capacitor arrangement comprises first capacitor and second capacitor with pressure-sensitive capacitance amount,

Wherein, circuit is operated with two kinds of patterns, under first pattern, input voltage is provided to a terminal of at least the first capacitor, under second pattern, construction of switch makes electric charge redistribute between first and second capacitors, so that the voltage at the first capacitor two ends obtains changing, thereby reduce the electric capacity of first capacitor, output voltage depends on the voltage at the first capacitor two ends that the result obtains.

The present invention has utilized that the shared of electric charge combines between voltage controlled capacitor amount and capacitor, and the result provides the voltage amplification characteristic.Therefore this structure can be used to the amplification of aanalogvoltage or boost (for example digital voltage) of fixed level.Therefore, circuit of the present invention can be used to level shift or amplification, and uses a spot of element to be integrated into pixelated array (if desired).

Construction of switch can comprise input switch, this input switch is used for selectively input voltage being connected to capacitor arrangement, and wherein under first pattern, input switch is connected to capacitor arrangement with input voltage, under second pattern, input switch is isolated input voltage and capacitor arrangement.Under second pattern, the voltage of a terminal of first and/or second capacitor is changed.Therefore, this structure stores input voltage on the capacitor arrangement into, and changing control voltage subsequently influences the electric charge share operations that changes output voltage.

The change of the voltage of a terminal of first capacitor preferably causes the minimizing of electric capacity.This can be used to produce the increase of voltage.

Second capacitor also can be pressure-sensitive, and under second pattern, the voltage of a terminal of second capacitor also can be changed.This can be used to balances charge flow.For example, under second pattern, the voltage of a terminal of first capacitor obtains increasing, and the voltage of a terminal of second capacitor is reduced simultaneously.

The change of the voltage of a terminal of second capacitor preferably causes the minimizing of electric capacity.First and second capacitors can be the same.

In another kind of structure, construction of switch comprises:

One first switch or a plurality of first switch are used for input voltage is connected to a terminal of first and second capacitors;

Second switch is used for each is controlled the terminal that voltage is connected to first and second capacitors;

An input switch is used for reference voltage is connected to another terminals of first and second capacitors.

In this structure, under first pattern, first switch or a plurality of first switch and input switch closure, therefore the voltage at capacitor two ends depends on input voltage, under second pattern, the second switch closure, output voltage comprises the voltage on another terminals of first and second capacitors.

In another structure, input end is connected to a terminal of first and second capacitors, and each control voltage is connected to another terminal of first and second capacitors by each gauge tap of construction of switch.Construction of switch preferably further comprises short circuiting switch, and this short circuiting switch is connected between another terminal of first and second capacitors.

In this circuit, under first pattern, the gauge tap closure, the voltage at capacitor two ends depends on input voltage, under second pattern, the short circuiting switch closure, output voltage comprises the voltage on another terminals of first and second capacitors.

Usually, compression capacitor or each compression capacitor can comprise transistor, and this transistorized source electrode connects together with drain electrode, and one of them terminal is defined by grid, and another terminal is by source electrode that is connected and drain electrode definition.This provides one and has been easy to the compression capacitor integrated with other transistor arrangement.For example, the Thin Film MOS transistor can be used.

Input switch can be by the Control of Voltage on the terminal of first capacitor.By this way, the pressure-sensitive control of timing controlled and capacitor is controlled by single control signal, has simplified the control of circuit, and has reduced the number of required control line.Input switch can comprise the first transistor, and the grid of this first transistor is connected to a terminal of first capacitor.When using second compression capacitor, input switch can comprise transistor seconds, and this transistor seconds is in parallel with the first transistor, and the grid of transistor seconds is connected to a terminal of second capacitor.

Circuit of the present invention can be used to a kind of active matrix apparatus, and this active matrix apparatus comprises the device unit array and is used to produce the circuit of the control signal of control device unit.This circuit is used for increasing the voltage level of control signal before control signal is provided to device unit.

Circuit of the present invention also can be used to the outside of array, come to make level translation from the signal of exterior I Cs, for example, and from the control signal of low pressure controller IC or from the digital data signal of external memory storage IC.Level translation signal can by integrated TFT circuit for example the digital to analog converter in the column drive circuit handled.

In Another application, the present invention can be used for active matrix display devices, this equipment comprises array of display pixels, and each display unit has the brush in pixels novel circuit, and wherein this brush in pixels novel circuit comprises the circuit that is used to amplify the grid voltage of oxide-semiconductor control transistors of the present invention therein.

For example, refresh circuit can comprise sensing circuit and write circuit, above-mentioned sensing circuit is stored a display pixel voltage in storage capacitor structures, above-mentioned write circuit depends on that the display pixel voltage of storage provides a voltage to display pixel, wherein write circuit comprises oxide-semiconductor control transistors, the grid voltage of oxide-semiconductor control transistors is provided by storage capacitor structures, and wherein storage capacitor structures comprises the capacitor arrangement of amplifying circuit.

More generally, circuit of the present invention can be used to active matrix array device, and this active matrix array device comprises a device unit array, and each device unit in the array is provided with circuit of the present invention.For example unit can comprise storage unit, image sensing pixel or display pixel.

The present invention also provides a kind of method of amplifying signal, comprises:

Input signal to one capacitor arrangement is provided, and this capacitor arrangement comprises first capacitor and one second capacitor with pressure-sensitive capacitance amount,

Input signal and capacitor arrangement are isolated; With

Therefore the voltage of change on a terminal of first capacitor change the electric capacity of first capacitor and change output voltage.

Description of drawings

Example of the present invention will be described in detail with reference to the attached drawings, and accompanying drawing is as follows:

Accompanying drawing 1 shows the conventional pixel wiring diagram of active matrix LC display;

Accompanying drawing 2 shows a complete LC display;

Accompanying drawing 3 shows the structural drawing of an amplifying circuit of the present invention;

Accompanying drawing 4 shows a kind of embodiment of the circuit of accompanying drawing 3;

Accompanying drawing 5 shows the characteristic of the compression capacitor that uses in the circuit of accompanying drawing 3;

Accompanying drawing 6 shows the control voltage of the circuit that is used to control accompanying drawing 3;

Accompanying drawing 7 shows the simplified model of the capacitor specific characteristics that is used for the mimic channel response;

Accompanying drawing 8 shows the circuit response of accompanying drawing 3, and this response is based on the model of the compression capacitor of accompanying drawing 7;

Accompanying drawing 9 shows second kind of embodiment of the circuit of accompanying drawing 3;

Accompanying drawing 10 shows the control voltage of the circuit that is used to control accompanying drawing 9;

Accompanying drawing 11 shows the circuit response of accompanying drawing 9, and this response is based on the model of the compression capacitor of accompanying drawing 7;

Accompanying drawing 12 shows a kind of circuit embodiment of the circuit of accompanying drawing 9;

Accompanying drawing 13 shows the circuit response of accompanying drawing 12;

Accompanying drawing 14 shows another example of circuit of the present invention;

Accompanying drawing 15 shows the characteristic of the compression capacitor that uses in the circuit of accompanying drawing 14;

Accompanying drawing 16 shows the control voltage of the circuit that is used to control accompanying drawing 14;

Accompanying drawing 17 shows the circuit response of accompanying drawing 14;

Accompanying drawing 18 shows another example of circuit of the present invention;

Accompanying drawing 19 shows the control voltage of the circuit that is used to control accompanying drawing 18;

Accompanying drawing 20 shows the circuit response of accompanying drawing 18;

Accompanying drawing 21 shows the circuit of the accompanying drawing 12 with an output buffer;

Accompanying drawing 22 shows the circuit of the accompanying drawing 12 with an output latch;

Accompanying drawing 23 shows a suggestion LCD pixel wiring diagram with brush in pixels novel circuit;

How the circuit that accompanying drawing 24 shows accompanying drawing 23 is modified the structural drawing that uses multiplying arrangement of the present invention;

Accompanying drawing 25 shows a kind of embodiment of the circuit of accompanying drawing 24.

Embodiment

Present invention relates in general to be used for circuit that signal is amplified.But, the present invention is relevant with the amplification requirement in the active matrix array device more specifically.For this reason, at first introduce a kind of in the common form of active matrix apparatus and the particular problem relevant that will solve by the present invention with these devices.

Accompanying drawing 1 shows a kind of conventional pixel structure that is used for active matrix liquid crystal display.This display is set to into the pel array of multirow and multiple row.The shared common row conductor 10 of each row pixel, the shared common column conductor 12 of each row pixel.Thin film transistor (TFT) 14 of each pixel packets Chinese juniper and a liquid crystal cells 16, the two series connection is arranged between column wire 12 and the public electrode 18.Transistor 14 is to be able to conducting and to end by the signal that row provides on the lead 10.Therefore the grid 14a of each transistor 14 that row lead 10 and related pixel are capable is connected.Each pixel comprises a holding capacitor 20 in addition, and an end 22 of this holding capacitor 20 is connected with next line electrode, previous row electrode or an independent electrode for capacitors.Capacitor 20 storing driver voltages, thus even after transistor 14 has been cut off, also can keep the signal at liquid crystal cells 16 two ends.

For the voltage that liquid crystal cells 16 is activated to hope obtains required gray level, and provide capable addressing pulse synchronously on the lead 10 of being expert at, suitable simulating signal is provided on column wire 12.Row address pulse conducting membrane transistor 14, thus make column wire 12 liquid crystal cell 16 can be charged to the voltage of hope, but also holding capacitor 20 can be charged to identical voltage.The be expert at afterbody of address pulse make transistor 14 end, and when to other row addressing, holding capacitor 20 is kept the voltage at 16 two ends, unit.Holding capacitor 20 reduces the influence of liquid crystal leakage, and the number percent that reduces the pixel capacitance amount that the voltage dependence by the liquid crystal cells electric capacity causes changes.

Row is order addressing in succession, so that all row are addressed in a frame period, and in the frame period subsequently, refresh.

As shown in Figure 2, go address signal by horizontal drive circuit 30 be provided to array of display pixels 34, pixel drive signal is provided to array of display pixels 34 by row addressing circuit 32.The display light 36 of having powerful connections, and each liquid crystal cells 16 modulation (decay changeably just) from the light of bias light 36, change the pixel image intensity (representing with arrow 38) of watching from array of display pixels 34 opposite sides.Array 34 is formed the Active Matrix LCD At module.Color filter is used to provide the red, green, blue pixel, makes color display apparatus to be formed.

The present invention relates to use compression capacitor to come amplifying signal.This technology especially focuses on because of TFT performance finite sum and lays the limited application that causes in the image element circuit that uses the large-area matrix device such as display (as mentioned above) and sensor that traditional signal amplification technique may be very difficult in the space of circuit.

Accompanying drawing 3 schematically shows a kind of overall plan of circuit of the present invention.According in this form of the present invention, import the structural input signal that transfer circuit 40 is used to set up capacitor 42, output transfer circuit 44 is used for amplifying signal is passed to other circuit.

In accompanying drawing 4, provided the simplification circuit of the principle of this solution route of explaining.Applied signal voltage passes through switch S _INBe applied to capacitor C ₁And C ₂This switch representative input transfer circuit 40.C ₁Be capacitor with fixed value, and C ₂It is capacitor with electric capacity that the voltage that exists with its two ends becomes.In side circuit, these capacitors can be real circuit component or the stray capacitance that can represent circuit, and for example the layout electric capacity of circuit or switchgear are such as the electric capacity of thin film transistor (TFT).The output transfer circuit is not shown in accompanying drawing 4.

Compression capacitor C ₂Can form by metal-oxide semiconductor (MOS) (MOS) capacitor.How the electric capacity of accompanying drawing 5 expression mos capacitance devices is according to function f _c(V _c) change with the voltage at its two ends.As the voltage V that is applied _cHave big on the occasion of the time, electric capacity trends towards maximal value.As the voltage V that is applied _cWhen having lower value, electric capacity reduces to minimum value.

The function of accompanying drawing 3 circuit is to operate to the input cycle with to the output cycle on the difference of this curve.Accompanying drawing 5 expressions are for the condenser voltage V in output cycle _OUT-V _A2With condenser voltage V for the input cycle _IN-V _A1

The waveform relevant with circuit operation as shown in Figure 6.The first of circuit operation is a switch S _INClosed a period of time, make the output node of circuit can be charged to input voltage level V _INSwitch disconnects subsequently, is applied to capacitor C ₂The voltage of one side is from original levels V _A1Become more high level V _A2

Voltage V _AChange can be to the output voltage influence of circuit by considering because of V _AThe C that gradual change causes ₁And C ₂The change in charge of last existence must the equal and opposite in direction opposite in sign and is assessed.

ΔQ ₁＝(V _OUT-V _IN)C ₁

${\mathrm{\&Delta;<figure-callout\; id="2"\; label="Q"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2=\underset{\mathrm{VIN}-\mathrm{<figure-callout\; id="1"\; label="VA"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">VA</figure-callout>}1}{\overset{\mathrm{VOUT}-\mathrm{<figure-callout\; id="2"\; label="VA"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">VA</figure-callout>}2}{\&Integral;}}\mathrm{fc}\left(v\right)\mathrm{dV}$

ΔQ ₁＝-ΔQ ₂

Consider capacitor C ₂Voltage dependence can get over the situation that function is described by the simple rank shown in the accompanying drawing 7, accompanying drawing 7 is illustrated in C _2maxAnd C _2minBetween electric capacity the threshold value V of rank when changing more takes place _TV _A1And V _A2Be to select like this: during input phase, C ₂The voltage at two ends is greater than the threshold voltage V of capacitor _T, during output stage, C ₂The voltage at two ends is less than the threshold voltage of capacitor.

By making C ₁And C ₂Between the electric charge flow equate, output voltage and input voltage can be associated.

ΔQ ₁＝-ΔQ ₂

(V _OUT-V _IN)C ₁＝C _2min(V _T-(V _OUT-V _A2))+C _2max((V _IN-V _A1)-V _T)

V _OUT(C ₁+C _2min)＝V _IN(C ₁+C _2max)+C _2min(V _T+V _A2)-C _2max(V _A1+V _T)

Therefore the peak signal gain is $\mathrm{Gain}=\frac{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\mathrm{<figure-callout\; id="1"\; label="max\; C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">max</figure-callout>}}}{C_{}}$

Also has offset voltage $\mathrm{Offset}=\frac{{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\min }(V_T+V_{A2})-{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\max }({\mathrm{<figure-callout\; id="1"\; label="V\; A"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">V</figure-callout>}}_A+V_T)}{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\min })}$

If C ₁=0.05pF, C _2max=0.1pF, C _2min=0.02pF, then Gain=2.14.This gain only obtains in a certain scope of voltage.In accompanying drawing 8 at V _A1=0V, V _A2=5V and V _TThe situation of=2V illustrates V _OUTAs V _INThe mode of function.The operation of this particular electrical circuit is by three area attributes.In a certain scope of input voltage, the small-signal gain of circuit equals calculated value 2.14.But, if falling under a certain value or increase to, input voltage is higher than second value, then gain drops to 1.The small-signal gain of circuit is equivalent to capacitor C greater than the limit point in one zone ₂Initial or the final voltage at two ends equals threshold voltage V _TThe point.Exceed these limit points, C ₂Electric capacity value between the input and output cycle do not change, so the gain of circuit drops to 1.Under be limited to V _IN-V _A1=V _TPerhaps V _IN=V _T+ V _A1On be limited to V _OUT-V _A2=V _TPerhaps V _OUT=V _T+ V _A2In order to realize the peak signal gain, the input reference signal strictness should be restricted to the scope between this upper and lower bound, but as long as fall between these limit points to the small part input reference signal, still can reach the gain greater than, will not be linear but amplify.

The operating area that boundary shown in the accompanying drawing 8 is clear and definite has reflected that the rank of the electric capacity shown in the accompanying drawing 7 get over function characteristic.In side circuit, electric capacitance change may be more gradually, as accompanying drawing 5 draws, and will have the so not clearly demarcated effect of transition that makes between these three operating areas like this.

By replacing C with second compression capacitor shown in the accompanying drawing 9 ₁, can increase the skew of gain and minimizing circuit.The electric capacity that second compression capacitor also is arranged so that it reduced during the output cycle.It is by secondary signal V _BControl, wherein this secondary signal V _BWith respect to V _AAnti-phase, thus two signals are tending towards offsetting in the combination of output node.If suppose compression capacitor C ₁Have and C ₂Identical form is in order to ensure C ₁Value during the output cycle, reduce C ₁Connection must and C ₂Connection opposite.The waveform relevant with circuit operation as shown in Figure 10.

During input phase, V _BBe high level V _B1, V _ABe low level V _A1During output stage, make V _BSwitch to low level V _B2, and make V _ASwitch to high level V _A2, so C ₁And C ₂Electric capacity all reduce.V is set _B1=V _A2And V _A1=V _B2Be easily.Although in the accompanying drawing 10 with voltage V _AAnd V _BBeing expressed as is to switch synchronously, even but voltage is switched at different time, in case when two voltages all reach their end value, the amplification of signal can take place still.

In the ideal case, at V _AAnd V _BBefore beginning to change or when beginning to change, S _INShould disconnect, flow back into input voltage source by switch so that prevent electric charge.

The gain of circuit can be according to calculating with top identical mode:

ΔQ ₁＝-ΔQ ₂

$-\underset{V_{B1}-V_{\mathrm{IN}}}{\overset{V_{B2}-V_{\mathrm{OUT}}}{\&Integral;}}\mathrm{fc}\left(v\right)\mathrm{dV}=-\underset{V_{\mathrm{IN}}-V_{A1}}{\overset{V_{\mathrm{OUT}}-{\mathrm{<figure-callout\; id="2"\; label="V\; A"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">V</figure-callout>}}_A}{\&Integral;}}\mathrm{fc}\left(v\right)\mathrm{dV}$

C _1min(V _T-(V _B2-V _OUT))+C _1max((V _B1-V _IN)-V _T)＝C _2min(V _T-(V _OUT-V _A2))+C _2max((V _IN-V _A1)-V _T)

V _OUT(C _1min+C _2min)＝V _IN(C _1max+C _2max)-C _1min(V _T-V _B2)-C _1max(V _B1-V _T)+C _2min(V _T+V _A2)-2 _max(V _A1+V _T)

$\mathrm{Gain}=\frac{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{1\max }+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\mathrm{<figure-callout\; id="1"\; label="max\; C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">max</figure-callout>}}}{C_{}}$

$\mathrm{Offset}=\frac{{-\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{1\min }(V_T-V_{B2})-{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{1\max }(V_{B1}-V_T)+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\min }(V_T+V_{A2})-{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\max }({\mathrm{<figure-callout\; id="1"\; label="V\; A"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">V</figure-callout>}}_A+V_T)}{({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{1\min }+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="A20048002266200281.png,A20048002266200301.png"\; state="\{\{state\}\}">C</figure-callout>}}_{2\min })}$

For example, if C _1max=C _2max=0.1pF, C _1min=C _2min=0.02pF, then Gain=5.

Illustrated at V in the accompanying drawing 11 _A1=V _B2=0V, V _A2=V _B1=5V and V _TThe situation V of=2V _OUTAs V _INThe mode of function.The operation of this circuit is by 5 area attributes.In a certain scope of input voltage, the small-signal gain of circuit equals calculated value 5, if but input voltage fall under a certain value or increase on second value, then the gain drop to 3.If input voltage increases on the higher upper limit or falls under the lower lower limit, then gain is kept to 1.The point that circuit gain changes numerical value equally with the input and output cycle during the voltage at compression capacitor two ends relevant.Equal V with the initial voltage at capacitor two ends _T(V _IN=V _T+ V _A1And V _IN=V _B1-V _T) situation and the final voltage at capacitor two ends equal V _T(V _OUT=V _T+ V _A2And V _OUT=V _B2-V _T) time corresponding, have two points relevant with each capacitor.As previously mentioned, gain is that for the reason that a certain input voltage level reduces the electric capacity of compression capacitor one or both of does not change between the input and output cycle.In order to obtain maximum gain, the electric capacity of two compression capacitors all must reduce between the input and output cycle.

The offset voltage of circuit depends on C ₁And C ₂Relative value and signal V _AAnd V _BVoltage level.May wish to change these parameter values, so that offset voltage is adjusted to the value that is suitable for the given circuit condition.

As mentioned above, a kind of feasible purposes of this circuit is the pixel that is used for being integrated into array apparatus.The amplifying circuit that has provided accompanying drawing 9 in the accompanying drawing 12 uses the feasible implementation of polycrystalline MOS transistor.

This circuit is to use being combined to form of p-type and n-type polycrystalline SiTFT.The switch that is used for during the input cycle input voltage being applied to output node is by transistor T ₁And T ₂The cmos transmission gate that forms.These transistorized grids drive with complementary clock signal CLK and NCLK.Although what illustrate is cmos transmission gate, p-type or n-transistor npn npn self also can be used for forming this switch.The compression capacitor that links to each other with output node is with two transistor Ts ₃And T ₄Form.Shown is that each transistorized source electrode is connected together with the drain electrode line, and the other end keeps disconnecting just enough although only connect each transistorized end on the principle.Employed is complementary transistor, but as optional another kind of scheme, can use the single-transistor form, if being connected of arrangement and grid and source electrode and/or drain electrode as requested, so that the electric capacity minimizing of hope to be provided between the input and output cycle.In this example circuit, with T ₃And T ₄Grid be connected with NCLK with two switch controlling signal CLK.

When signal CLK is height and signal NCLK when low, by T ₁And T ₂The transmission gate conducting that forms, and input voltage is delivered to T ₃And T ₄The capacitor that forms.If the voltage difference between signal CLK and the input voltage have greater than n-transistor npn npn threshold voltage on the occasion of, T then ₃To have big relatively electric capacity.Similarly, if the voltage difference between signal NCLK and the input voltage has the negative value greater than p-transistor npn npn threshold voltage, then T ₄To have big relatively electric capacity.To switch to CLK be low and NCLK when being high when the level of CLK and NCLK, and transmission gate ends, and output node is become with input voltage isolate.Simultaneously, the variation voltage level of CLK and NCLK has changed capacitor T ₃And T ₄The voltage that two ends present.In the time of within input voltage is in proper range, the voltage at capacitor two ends will be fallen below the transistorized threshold voltage, and their electric capacity is reduced, and sampled input signal is amplified.

The simulation result of this circuit as shown in Figure 13.The situation that accompanying drawing 13 expression is switched between the voltage of 0V and 10V for CLK and NCLK, how output voltage and gain change with input voltage.The threshold voltage of TFT be approximately 3V (n-type) and-3V (p-type).T ₁And T ₂The width that 5 μ m are arranged, T ₃And T ₄The width that 40 μ m are arranged.The length of all TFT is 5 μ m.

In accompanying drawing 12, the TFT capacitor is driven by the transistorized same signal of control input switch.Also can use independent control signal, for example be used for switching with respect to the signal on the switching delay TFT capacitor of TFT input switch.For the switching rate of compensation switching signal, this also is desirable.

In the circuit of accompanying drawing 9, input signal is applied on the terminal of two capacitors by input switch.The multiple alternate manner that signal voltage can be applied to capacitor arrangement is arranged.For example, on input voltage being applied to the shared node of two compression capacitors, it can also be applied in addition and connect control voltage V _ANode or be applied to and connect control voltage V _BNode, perhaps be applied to simultaneously on above-mentioned two nodes.Importantly, input voltage must influence the voltage that at least one (preferably owning) compression capacitor two ends presents during the input cycle.

The capacitor arrangement that accompanying drawing 14 expression and accompanying drawing 9 are identical, but have extra switch, be used for making input signal during importing, to be applied on the opposite terminal of two compression capacitors.In fact, the extra switch of accompanying drawing 14 Already in is used to produce V _AAnd V _BCircuit in, so in fact the circuit of accompanying drawing 14 does not make required overall circuit obviously complicated.Simultaneously, make the common node of two capacitors be charged to reference potential V _R

Therefore, circuit has reference potential V _RBe connected to the first input switch S of common electrical container terminal ₁The second and the 3rd switch S ₂And S ₃Input voltage is connected to the opposite terminal of each capacitor, the 4th and the 5th switch S ₄And S ₅To control voltage V _AAnd V _BConnect their capacitors separately.

In the analysis below, suppose that compression capacitor is formed by depletion type n-type MOS device, the desired electrical capacity ratio that this device has form shown in the accompanying drawing 15 applies voltage characteristic.

The threshold voltage of depletion type MOS capacitor is a negative value.When this threshold voltage of voltage ratio at capacitor two ends during more towards negative direction, capacitor has the low-voltage capacity value, and when this threshold voltage of voltage ratio at capacitor two ends during more towards positive dirction, capacitor has the higher capacitance value.

During the input cycle, switch S ₁, S ₂, S ₃Closure, S ₄, S ₅Disconnect.Therefore, reference voltage is stored in a side of each capacitor, and input voltage is stored in the opposite side of each capacitor.With reference voltage V _RValue be chosen to, during the input cycle, two compression capacitors all have higher capacitance value.When charging is finished, with S ₁, S ₂, S ₃Disconnect, and then during the output cycle, with S ₄, S ₅Closed.Like this, control voltage is applied to the opposite side of two capacitors.

With V _AAnd V _BLevel be chosen to, during the output cycle, the voltage ratio threshold voltage at compression capacitor two ends is more towards negative direction, and therefore the capacitance value of these capacitors drops to lower value.Show the relative level of different voltages with the waveform table in the accompanying drawing 16.

Accompanying drawing 17 expression for the high value of the electric capacity of compression capacitor be 0.1pF, electric capacity be 0.02pF, V than low value _A=5V, V _B=0V, V _R=2.5V and V _TThe situation of=-1V, how the output voltage of circuit changes with input voltage.With the same under the situation of the circuit of accompanying drawing 9, it is 5 size that maximum gain has, but this through circuit of transforming in, gain is that negative value and this circuit show as inverting amplifier.This anti-phase origin cause of formation is to apply the node of input signal and obtain the two opposite sides of the node of output signal at capacitor.

This example shows also can become to obtain negative gain with circuit design of the present invention, but also shows also and control voltage can be applied on the terminal identical with input voltage of capacitor.

In the circuit of accompanying drawing 14, will not be applied on two capacitors by input signal.If only signal is applied on the capacitor, then gain will reduce.

Can also apply one second input signal by the replacement reference voltage uses this circuit that the difference of two signals is amplified.So poor through between two input signals that amplify of output voltage representative.

In above-mentioned example, input signal is applied to capacitor arrangement by input switch, therefore during input phase, input voltage is connected to capacitor arrangement, and during output stage, input voltage and capacitor arrangement is isolated.

In fact, needn't input signal be applied on the capacitor by input switch.

Accompanying drawing 18 expressions are applied directly to the Low ESR input voltage source in the circuit of two compression capacitors.

Capacitor C ₁And C ₂Be in parallel equally, a terminal of each capacitor is connected to input voltage, but in this circuit, does not have input switch.Another terminal of each capacitor passes through switch S separately ₁And S ₂With control terminal V _AAnd V _BBe connected.Above-mentioned these another terminals form the output terminal of circuit, and this point is from hereinafter obviously finding out.Between another terminal of two capacitors, be provided with another switch S ₃, and in this circuit, the electric charge redistribution between two capacitors is by the connection S between the switch capacitor ₃Realize, rather than be applied to by change that their voltage realizes.

The threshold voltage hypothesis of capacitor is+2V, and is the same with the circuit of accompanying drawing 9.

During the input cycle, switch S ₁And S ₂Closure, thereby with capacitor C ₁And C ₂Be charged to the voltage that depends on applied signal voltage.With V _AAnd V _BValue be chosen to C ₁And C ₂The voltage at two ends is all greater than threshold voltage 2V, and therefore two capacitors have higher capacitance value at first.During the output cycle, make S ₁And S ₂Disconnect, make S subsequently ₃Closed.The electric charge redistribution occurs in C ₁And C ₂Between, therefore the voltage that causes the capacitor two ends cause C less than threshold voltage ₁And C ₂The minimizing of the electric capacity of the two.Output signal is from C ₁And C ₂Public line obtain, this public line connects the opposition side of input signal at capacitor.

Shown in top example, this causes circuit to have negative gain.The relative level that has voltage during this circuit operation has been shown in the accompanying drawing 19.

Accompanying drawing 20 expression at the high value of the electric capacity of compression capacitor be 0.1pF, electric capacity be 0.02pF, V than low value _A=10V, V _B=-5V and V _TThe situation of=2V, how the output voltage of this circuit changes with input voltage.The maximum gain of this circuit is-4, and this yield value is less than ± V in the difference of input voltage and output voltage _TLimit point between obtain.When circuit is operated outside these limit points, C ₁Perhaps C ₂Electric capacity during the output cycle, do not change into than low value.

Circuit of the present invention has multiple feasible purposes in the active matrix array device field.To provide first example at the level translation of numerical data now.

The thin-film transistor circuit that is formed on the substrate of active matrix LC display is using the higher supply voltage of conventional crystal silicon IC than being used to control them to carry out work in typical case.Being integrated into level translation circuit on the display base plate is used for from the low voltage digital signal interface of the control IC TFT circuit to high voltage.A kind of feasible level translation circuit of accompanying drawing 21 expressions, this circuit is based on the amplifying circuit of accompanying drawing 12.

The output transfer circuit of amplifier realized by clock control CMOS phase inverter 50, and this phase inverter 50 is formed to T8 by transistor T 5.The output voltage of level translation circuit is only effective during the output cycle of amplifier, the clock signal that is input to the clock control phase inverter is arranged so that the output signal of phase inverter is low-impedance during this output cycle.

For continuous data output is provided, may wish to realize a latch circuit circuit, as shown in Figure 22 at the output terminal of level translation circuit.

If the voltage level of CLK and NCLK identical (VDD and VSS), the threshold voltage equal and opposite in direction of capacitor TFT T3 and T4, the width of T3 and T4 and equal in length, then the input switch voltage of level translating device is positioned at the centre position of VDD and VSS.In practice, if input switch voltage has different value (for example approaching VSS) then is more convenient.By changing relative width and the length of T3 and T4, can realize some change of input switch voltage.But,, then during the amplifier input cycle, can again transistor T 4 be biased on the threshold voltage if require input voltage switching under the voltage near VSS very much.This problem can replace T4 to avoid by using such compression capacitor: when the voltage at these device two ends hanged down, this compression capacitor had high relatively electric capacity.For example, can be a NMOS depletion-mode transistor.Under the situation of n-type depletion mode device, transistorized grid can be connected to the output node of amplifying circuit, and source electrode and drain electrode are connected to signal NCLK.

Circuit of the present invention can be used as level translation circuit, is used for providing from the outside voltage level of viewing area (accompanying drawing 2 34), for example is used to produce capable voltage waveform.Circuit of the present invention also can be used in the single pixel of array apparatus.A special applications is in the refresh circuit of AMLCD pixel.Using refresh circuit in the LCD pixel is a new relatively development, and is reduced power consumption and driven by hope.

Active matrix array device, particularly active matrix array display device have obtained in such as computing machine, mobile phone, personal digital assistant or the like using widely at battery powered electronic installation.In said apparatus, reducing power consumption is important problem.

A pith of the power consumption of active matrix array device originates from the charging of matrix array elements.Especially at the large tracts of land active matrix array device or have in the active matrix array device of a large amount of row and column leads, each lead has big relatively electric capacity, and charging can consume a large amount of power to matrix array elements, because in an addressing period of active matrix array device, may have to repeatedly to column conductor capacitance charging and discharge, so as in all relevant matrix array elements the electric charge that meets the requirements of storage in succession.

Data value in being stored in each matrix array elements does not change and is that this especially wastes under the situation that periodically rewrites with the identical data value.For example, above-mentioned situation may occur in and require active matrix array device to produce for a long period of time under the situation of constant output, for example switches to stand-by state because active matrix array device is formed its a part of electronic installation.

In order to realize the saving of this power consumption, can realize low-power operating mode, under this pattern, each pixel of display is worked as the self-refresh dynamic storage cell.In the time needn't replacing charge stored, can realize that power consumption reduces along with each field duration.

The dot structure that the accompanying drawing 23 expression inventor propose.The base pixel element of accompanying drawing 1 in accompanying drawing 23 with identical Reference numeral repeat mark.

Each pixel has refresh circuit 60, this refresh circuit 60 link to each other with pixel electrode (public terminal of lc unit 18 and holding capacitor 20).This refresh circuit comprises second input transistors 62, and this second input transistors 62 is controlled at its grid by refresh control line 64.What connect with second input transistors 62 is another transistor 68.Therefore transistor 62 and 68 is connected in series between row 12 and the pixel electrode, and they can realize that voltage is from being listed as the transmission of pixel electrode by the mechanism different with common image element circuit element 10,14.

The grid voltage of second holding capacitor, 66 memory transistors 68, so the switch of oxide-semiconductor control transistors 68.Capacitor plays the effect of pixel internal storage storage unit, and pixel electrode voltage can be stored on this capacitor 66 by another transistor 70.Like this, capacitor 66 can be used for pixel electrode voltage is sampled, and condenser voltage also can be used for controlling voltage applying from row 12 to pixel electrode (by the switch of oxide-semiconductor control transistors 68).Read the grid voltage of control line 72 oxide-semiconductor control transistors 70.

By following introduction, operating in of circuit will be clearer on the more details.

Before low-power mode begins, at first data are written in the pixel with traditional approach.But data voltage may only got one of two values, for example 0V or 5V in typical case.Like this, low-power mode provides the image of having lost gray-scale information.

In order to minimize the power consumption of display, wish consequently to have avoided the charge transfer between the capacitor in the image element circuit in each frequent refresh cycle to the transmission of pixel in section pause data sometime.But along with the past of time, the electric charge that is applied to pixel capacitor will be by thin film transistor (TFT) or liquid crystal leakage.For fear of above-mentioned situation, must carry out the periodic refresh frequency of normal refresh speed (but be less than) to data, and this is to use brush in pixels novel circuit 60 in each pixel that is integrated in display to realize.

Though in order to reduce power consumption, can use lower refreshing frequency, even refreshing frequency is identical with normal addressing frequency, still can power save, because can refresh many capable pixels simultaneously.This has reduced voltage waveform and has appeared at the row of display and the frequency on the public electrode, has therefore reduced power consumption.

Typical refresh operation carries out in the following manner.The data voltage that had before applied (being 0V or 5V in above-mentioned example) at first is temporarily stored in second capacitor 66.This reads control line 72 and realizes for high-voltage level turn-on transistor 70 by making.Electric charge is shared and is occurred between three capacitors 18,20 and 66.Because obviously greater than the electric capacity of capacitor 66, the voltage on the capacitor 66 that the result obtains is substantially equal to data voltage level to pixel capacitance amount (18 and 20).At this constantly, 0V is applied to column wire 12.So transistor 70 is ended, and data is stored on the capacitor 66 temporarily.

Then with pixel capacitance charges to high data voltage level 5V, this is by being applied to this voltage on the column wire 12 and of short duration turn-on transistor 14 is realized.

The operation of circuit is, the voltage by making row electrode 12 is for low data voltage level and make refresh line 64 be high-voltage level, comes turn-on transistor 62, makes the data that are stored on the capacitor 66 anti-phase and it is turned back to pixel capacitance.

If the data voltage that is stored on the capacitor 66 is low, near 0V, then transistor 68 ends, and pixel remains under the high data level, and this high data level is the inverse value that is stored in the data on 66.If the data voltage that is stored on 66 is high, near 5V, then transistor 68 conductings, pixel capacitance discharges into the low data voltage level on the column wire 12, and this low data voltage level is the inverse value that is stored in the data of capacitor 66.

The operation of this circuit is based on common electrode drive scheme, so public electrode 22 depends on the driving polarity that is applied to LC, at about 0V with approximately switching between the 5V.Be applied to the 0V of pixel and the voltage of 5V and will depend on that driving polarity provides bright or dark output.

Therefore, if public electrode is about 5V (driving LC is negative), then the 0V pixel voltage is corresponding to dark pixel (the high mean square value voltage of LC), and the 5V pixel voltage is corresponding to bright pixel (the low mean square value voltage of LC).If public electrode is about 0V (LC is just driven), then the 5V pixel voltage is corresponding to dark pixel, and the 0V pixel voltage is corresponding to bright pixel.

Voltage switching timing on the public electrode is important for the operation of refresh circuit.When refresh operation begins, when pixel voltage being sampled on the capacitor 66, public electrode must be in voltage identical to the last addressing of pixel or when refreshing under.After sampling is finished and before pixel is charged to 5V or simultaneously, the voltage on the public electrode must be switched to other level.

The data high-voltage level on the grid of transistor 68 and the difference of data low voltage level will be enough between conducting and not on-state to switch this device, are very important for the operation of image element circuit.If the threshold voltage of transistor 68 is too big with respect to the data voltage range at grid place, then refresh operation can not correct execution.When data voltage when pixel capacitance is delivered to 66, electric charge is shared and is taken place, above-mentioned electric charge is shared the amplitude that can reduce data-signal.

If the minimizing of this signal amplitude is too big, then signal may become and be not enough to switch 68, and refresh operation also will be failed simultaneously.

Therefore, it is favourable providing some amplification to the data-signal at transistor 68 grid places, because this will increase the stability of circuit for the variation of electric capacity and TFT characteristic.By replace the capacitor 66 of accompanying drawing 23 with two compression capacitors shown in the accompanying drawing 24, above-mentioned amplification method can be applied to this image element circuit at an easy rate.

As shown in the figure, above-mentioned compression capacitor is being read between control line 72 and the refresh line 64.Therefore above-mentioned two lines have played voltage source V _AAnd V _BEffect, for example as shown in Figure 9.As mentioned above, the voltage on these lines changes during refresh operation, and these changes can be used to provide at output terminal (grid of transistor 68 just) amplification of hope.

Capacitor can form in every way, but method is to use gate metal, gate insulator and semi-conductive non-impurity-doped layer or lightly-doped layer easily.For example, if the TFT that uses in the image element circuit is a n-type polycrystalline silicon device, then can use n-type TFT to form capacitor easily, wherein the source electrode of n-type TFT connects together with drain terminal, as shown in Figure 25.

Under the typical circuit operating frequency, when on the gate terminal with respect to the voltage of source electrode and drain terminal during less than transistorized threshold voltage, the electric capacity of n-type TFT has low value, when grid voltage during greater than threshold voltage, the electric capacity of n-type TFT has high value.The transistor 80 of accompanying drawing 25 is connected in the following manner with 82: between reading duration, when data voltage when the pixel capacitance amount passes to them, have higher capacity; During refreshing, when data turn back to pixel capacitance with anti-phase form, have than low-voltage capacity.

The change of 80 and 82 electric capacity is to change with the voltage at the caused transistor of refresh control signal two ends and cause by reading.Between reading duration, read control signal and be in high level, 10V for example, refresh control signal is in low level, for example-7V.Because the pixel data voltage level is near 0V and 5V, read and refresh on the electrode voltage sufficient to guarantee transistor 80 and 82 the two all be in the higher capacity state during this period.

During the refresh cycle, read-out electrode is in low-voltage-7V, refreshes electrode and is in high level 10V.Under the point that this electric capacity that causes the voltage at 80 and 82 two ends to drop to them reduces, cause being connected to the amplification of the data-signal on the circuit node of transistor 68 grids.This amplification is by the particular instance of image element circuit being carried out circuit simulation and investigating.Have by two under the situation that the capacitor of fixed value forms at capacitor 66, the ending during refreshing, the data voltage level of transistor 68 grids be 2.87V and-0.28V.The circuit that forms by two compression capacitors for the capacitor 66 shown in accompanying drawing 24 and 25, the data voltage level of equivalence be 5.88V and-0.57V.The data signal amplitude of this expression oxide-semiconductor control transistors 68 increases by 2 times.

The advantage that the present invention brings can be found out from many aspects.This means that image element circuit allows more variation on transistor characteristic, the electric capacity relevant with image element circuit also allowed more variation, perhaps provide a minimizing to be provided to the chance of the data voltage amplitude of pixel, this can cause the further minimizing of operand power, because data voltage amplitude enough switching transistor 68 before amplifying.

Said method also can be applied to reading of a plurality of circuit function blocks that comprise memory device, particularly dynamic storage cell or refresh, sensing and imaging device, and picture element signal is read, level translation circuit, the amplification of low level simulation or digital signal.

A plurality of different circuit with different amplification responses illustrate.In each case, circuit has an input voltage range that circuit gain is constant.Therefore circuit has the input voltage range of 0.5V at least, and preferably at least about 1V, circuit provides linear gain in this scope.But circuit is operated in wideer input voltage range.

A plurality of specific implementation of amplifying circuit of the present invention provide, and use but circuit of the present invention can be used for other.

Claims (27)

1. amplifying circuit comprises:

Input end (V _IN), provide input voltage to this input end;

Capacitor arrangement (42); With

Construction of switch;

Wherein capacitor arrangement comprises the first capacitor (C with pressure-sensitive capacitance amount ₂) and the second capacitor (C ₁),

Wherein, this circuit can be with two kinds of pattern operations, under first pattern, input voltage is provided to a terminal of at least the first capacitor, under second pattern, construction of switch makes electric charge redistribute between first and second capacitors, so that the voltage at the first capacitor two ends changes, thereby reduce the electric capacity of first capacitor, output voltage depends on the voltage at the first capacitor two ends that the result obtains.

2. according to the circuit of claim 1, wherein construction of switch comprises input switch (S _IN), this input switch is used for selectively input voltage being connected to capacitor arrangement (42), and wherein under first pattern, input switch is connected to capacitor arrangement with input voltage, and under second pattern, input switch is isolated input voltage and capacitor arrangement.

3. according to the switch of claim 2, wherein under second pattern, the voltage (V on the terminal of first and/or second capacitor _A, V _B) be changed.

4. according to the circuit of claim 3, wherein the change of voltage takes place on a terminal of first capacitor, and causes electric capacity to reduce.

5. according to the circuit of claim 3, the second capacitor (C wherein ₁) also be pressure-sensitive, under second pattern, the voltage on the terminal of first and second capacitors is changed.

6. according to the circuit of claim 5, wherein the change of voltage causes electric capacity to reduce on second capacitor terminal.

7. according to the circuit of claim 5 or 6, wherein under second pattern, the first capacitor (C ₂) a terminal on voltage (V _A) obtain increasing, and the second capacitor (C ₁) a terminal on voltage (V _B) be reduced.

8. according to the circuit of claim 7, wherein under second pattern, the first capacitor (C ₂) a terminal on voltage (V _A) be increased to and be higher than input voltage from being lower than input voltage, and the second capacitor (C ₁) a terminal on voltage (V _B) be reduced to and be lower than input voltage from being higher than input voltage.

9. according to the circuit of one of claim 3-8, wherein input switch is voltage-controlled by on the terminal of first capacitor.

10. according to the circuit of claim 9, wherein input switch comprises and draws together the first transistor (T1), and this first transistor has a grid that terminal is connected with first capacitor.

11. circuit according to claim 10, wherein second capacitor also is pressure-sensitive, and wherein under second pattern, voltage on the terminal of second capacitor also obtains changing, and wherein input switch comprises the transistor seconds (T2) in parallel with the first transistor (T1), and the grid of transistor seconds is connected with a terminal of second capacitor.

12. according to the circuit of claim 1, wherein construction of switch comprises:

First switch or a plurality of first switch (S ₂, S ₃), be used for input voltage is connected to a terminal of first and second capacitors;

Second switch (S ₄, S ₅), be used for each is controlled the terminal that voltage is connected to first and second capacitors; With

Input switch (S ₁), be used for reference voltage is connected to another terminals of first and second capacitors.

13. according to the circuit of claim 12, wherein, under first pattern, first switch or a plurality of first switch (S ₂, S ₃) and input switch (S ₁) closure, so that the voltage at capacitor two ends depends on input voltage (V _IN), and under second pattern, second switch (S ₄, S ₅) closure, and input voltage comprises the voltage on another terminals of first and second capacitors.

14. according to the circuit of claim 12 or 13, wherein, first capacitor comprises and exhausts n-type MOS device.

15. according to the circuit of claim 14, wherein, first and second capacitors comprise and exhaust n-type MOS device.

16. according to the circuit of claim 1, wherein, the input end and the first and second capacitor (C ₂, C ₁) a terminal be connected and each gauge tap (S of each control voltage by construction of switch ₁, S ₂) be connected to another terminals of first and second capacitors.

17. according to the circuit of claim 16, wherein, construction of switch further comprises short circuiting switch (S ₃), this short circuiting switch is connected between another terminal of first and second capacitors.

18. according to the circuit of claim 17, wherein, under first pattern, gauge tap (S ₁, S ₂) closure, and the voltage at capacitor two ends depends on input voltage (V _IN), and under second pattern, short circuiting switch (S ₃) closure, output voltage comprises the voltage on another terminals of first and second capacitors.

19. circuit according to aforementioned arbitrary claim, wherein, described or each compression capacitor comprises transistor, and this transistor has source electrode and the drain electrode that connects together, and a wherein said terminal is defined by grid, and described another terminal is by source electrode that is connected and drain electrode definition.

20. according to the circuit of claim 19, wherein, transistor described or each compression capacitor comprises the Thin Film MOS transistor.

21. active matrix apparatus, comprise device unit array (34) and be used to produce and be used for the circuit (30 of control signal of control device unit, 32), comprise in addition that aforementioned arbitrary claim is described, be used for before control signal is provided to device unit, increasing the circuit of the voltage level of control signal.

22., wherein, comprise the latch circuit circuit that is in amplification circuit output end in addition according to the device of claim 21.

23. active matrix display devices, comprise array of display pixels, each display unit has the brush in pixels novel circuit, and this brush in pixels novel circuit comprises any one described amplifying circuit in the claim 1 to 20, is used to amplify the grid voltage of refresh circuit inner control transistor (68).

24. device according to claim 23, wherein, refresh circuit comprises sensing circuit and write circuit (68), above-mentioned sensing circuit is used for going up storage display pixel voltage in storage capacitor structures (66), above-mentioned write circuit is used to depend on that the display pixel voltage of storage provides voltage to display pixel, wherein write circuit comprises oxide-semiconductor control transistors (68), the grid voltage of oxide-semiconductor control transistors is provided by storage capacitor structures (66), and wherein storage capacitor structures comprises the capacitor arrangement of amplifying circuit.

25. an active matrix array device that comprises the device unit array, each device unit in this array are equipped with any one described circuit in the claim 1 to 20.

26. according to the device of claim 25, wherein, device unit comprises storage unit, image sensing pixel or display pixel.

27. the method for an amplifying signal comprises:

Provide input signal to capacitor arrangement, this capacitor arrangement comprises the first capacitor (C with pressure-sensitive capacitance amount ₂) and the second capacitor (C ₁);

Make electric charge at the first and second capacitor (C ₂, C ₁) between redistribute so that the voltage at the first capacitor two ends obtains changing, thereby reduces the electric capacity of first capacitor;

An output voltage is provided, and this output voltage depends on the voltage at the first capacitor two ends.

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