CN1822333A - Thin film transistor, method for producing thin film transistor and pixel structure - Google Patents
Thin film transistor, method for producing thin film transistor and pixel structure Download PDFInfo
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- CN1822333A CN1822333A CN 200510007379 CN200510007379A CN1822333A CN 1822333 A CN1822333 A CN 1822333A CN 200510007379 CN200510007379 CN 200510007379 CN 200510007379 A CN200510007379 A CN 200510007379A CN 1822333 A CN1822333 A CN 1822333A
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Abstract
Present invention relates to thin film transistor, thin film transistor and dot structure manufacturing method. It contains firstly forming grid on substrate, then forming gate insulating layer on substrate to cover grid, forming source/drain layer on gate insulating layer and source/drain layer exposing out part gate insulating layer above gate, finally forming channel layer on gate insulating layer above gate. Said method can avoid channel layer damage duo to over etching, to raise thin film transistor and dot structure making qualification rate.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, and be particularly related to the manufacture method of a kind of thin-film transistor and manufacture method and dot structure.
Background technology
The communication interface of display behaviour and information is the trend of development at present with the flat-panel screens.Flat-panel screens mainly contains following several: display of organic electroluminescence (OrganicElectro-Luminescence Display, OELD), plasma display (Plasma DisplayPanel, PDP) and Thin Film Transistor-LCD etc. (Thin Film Transistor LiquidCrystal Display, TFT-LCD).Wherein, being most widely used with Thin Film Transistor-LCD again.
Thin Film Transistor-LCD mainly is made of plurality of groups of substrates of thin-film transistor, colorized optical filtering multiple substrate and liquid crystal layer, and wherein plurality of groups of substrates of thin-film transistor is made up of a plurality of pixel cells of arranging in the array mode (pixel unit).Wherein, each pixel cell is made up of thin-film transistor and the data line that is electrically connected with thin-film transistor, scan line and pixel electrode (pixel electrode).Above-mentioned thin-film transistor comprises grid, channel layer, source/drain, and thin-film transistor is used as the switch module of pixel cell (pixel unit).
Figure 1A～1E is a kind of manufacturing process generalized section of known thin-film transistor.Please refer to Figure 1A, at first on substrate 110, form grid 120.Then on substrate 110, continue the gate insulation layer 130 of formation shown in Figure 1B with cover gate 120.Please continue C, continue it, on the gate insulation layer above the grid 120 130, form channel layer 140 and nurse contact material layer 150 difficult to understand with reference to Fig. 1.Afterwards, on nurse contact material layer 150 difficult to understand, form the conductor material layer 160 shown in Fig. 1 D, continue again to carry out backward channel etching (Back ChannelEtching for conductor material layer 160 and nurse contact material layer 150 difficult to understand, BCE) technology is to define the source 170 shown in Fig. 1 E.So far, grid 120, channel layer 140 and source 170 constitute thin-film transistor 100.
The manufacture process of above-mentioned known thin-film transistor 100 is after being formed on the channel layer 140 in regular turn with conductor material layer 160 nurse contact material layer 150 difficult to understand earlier, the mode of utilizing photoetching again is in addition dark etching of nurse contact material layer 150 difficult to understand and conductor material layer 160, and forms source 170.Yet, when making thin-film transistor array (TFT array) substrate of active display assembly with above-mentioned technology, must make each thin-film transistor 100 in the technology of dark etching nurse contact material difficult to understand layer 150, all can expose channel layer 140 fully, can separate fully with drain electrode layer with the source layer of the source 170 of guaranteeing thin-film transistor 100.But, because nurse contact material layer 150 variable thickness difficult to understand of each thin-film transistor 100 are fixed impartial in the array, so tend in the thin thin-film transistor 100 of nurse contact material layer 150 difficult to understand, channel layer 140 be caused the situation of over etching (over-etching), thereby influence the electric performance of channel layer 140.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of method of manufacturing thin film transistor, it can prevent that channel layer is damaged, and promotes the electric performance of thin-film transistor.
Another object of the present invention provides a kind of thin-film transistor, and it utilizes above-mentioned method for fabricating thin film transistor manufacturing to form, and can have preferable electric performance.
A further object of the present invention provides a kind of one pixel structure process method, comprises above-mentioned dot structure with the existing thin-film transistor of better electrical gas meter to produce, and then promotes the operating characteristic of dot structure.
The present invention proposes a kind of method of manufacturing thin film transistor, at first, forms grid on substrate.Then, on substrate, form gate insulation layer with cover gate.Continue it, on gate insulation layer, form source, and this source exposes the part gate insulation layer of grid top.Afterwards, on the part gate insulation layer above the grid, form channel layer.
According to the described method of manufacturing thin film transistor of preferred embodiment of the present invention, the step of above-mentioned formation source for example forms ohmic contact layer for elder generation on gate insulation layer, and ohmic contact layer exposes the part gate insulation layer of grid top.Continue it, on ohmic contact layer, form the source/drain conductor layer.
According to the described method of manufacturing thin film transistor of preferred embodiment of the present invention, the step of above-mentioned formation source is for example for forming nurse contact material layer difficult to understand and conductor material layer in regular turn on gate insulation layer.Continue it, patterned conductor material layer and nurse contact material layer difficult to understand in regular turn are to expose the part gate insulation layer of grid top.Wherein the method for patterned conductor material layer comprises Wet-type etching or dry-etching, and the method for patterning nurse contact material difficult to understand layer comprises Wet-type etching or dry-etching.
According to the described method of manufacturing thin film transistor of preferred embodiment of the present invention, the material of above-mentioned gate insulation layer comprises silicon nitride or silica.
According to the described method of manufacturing thin film transistor of preferred embodiment of the present invention, the material of above-mentioned channel layer comprises amorphous silicon or polysilicon.
The present invention proposes a kind of thin-film transistor, comprises grid, gate insulation layer, source and channel layer.Wherein, grid is arranged on the substrate.Gate insulation layer is arranged on the substrate, and cover grid.Source is arranged on the gate insulation layer, and source exposes the part gate insulation layer of grid top.Channel layer is arranged on the part gate insulation layer of grid top.
According to the described thin-film transistor of preferred embodiment of the present invention, above-mentioned source comprises ohmic contact layer and source/drain conductor layer, and ohmic contact layer is arranged on the gate insulation layer, and ohmic contact layer exposes the part gate insulation layer of grid top.And the source/drain conductor layer is arranged on the ohmic contact layer.
According to the described thin-film transistor of preferred embodiment of the present invention, the material of above-mentioned gate insulation layer comprises silicon nitride or silica.
According to the described thin-film transistor of preferred embodiment of the present invention, the material of above-mentioned channel layer comprises amorphous silicon or polysilicon.
The present invention proposes a kind of one pixel structure process method, at first, form grid and scan line on substrate, and grid connects scan line.Then, on substrate, form gate insulation layer with cover gate and scan line.Continue it, on gate insulation layer, form first source, second source and data line, wherein first source and second source lay respectively at the both sides of the gate insulation layer of grid top, and first source is electrically connected to data line.Afterwards, form channel layer on the gate insulation layer above the grid, wherein grid, channel layer, first source and second source constitute thin-film transistor.Next, on substrate, form protective layer to cover above-mentioned thin-film transistor and data line.And protective layer has opening and exposes part second source.Afterwards, on protective layer, form pixel electrode, and pixel electrode is inserted opening and is electrically connected with second source.
According to the described one pixel structure process method of preferred embodiment of the present invention, above-mentioned formation first source and the step of second source for example form ohmic contact layer for elder generation on gate insulation layer, and ohmic contact layer exposes the part gate insulation layer of grid top.Continue it, on ohmic contact layer, form the source/drain conductor layer.
According to the described one pixel structure process method of preferred embodiment of the present invention, above-mentioned formation first source and the step of second source are for example for forming nurse contact material layer difficult to understand and conductor material layer in regular turn on gate insulation layer.Continue it, patterned conductor material layer and nurse contact material layer difficult to understand in regular turn are to expose the part gate insulation layer of grid top.Wherein the method for patterned conductor material layer comprises Wet-type etching or dry-etching, and the method for patterning nurse contact material difficult to understand layer comprises Wet-type etching or dry-etching.
According to the described one pixel structure process method of preferred embodiment of the present invention, the material of above-mentioned gate insulation layer comprises silicon nitride or silica.
According to the described one pixel structure process method of preferred embodiment of the present invention, the material of above-mentioned channel layer comprises amorphous silicon or polysilicon.
According to the described one pixel structure process method of preferred embodiment of the present invention, the material of above-mentioned protective layer comprises silicon nitride or silica.
According to the described one pixel structure process method of preferred embodiment of the present invention, the material of above-mentioned pixel electrode comprises indium tin oxide or indium-zinc oxide.
The present invention forms channel layer again because form earlier source, therefore can avoid channel layer in the process that forms source because of over etching is damaged, to promote the manufacturing qualification rate of thin film transistor and pixel structure.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Embodiment
Fig. 2 A～2E is the manufacturing process generalized section of a kind of thin-film transistor in the preferred embodiment of the present invention.At first, please refer to Fig. 2 A, on substrate 210, form grid 220.In one embodiment, the method that forms grid 220 for example is prior to deposition one deck conductor layer (not expressing among the figure) on the substrate 210, utilize photomask (not expressing among the figure) to cooperate photoetching process afterwards again, on substrate 210, to form grid 220 with patterning conductor layer.Above-mentioned lithography step is general semiconductor fabrication process, and is therefore known by the person of ordinary skill in the field about the detailed content of these steps, repeats no more in this.
Then, please refer to Fig. 2 B, on substrate 210, form gate insulation layer 230 with cover gate 220.The method that forms gate insulation layer 230 for example is physical vapour deposition (PVD) (physical vapordeposition, PVD) or chemical vapour deposition technique (chemical vapor deposition, CVD), and the material of gate insulation layer 230 for example be silicon nitride or silica.
Continue it, please refer to Fig. 2 C and Fig. 2 D, on gate insulation layer 230, form source 240a, and source 240a exposes the part gate insulation layer 230 of grid 220 tops.In one embodiment, the method for formation source 240a for example is that the following step is described.
At first, please refer to Fig. 2 C, form nurse contact material layer 242 difficult to understand and conductor material layer 244 in regular turn on gate insulation layer 230, in one embodiment, the formation method of nurse contact material layer 242 difficult to understand and conductor material layer 244 for example is physical vapour deposition (PVD) or chemical vapour deposition technique.Then, patterned conductor material layer 244 and nurse contact material layer 242 difficult to understand in regular turn, forming the source 240a shown in Fig. 2 D, and this source 240a exposes the part gate insulation layer 230 of grid 220 tops.In one embodiment, the method for patterned conductor material layer 244 for example is Wet-type etching or dry-etching, and the method for patterning nurse contact material difficult to understand layer 242 for example is Wet-type etching or dry-etching.In a preferred embodiment, it is that mask carries out Wet-type etching to conductor material layer 244 with patterning photoresist layer (not expressing among the figure) earlier for example, to form source/drain conductor layer 244a.Then, be mask with identical patterning photoresist layer (not expressing among the figure) again, nurse contact material layer 242 difficult to understand is carried out dry-etching, with formation ohmic contact layer 242a, and constitute source 240a with source/drain conductor layer 244a.
Afterwards, please refer to Fig. 2 E, on the part gate insulation layer 230 above the grid 220, form channel layer 250a.In one of the present invention preferred embodiment, the formation method of channel layer 250a is for example for being deposited on channel material layer (not expressing among the figure) on the gate insulation layer 230 earlier, and cover source 240a, again this channel material layer is carried out photoetching, to form the channel layer 250a shown in Fig. 2 E.Wherein, the material of channel layer 250a for example is amorphous silicon or polysilicon.
Certainly, in the above-mentioned photoetching process that defines channel layer 250a, also the channel material layer on the source 240a can be removed, so that channel layer 250a only is positioned on the part gate insulation layer 230 of grid 220 tops, as shown in Figure 3.Hence one can see that, and the present invention does not limit channel layer 250a and whether covers source 240a.
Below will describe the thin-film transistor that the present invention forms according to above-mentioned technology manufacturing in detail.
Please continue the E with reference to Fig. 2, thin-film transistor 200 comprises grid 220, gate insulation layer 230, source 240a and channel layer 250a.Wherein, grid 220 is arranged on the substrate 210, and gate insulation layer 230 is arranged on the substrate 210 and cover grid 220.Source 240a is arranged on the gate insulation layer 230, and source 240a exposes the part gate insulation layer 230 of grid 220 tops.Channel layer 250a then is arranged on the part gate insulation layer 230 of grid 220 tops.
In a preferred embodiment, above-mentioned source 240a comprises ohmic contact layer 242a and source/drain conductor layer 244a, wherein ohmic contact layer 242a is arranged on the gate insulation layer 230, and ohmic contact layer 242a exposes the part gate insulation layer 230 of grid 220 tops.Source/drain conductor layer 244a then is arranged on the ohmic contact layer 242a.In addition, the material of gate insulation layer 230 is silicon nitride or silica for example, and the material of channel layer 250a for example is amorphous silicon or polysilicon.
Because the present invention forms earlier source 240a to form channel layer 250a again, therefore can avoid channel layer 250a in the process that forms source 240a because of over etching is damaged, and then it is existing to make channel layer 250a can have a better electrical gas meter.
Fig. 4 is the schematic top plan view of a kind of dot structure of the present invention, and Fig. 5 A～5E is the manufacturing process generalized section of a kind of dot structure of being looked along A-A ' hatching among Fig. 4.
At first, please on substrate 310, form grid 320 and scan line 330 simultaneously with reference to Fig. 4 and Fig. 5 A, and grid 320 connects scan line 330.Then, please refer to Fig. 4 and Fig. 5 B, on substrate 310, form gate insulation layer 340 with cover gate 320 and scan line 330.The method that forms gate insulation layer 340 for example is physical vaporous deposition or chemical vapour deposition technique, and the material of gate insulation layer 340 for example is silicon nitride or silica.
Continue it, please refer to Fig. 4 and Fig. 5 C, on gate insulation layer 340, form first source 352, second source 354 and data line 360, wherein first source 352 and second source 354 lay respectively on the gate insulation layer 340 of top, grid 320 both sides, and first source 352 is electrically connected to data line 360.In one of the present invention preferred embodiment, it is identical or similar with the step of the step of second source 354 and the formation source 240a described in the above-mentioned thin-film transistor 200 to form first source 352, will no longer be given unnecessary details at this.
Afterwards, please be simultaneously with reference to Fig. 4 and Fig. 5 D, on the gate insulation layer above the grid 320 340, form channel layer 370, in one embodiment, the formation method of channel layer 370 is for example for being deposited on channel material layer (not expressing among the figure) on the gate insulation layer 340 with elder generation, and cover first source 352 and second source 354, again this channel material layer is carried out photoetching, on the part gate insulation layer 340 above the grid 320, to form channel layer 370.Wherein, the material of channel layer 370 for example is amorphous silicon or polysilicon.At this, the thin-film transistor 200 that grid 320, channel layer 370, first source 352 and second source 354 constitute in the foregoing description.
Then, please refer to Fig. 4 and Fig. 5 E, on substrate 310, form protective layer 380, and protective layer 380 has opening 382 to expose part second source 354.Wherein, the material of protective layer 380 for example is silicon nitride or silica; and the method for its formation for example is to be deposited on all sidedly on the substrate 310 with physical vaporous deposition or chemical vapour deposition technique earlier; carry out photoetching process again; in protective layer 380, to form opening 382, with second source 354 of expose portion.
Afterwards, please continue, on protective layer 380, form pixel electrode 390, and pixel electrode 390 is inserted opening 382 and is electrically connected with second source 354 with reference to Fig. 4 and Fig. 5 E.Wherein, the material of pixel electrode 390 for example be indium tin oxide (Indium Tin Oxide, ITO) or indium-zinc oxide (Indium Zinc Oxide, IZO), and the method for its formation for example is a sputter.So far after step is finished, be to form dot structure 300.
The manufacture method of above-mentioned dot structure 300 has been adjusted the manufacturing sequence of first source 352 and second source 354 and channel layer 370, therefore can avoid channel layer 370 to be damaged in the etch process that forms first source 352 and second source 354.So the present invention can make has the existing dot structure of better electrical gas meter 300.
In sum, the present invention has following advantage:
(1) the present invention forms source earlier to form channel layer again, therefore can avoid channel layer to be damaged because of over etching in the process that forms source.
(2) the present invention's channel layer is not because of can etchedly destroying, so the present invention's thin-film transistor has preferable electric performance.
(3) the present invention's dot structure, thin-film transistor and manufacture method thereof can promote the manufacturing qualification rate of thin film transistor and pixel structure.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the invention; when can doing a little change and change, so the present invention's protection range is as the criterion when looking the claim person of defining.
Description of drawings
Figure 1A～1E is a kind of manufacturing process generalized section of known thin-film transistor.
Fig. 2 A～2E is the manufacturing process generalized section of a kind of thin-film transistor in the present invention's the preferred embodiment.
Fig. 3 is the generalized section of another kind of thin-film transistor among the present invention's the embodiment.
Fig. 4 is the schematic top plan view of a kind of dot structure of the present invention.
Fig. 5 A～5E is the manufacturing process generalized section of a kind of dot structure of being looked along AA ' hatching among Fig. 4.
The primary clustering description of symbols
100: thin-film transistor
110: substrate
120: grid
130: gate insulation layer
140: channel layer
150: nurse contact material layer difficult to understand
160: conductor material layer
170: source
200: thin-film transistor
210: substrate
220: grid
230: gate insulation layer
240a: source
242: nurse contact material layer difficult to understand
242a: ohmic contact layer
244: conductor material layer
244a: source/drain conductor layer
250a: channel layer
300: dot structure
310: substrate
320: grid
330: scan line
340: gate insulation layer
352: the first source
354: the second source
360: data wire
370: channel layer
380: protective layer
382: opening
390: pixel electrode
A-A ': hatching
Claims (20)
1. method of manufacturing thin film transistor is characterized in that comprising:
On substrate, form grid;
On this substrate, form gate insulation layer to cover this grid;
Form source on this gate insulation layer, this source exposes this gate insulation layer of part of this grid top; And
On this gate insulation layer of the part above this grid, form channel layer.
2. the method for manufacturing thin film transistor according to claim 1 is characterized in that the step that forms this source comprises:
On this gate insulation layer, form ohmic contact layer, and this ohmic contact layer exposes this gate insulation layer of part of this grid top; And
On this ohmic contact layer, form the source/drain conductor layer.
3. the method for manufacturing thin film transistor according to claim 2 is characterized in that the step that forms this source comprises:
On this gate insulation layer, form nurse contact material layer difficult to understand and conductor material layer in regular turn; And
This conductor material layer of patterning and this Austria's nurse contact material layer in regular turn are to expose this gate insulation layer of part of this grid top.
4. the method for manufacturing thin film transistor according to claim 3 is characterized in that the method that patterning should Austria's nurse contact material layer comprises Wet-type etching or dry-etching.
5. the method for manufacturing thin film transistor according to claim 3 is characterized in that the method for this conductor material layer of patterning comprises Wet-type etching or dry-etching.
6. the method for manufacturing thin film transistor according to claim 1 is characterized in that the material of this gate insulation layer comprises silicon nitride or silica.
7. the method for manufacturing thin film transistor according to claim 1 is characterized in that the material of this channel layer comprises amorphous silicon or polysilicon.
8. thin-film transistor is characterized in that comprising:
Grid is arranged on the substrate;
Gate insulation layer is arranged on this substrate, and this gate insulation layer covers this grid;
Source is arranged on this gate insulation layer, and this source exposes this gate insulation layer of part of this grid top; And
Channel layer is arranged on this gate insulation layer of part of this grid top.
9. described according to Claim 8 thin-film transistor is characterized in that this source comprises:
Ohmic contact layer is arranged on this gate insulation layer, and this ohmic contact layer exposes this gate insulation layer of part of this grid top; And
The source/drain conductor layer is arranged on this ohmic contact layer.
10. described according to Claim 8 thin-film transistor is characterized in that the material of this gate insulation layer comprises silicon nitride or silica.
11. described according to Claim 8 thin-film transistor is characterized in that the material of this channel layer comprises amorphous silicon or polysilicon.
12. an one pixel structure process method is characterized in that comprising:
On substrate, form grid and scan line, and this grid connects this scan line;
On this substrate, form gate insulation layer to cover this grid and this scan line;
On this gate insulation layer, form first source, second source and data line, wherein this first source and this second source lay respectively on this gate insulation layer of this top, grid both sides, and this first source is electrically connected to this data line;
Form channel layer on this gate insulation layer above this grid, wherein this grid, this channel layer, this first source and this second source constitute thin-film transistor;
On this substrate, form protective layer covering this thin-film transistor and this data wire, and have opening in this protective layer and expose partly this second source; And
On this protective layer, form pixel electrode, and this pixel electrode is inserted this opening and is electrically connected with this second source.
13. the one pixel structure process method according to claim 12 is characterized in that the step that forms this first source and this second source comprises:
On this gate insulation layer, form ohmic contact layer, and this ohmic contact layer and this gate insulation layer that exposes this grid top; And
On this ohmic contact layer, form the source/drain conductor layer.
14. the one pixel structure process method according to claim 13 is characterized in that the step that forms this first source and second source comprises:
On this gate insulation layer, form nurse contact material layer difficult to understand and conductor material layer in regular turn; And
This conductor material layer of patterning and this Austria's nurse contact material layer in regular turn are to form this first source and second source.
15. the one pixel structure process method according to claim 14 is characterized in that the method that patterning should Austria's nurse contact material layer comprises Wet-type etching or dry-etching.
16. the one pixel structure process method according to claim 14 is characterized in that the method for this conductor material layer of patterning comprises Wet-type etching or dry-etching.
17. the one pixel structure process method according to claim 12 is characterized in that the material of this gate insulation layer comprises silicon nitride or silica.
18. the one pixel structure process method according to claim 12 is characterized in that the material of this channel layer comprises amorphous silicon or polysilicon.
19. the one pixel structure process method according to claim 12 is characterized in that the material of this protective layer comprises silicon nitride or silica.
20., it is characterized in that the material of this pixel electrode comprises indium tin oxide or indium-zinc oxide according to claim 12 a described one pixel structure process method.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510007379 CN1822333A (en) | 2005-02-16 | 2005-02-16 | Thin film transistor, method for producing thin film transistor and pixel structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510007379 CN1822333A (en) | 2005-02-16 | 2005-02-16 | Thin film transistor, method for producing thin film transistor and pixel structure |
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| CN1822333A true CN1822333A (en) | 2006-08-23 |
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| CN 200510007379 Pending CN1822333A (en) | 2005-02-16 | 2005-02-16 | Thin film transistor, method for producing thin film transistor and pixel structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237411A (en) * | 2010-05-05 | 2011-11-09 | 元太科技工业股份有限公司 | Oxide thin film transistor and manufacturing method thereof |
| CN106206606A (en) * | 2016-08-08 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display floater, display device |
-
2005
- 2005-02-16 CN CN 200510007379 patent/CN1822333A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237411A (en) * | 2010-05-05 | 2011-11-09 | 元太科技工业股份有限公司 | Oxide thin film transistor and manufacturing method thereof |
| CN106206606A (en) * | 2016-08-08 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display floater, display device |
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