CN1818830A - Power-supply saving method and system for central processing unit - Google Patents
Power-supply saving method and system for central processing unit Download PDFInfo
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- CN1818830A CN1818830A CN 200610058293 CN200610058293A CN1818830A CN 1818830 A CN1818830 A CN 1818830A CN 200610058293 CN200610058293 CN 200610058293 CN 200610058293 A CN200610058293 A CN 200610058293A CN 1818830 A CN1818830 A CN 1818830A
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Abstract
An energy-saving method of central processing unit includes driving central processing unit to depart from dormant state of non-snoop event by system chip and entering a processing state for executing command as well as entering a system management mode when said unit is in dormant state of non-snoop event and requested event of bus bar main controller is sent out by peripheral device; then transmitting the requested event to control processing unit by arbitrator, driving said unit to be at dormant state of non-snoop event by closing arbitrator and executing an interruption program in system management after the requested event is processed .
Description
Technical field
The present invention relates to a kind of saving power source method and system, particularly relate to a kind of saving power source method and system of CPU (central processing unit), to save the power supply of CPU (central processing unit).
Background technology
Along with the progress of computing machine (computer) systems technology, the function that computer system had is more and more for powerful thorough, also because of so bringing the considerable facility of the common people now.So computer system also can provide the common people to amuse and divert oneself except can helping common people's processing transactions because developed towards the multimedia service direction now.The computer system functions big thorough relative central processing unit for processing speed that tends to become strong more also promotes day by day now, so the power supply that CPU (central processing unit) consumed also increases day by day, this is for must being a major issue by battery powered portable computer.Because the electrical source consumption of battery can reduce the time that portable computer uses soon relatively, so can on the use portable computer, impact using the common people.
Computer system all is provided with power-supply management system now for the foregoing reasons, Chang Yong power-supply management system has Advanced Program Zoom (Advanced Power Management now, APM) with advanced framework power supply interface (Advanced Configuration and Power Interface, ACPI) two kinds, wherein to carry out ACPI efficient the best of power management by operating system.The ACPI power management is divided into four kinds of states, is respectively system state G (Global), unit state D (Device), dormant state S (Sleeping) and CPU (central processing unit) state C (CPU).
Seeing also shown in Figure 1ly, is the CPU (central processing unit) constitutional diagram of the advanced framework power supply interface of existing known techniques.As shown in the figure, the CPU (central processing unit) state of ACPI includes C0, C1, C2, C3 four levels, the C0 state is the treatment state of CPU (central processing unit) executable instruction, and C1, C2, C3 state are respectively the various level dormant state, and the operating system of computer system can be ordered about CPU (central processing unit) according to the user mode of CPU (central processing unit) and be entered the dormant state of suitable level to save power supply.
In above-mentioned C1, C2 and the C3 state, because the C3 state is for spying on the dormant state of (non-snoop) incident, so CPU (central processing unit) is to handle any incident when being in the C3 state, and is in complete dormant state, so the C3 state is the dormant state of power saving.The System on chip that CPU (central processing unit) enters computer system behind the C3 state receive couple peripheral device sent one interrupts (Interrupt) incident or a bus-bar primary controller when requiring (Bus Master Request) incident, CPU (central processing unit) promptly can be left the C3 state and return back to the C0 state with handling interrupt incident or bus-bar primary controller requirement incident.Afterwards, when the user mode of CPU (central processing unit) must reach the condition that enters the C3 state, operating system just can be ordered about CPU (central processing unit) once again and be entered the C3 state.
But, it only is that (memory body is a storage medium to peripheral device desire reading system memory body that the bus-bar primary controller requires incident, storer, internal memory, below all be called memory body) data and the processing events sent, but owing to leaving the C3 state to the C0 state in order to handle this incident, wait for again afterwards after CPU (central processing unit) reaches the condition that enters C3 just being entered the C3 state that Central Processing Unit is treated to wait for that at the C0 state time that enters the C3 state will cause CPU (central processing unit) to expend more power supply in this.So CPU (central processing unit) can't reach maximum province's electrical efficiency, this problem will reduce service time portable computer, and can impact on the use portable computer the user.
This shows that the saving power source method of above-mentioned existing CPU (central processing unit) and system obviously still have inconvenience and defective, and demand urgently further being improved in method, product structure and use.In order to address the above problem, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and conventional method and product do not have appropriate method and structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found a kind of saving power source method and system of new CPU (central processing unit), just become the current industry utmost point to need improved target.
Because there are defective in the saving power source method and the system of above-mentioned existing CPU (central processing unit), therefore, the present invention is directed to the problems referred to above and propose a kind of saving power source method and system of new CPU (central processing unit), allow the CPU (central processing unit) can be after the dormant state of leaving the incident of can't spying on is handled the bus-bar primary controller and required incident, return back to the dormant state of the incident of can't spying on immediately, using increases the service time of economizing electrical efficiency and then improving portable computer, to address the above problem.
Summary of the invention
Fundamental purpose of the present invention is, overcome the saving power source method of existing CPU (central processing unit) and the defective that system exists, and provide a kind of saving power source method and system of new CPU (central processing unit), technical matters to be solved is to make it allow CPU (central processing unit) under the dormant state that is in the incident of can't spying on and peripheral device when sending the bus-bar primary controller and requiring incident, the dormant state of leaving the incident of can't spying on enters the treatment state of executable instruction and enters a System Management Mode, require incident to handle the bus-bar primary controller, and after finishing processing, order about the dormant state that CPU (central processing unit) is returned the incident of can't spying in System Management Mode executive system management interrupt formula by CPU (central processing unit), and can reach best purpose of power saving, thereby be suitable for practicality more.
The object of the invention to solve the technical problems is to adopt following technical scheme to realize.The saving power source method of a kind of CPU (central processing unit) that proposes according to the present invention, when applying to a CPU (central processing unit) and being in a C3 state and a peripheral device and sending a bus-bar primary controller requirement incident, this method comprises the steps: to send one first control message and a system management interrupt message to this CPU (central processing unit), orders about this CPU (central processing unit) and leaves this C3 state and enter a C0 state and a System Management Mode; And open a moderator, handle to transmit this bus-bar primary controller requirement incident to this CPU (central processing unit); Wherein, when intact this bus-bar primary controller of this central processing unit for processing requires incident, close this moderator and carry out a system management interrupt formula, order about this CPU (central processing unit) and reply this C3 state that enters to send one second control message to this CPU (central processing unit).
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The saving power source method of aforesaid CPU (central processing unit), it more comprises to the step of this CPU (central processing unit) for wherein said transmission one first a control message and a system management interrupt message: write one first setting value to, first working storage, this CPU (central processing unit) is after handling this bus-bar primary controller requirement incident, this first setting value then is eliminated, after this CPU (central processing unit) is detected this first setting value and is eliminated, carry out this system management interrupt formula.
The saving power source method of aforesaid CPU (central processing unit), after wherein said CPU (central processing unit) is replied and is entered this C3 state, when if this peripheral device sends an interrupt event, this CPU (central processing unit) is left this System Management Mode, and send this first control message to this CPU (central processing unit) enter this C0 state and open this moderator to leave this C3 state, handle to transmit this interrupt event to this CPU (central processing unit).
The saving power source method of aforesaid CPU (central processing unit), when wherein said peripheral device sends this interrupt event, write one second setting value to, second working storage, this CPU (central processing unit) is left this System Management Mode and is removed this second setting value according to this second setting value.
The saving power source method of aforesaid CPU (central processing unit), wherein said system management interrupt formula is stored in a memory body.
The object of the invention to solve the technical problems also realizes by the following technical solutions.The saving power source method of a kind of CPU (central processing unit) that proposes according to the present invention, apply to a CPU (central processing unit) and be in one can't spy on the dormant state of (non-snoop) incident and a peripheral device and send a bus-bar primary controller and require incident the time, this method comprises the steps: to send one first control message and a system management interrupt message to this CPU (central processing unit), orders about this CPU (central processing unit) and leaves a treatment state and the System Management Mode that this dormant state that can't spy on incident enters an executable instruction; And open a moderator, handle to transmit this bus-bar primary controller requirement incident to this CPU (central processing unit); Wherein, when intact this bus-bar primary controller of this central processing unit for processing requires incident, close this moderator and carry out a system management interrupt formula, order about this CPU (central processing unit) answer and enter the dormant state that this can't spy on incident to send one second control message to this CPU (central processing unit).
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The saving power source method of aforesaid CPU (central processing unit), it more comprises to the step of this CPU (central processing unit) for wherein said transmission one first a control message and a system management interrupt message: write one first setting value to, first working storage, this CPU (central processing unit) is after handling this bus-bar primary controller requirement incident, this first setting value then is eliminated, after this CPU (central processing unit) is detected this first setting value and is eliminated, carry out this system management interrupt formula.
The saving power source method of aforesaid CPU (central processing unit), after wherein said CPU (central processing unit) is replied and is entered this dormant state that can't spy on incident, when if this peripheral device sends an interrupt event, this CPU (central processing unit) is left this System Management Mode, and send this first control message to this CPU (central processing unit) enter the treatment state of this executable instruction and open this moderator to leave this dormant state that can't spy on incident, handle to transmit this interrupt event to this CPU (central processing unit).
The saving power source method of aforesaid CPU (central processing unit), when wherein said peripheral device sends this interrupt event, write one second setting value to, second working storage, this CPU (central processing unit) is left this System Management Mode and is removed this second setting value according to this second setting value.
The saving power source method of aforesaid CPU (central processing unit), wherein said system management interrupt formula is stored in a memory body.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.The saving power-supply system of a kind of CPU (central processing unit) that proposes according to the present invention, apply to a CPU (central processing unit) and be in one can't spy on the dormant state of (non-snoop) incident and a peripheral device and send a bus-bar primary controller and require incident the time, this system includes: a memory body, store a break in service formula, carry out for this CPU (central processing unit); One moderator transmits this bus-bar primary controller requirement incident to this CPU (central processing unit); An and System on chip, send one first a control message and a system management interrupt message to this CPU (central processing unit), order about this CPU (central processing unit) and leave a treatment state and the System Management Mode that this can't be spied on the dormant state of incident and enter an executable instruction, to handle this bus-bar primary controller requirement incident; Wherein, when this CPU (central processing unit) enters the treatment state of this executable instruction, opening this moderator transmits this bus-bar primary controller requirement incident to this CPU (central processing unit) and handles, when handling this bus-bar primary controller requirement incident, close this moderator and carry out this system management interrupt formula, order about this CPU (central processing unit) answer and enter the dormant state that this can't spy on incident to send one second control message to this CPU (central processing unit).
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The saving power-supply system of aforesaid CPU (central processing unit), it more includes: one first working storage, store one first setting value, when this System on chip sends this system management interrupt message, and write this first setting value to this first working storage, then remove this first setting value after intact this bus-bar primary controller requirement incident of this central processing unit for processing, after this CPU (central processing unit) is detected this first setting value and is eliminated, carry out this system management interrupt formula.
The saving power-supply system of aforesaid CPU (central processing unit), wherein said first working storage is arranged at this System on chip.
The saving power-supply system of aforesaid CPU (central processing unit), after wherein said CPU (central processing unit) is replied and is entered this dormant state that can't spy on incident, when if this peripheral device sends an interrupt event, this CPU (central processing unit) is left this System Management Mode, this System on chip and send this first control message to this CPU (central processing unit) enter the treatment state of this executable instruction and open this moderator to leave this dormant state that can't spy on incident, handle to transmit this interrupt event to this CPU (central processing unit).
The saving power-supply system of aforesaid CPU (central processing unit), it more includes: one second working storage, store one second setting value, when this peripheral device sends this interrupt event, this System on chip writes one second setting value to this second working storage, and this CPU (central processing unit) is left this System Management Mode and removed this second setting value according to this second setting value.
The saving power-supply system of aforesaid CPU (central processing unit), wherein said second working storage is arranged at this System on chip.
The saving power-supply system of aforesaid CPU (central processing unit), wherein said moderator is arranged at this System on chip.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, the saving power source method and the system of CPU (central processing unit) of the present invention are when mainly applying to CPU (central processing unit) and being in the C3 state of the incident of can't spying on and a peripheral device and sending a bus-bar primary controller and require incident to desire to handle.The present invention sends one first control message and a system management interrupt message to CPU (central processing unit) by a System on chip, leaves a C0 state and the System Management Mode that the C3 state enters an executable instruction to order about CPU (central processing unit); Afterwards, opening a moderator handles with transmission bus-bar primary controller requirement incident to CPU (central processing unit).After CPU (central processing unit) is finished dealing with bus-bar primary controller requirement incident, promptly close moderator and carry out a system management interrupt formula and recover to enter the C3 state, and then can reach purpose of power saving to order about CPU (central processing unit).After CPU (central processing unit) was returned the C3 state, if when peripheral device sends an interrupt event and desires to handle, CPU (central processing unit) was left System Management Mode, and left the C3 state and enter the C0 state with the handling interrupt incident.
By technique scheme, the saving power source method and the system of CPU (central processing unit) of the present invention have following advantage at least: the present invention is mainly used in that CPU (central processing unit) enters behind the C3 state of the incident of can't spying on if peripheral device sends the bus-bar primary controller when requiring incident, the present invention allows CPU (central processing unit) leave the treatment state that the C3 state enters executable instruction and requires incident to handle the bus-bar primary controller, and enters System Management Mode with separating operation system keyholed back plate.So CPU (central processing unit) can be ordered about CPU (central processing unit) and return the C3 state that enters immediately by CPU (central processing unit) in System Management Mode executive system management interrupt formula after finishing processing bus-bar primary controller requirement incident.So promptly can reduce CPU (central processing unit) loss electric energy, and then can reach purpose of energy saving, can increase the cruising time of the battery of portable computer.The present invention can also save the power consumption of desktop PC in addition, and then improves and to reach the computing machine purpose of energy saving, is very suitable for practicality.
In sum, the present invention is the saving power source method and the system of relevant a kind of CPU (central processing unit), be used for a CPU (central processing unit) and be in the dormant state that to spy on (non-snoop) incident, and when a peripheral device sent a bus-bar primary controller requirement incident, a System on chip of the present invention ordered about CPU (central processing unit) earlier and leaves a treatment state and the System Management Mode that the dormant state of the incident of can't spying on enters an executable instruction; Afterwards, opening a moderator handles with transmission bus-bar primary controller requirement incident to CPU (central processing unit).After CPU (central processing unit) is handled bus-bar primary controller requirement incident, promptly close moderator and carry out a system management interrupt formula, recover to enter the dormant state of the incident of can't spying on, so promptly can reach best purpose of power saving to order about CPU (central processing unit).The present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on method, product structure or function, have technically than much progress, and produced handy and practical effect, and the effect that the saving power source method of more existing CPU (central processing unit) and system have enhancement, thereby being suitable for practicality more, and having the extensive value of industry, really is a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the CPU (central processing unit) constitutional diagram of the advanced framework power supply interface of existing known techniques.
Fig. 2 is the calcspar of a preferred embodiment of the present invention.
Fig. 3 is the process flow diagram of a preferred embodiment of the present invention.
10: CPU (central processing unit) 30: System on chip
31: peripheral device 33: moderator
37: the second working storages of 35: the first working storages
39: systematic memory body 40: read-only memory
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, saving power source method and its embodiment of system, method, step, structure, feature and the effect thereof of the CPU (central processing unit) that foundation the present invention is proposed, describe in detail as after.
Seeing also shown in Figure 2ly, is the calcspar of a preferred embodiment of the present invention.As shown in the figure, the embodiment of the invention includes a CPU (central processing unit) 10, a System on chip 30 and a systematic memory body 39.This System on chip 30 couples to transmit message and data with CPU (central processing unit) 10 and systematic memory body 39 respectively.In addition, this System on chip 30 more is coupled with a read-only memory 40 and a peripheral device 31, and is provided with a moderator 33, one first working storage 35 and one second working storage 37.Read-only memory 40 stores a system management interrupt formula.Above-mentioned only is one embodiment of the invention, first working storage 35 and second working storage 37 is non-only can be located at System on chip 30.
When CPU (central processing unit) 10 enters the C3 state that can't spy on (noon-snoopZ) incident, in order to allow System on chip 30 can't transmit processing events that peripheral device 31 sent to this CPU (central processing unit) 10, so CPU (central processing unit) 10 is before entering the C3 state of the incident of can't spying on, System on chip 30 can be closed moderator 33, make CPU (central processing unit) 10 can't be sent to CPU (central processing unit) 10 by the moderator 33 of System on chip 30 entering the processing events that C3 state rear perimeter edge device 31 sends, allow CPU (central processing unit) 10 spy on processing events and be in complete dormant state.
Next please cooperate consult shown in Figure 3, illustrate that the present invention enters the C3 state of the incident of can't spying in CPU (central processing unit) 10 after, the disposal route when System on chip 30 receives bus-bar primary controller that peripheral devices 31 are sent and requires incident.CPU (central processing unit) 10 is to be in the C3 state shown in step S0 now, and moderator 33 has been a closed condition as above stated specification.At this moment, if System on chip 30 is shown in step S1, when the bus-bar primary controller that reception peripheral device 31 is sent requires incident, System on chip 30 is execution in step S2, send one first control message and a system management interrupt (SystemManagement Interrupt, SMI) message is to CPU (central processing unit) 10 and write one first setting value to the first working storage 35, to record bus-bar primary controller requirement incident.
To leave the C0 state that the C3 state enters to executable instruction when CPU (central processing unit) 10 receives the first control message, and according to the system management interrupt message that is received enter a System Management Mode (System Management Mode, SMM).System on chip 30 transmitting system management interrupt messages of the present invention to the reason of CPU (central processing unit) 10 is, after CPU (central processing unit) 10 is left the C3 state and is entered the C0 state immediately, the operating system that can be controlled by computer system just can't be returned the C3 state immediately because of Central Processing Unit 10 in this after handling bus-bar primary controller requirement incident.So System on chip 30 of the present invention also transmitting system management interrupt message when sending the first control message is ordered about CPU (central processing unit) 10 and is entered System Management Mode and allow CPU (central processing unit) 10 separating operation system keyholed back plates.
Because flog system wafer 30 transmitting system management interrupt messages are a lot of to the trigger event of CPU (central processing unit) 10, so each trigger event can write setting value at relative working storage in flog system wafer 30 transmitting system management interrupt messages during to CPU (central processing unit) 10,, after entering System Management Mode, detect all working storages and carry out the system management interrupt formula that is stored in read-only memory 40 with the foundation setting value for CPU (central processing unit) 10.Hence one can see that, and CPU (central processing unit) 10 needs spended time to detect the working storage of all trigger event correspondences after entering System Management Mode.The present invention promptly opens moderator 33 by this detecting time, handles with transmission bus-bar primary controller incident to CPU (central processing unit) 10.When detecting first setting value, CPU (central processing unit) 10 of the present invention learnt bus-bar primary controller requirement incident, thus executive system management interrupt formula not, till handling bus-bar primary controller requirement incident and removing first setting value.
By as can be known aforementioned, when CPU (central processing unit) 10 is left the C3 state and is entered C0 state and System Management Mode, System on chip 30 is with execution in step S3, open moderator 33, require event transmission to CPU (central processing unit) 10 to handle with the bus-bar primary controller that allows peripheral device 31 send, and detect first setting value.When CPU (central processing unit) 10 finish handle bus-bar primary controller requirement incident after, System on chip 30 is execution in step S4, closes moderator 33 and removes first setting value of first working storage 35.At this moment, CPU (central processing unit) 10 promptly can detect first setting value and be eliminated, and bus-bar primary controller requirement incident has been handled in expression.
Then, CPU (central processing unit) 10 is shown in step S5, and executive system management interrupt formula, system management interrupt formula of the present invention are to order about CPU (central processing unit) 10 to return the C3 state.When CPU (central processing unit) 10 was carried out system management interrupt formula of the present invention, CPU (central processing unit) 10 can send one second control message to CPU (central processing unit) 10 by flog system wafers 30, allows CPU (central processing unit) 10 reply the C3 state that enters.When CPU (central processing unit) 10 was carried out the break in service formulas, (System ManagementRAM SMRAM), and then carried out the break in service formula can to read break in service formula to the system management random access memory of read-only memory 40 earlier.The system management random access memory is the specific storage scope of systematic memory body 37.
By as can be known aforementioned, the present invention enters System Management Mode separating operation system keyholed back plate by ordering about CPU (central processing unit) 10, so promptly not can as the existing located by prior art because of be subjected to the operating system keyholed back plate after CPU (central processing unit) 10 is finished processing bus-bar primary controller incident, can't return back to the C3 state at once, so the present invention can be than more power saving of prior art.
After the CPU (central processing unit) 10 execution of step S5, when sending a processing events again as if peripheral device 31,30 execution in step S6 of System on chip, whether the judgment processing incident is an interrupt event.If this processing events is not interrupt event System on chip 30 execution in step S7 then when being bus-bar primary controller requirement incident, send first control message to the CPU (central processing unit) 10 and leave the C3 state to order about CPU (central processing unit) 10, and write first setting value to the first working storage 35, and the flow process of returning step S3 is to repeat above-mentioned steps S3～S5.
If CPU (central processing unit) 10 must be left System Management Mode when this processing events was interrupt event, and returned back to operating system keyholed back plate pattern with the handling interrupt incident.At this moment, the present invention writes one second setting value to the second working storage 37 by System on chip 30 execution in step S8; Afterwards, CPU (central processing unit) 10 can be shown in step S9, detect second setting value that second working storage 37 deposited and shown in step S10, leave System Management Mode and return back to operating system keyholed back plate pattern according to second setting value, and remove second setting value of second working storage 37 simultaneously.In addition, System on chip 30 can send the first control message to CPU (central processing unit) 10, returns back to the C0 state of normal executable instruction to order about CPU (central processing unit) 10 to leave the C3 state.This moment, CPU (central processing unit) 10 was because of returning back to operating system keyholed back plate pattern, and operating system can be opened moderators 33 by flog system wafer 30, with transmit interrupt event to CPU (central processing unit) 10 to handle.
When this processing events is that interrupt event and CPU (central processing unit) 10 are must leave System Management Mode the time, the present invention also can directly order about CPU (central processing unit) 10 by System on chip 30 and leave System Management Mode, and send the first control message to CPU (central processing unit) 10, return back to the C0 state to order about CPU (central processing unit) 10 to leave the C3 state, and must execution in step S8～S10.
In sum, the saving power source method and the system of CPU (central processing unit) of the present invention, be mainly used in that CPU (central processing unit) enters behind the C3 state of the incident of can't spying on if peripheral device sends the bus-bar primary controller when requiring incident, the present invention allows CPU (central processing unit) leave the treatment state that the C3 state enters executable instruction and requires incident to handle the bus-bar primary controller, and enters System Management Mode with separating operation system keyholed back plate.So CPU (central processing unit) can be ordered about CPU (central processing unit) and return the C3 state that enters immediately by CPU (central processing unit) in System Management Mode executive system management interrupt formula after finishing processing bus-bar primary controller requirement incident.So can reduce CPU (central processing unit) loss electric energy, and then reach purpose of energy saving, with the cruising time of the battery that increases portable computer, the present invention also can save the power consumption of desktop PC and then improve and reach the computing machine purpose of energy saving.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (17)
1, a kind of saving power source method of CPU (central processing unit) when applying to a CPU (central processing unit) and being in a C3 state and a peripheral device and sending a bus-bar primary controller requirement incident, is characterized in that this method may further comprise the steps:
Send one first control message and a system management interrupt message to this CPU (central processing unit), order about this CPU (central processing unit) and leave this C3 state and enter a C0 state and a System Management Mode; And
Open a moderator, handle to transmit this bus-bar primary controller requirement incident to this CPU (central processing unit);
Wherein, when intact this bus-bar primary controller of this central processing unit for processing requires incident, close this moderator and carry out a system management interrupt formula, order about this CPU (central processing unit) and reply this C3 state that enters to send one second control message to this CPU (central processing unit).
2, the saving power source method of CPU (central processing unit) according to claim 1, it is characterized in that wherein said transmission one first a control message and a system management interrupt message to the step of this CPU (central processing unit) more comprises: write one first setting value to, first working storage, after intact this bus-bar primary controller requirement incident of this central processing unit for processing, this first setting value then is eliminated, after this CPU (central processing unit) is detected this first setting value and is eliminated, carry out this system management interrupt formula.
3, the saving power source method of CPU (central processing unit) according to claim 1, after it is characterized in that wherein said CPU (central processing unit) answer enters this C3 state, when if this peripheral device sends an interrupt event, this CPU (central processing unit) is left this System Management Mode, and send this first control message to this CPU (central processing unit) enter this C0 state and open this moderator to leave this C3 state, handle to transmit this interrupt event to this CPU (central processing unit).
4, the saving power source method of CPU (central processing unit) according to claim 3, when it is characterized in that wherein said peripheral device sends this interrupt event, write one second setting value to, second working storage, this CPU (central processing unit) is left this System Management Mode and is removed this second setting value according to this second setting value.
5, the saving power source method of CPU (central processing unit) according to claim 1 is characterized in that wherein said system management interrupt formula is stored in a memory body.
6, a kind of saving power source method of CPU (central processing unit), apply to a CPU (central processing unit) and be in one can't spy on the dormant state of (non-snoop) incident and a peripheral device and send a bus-bar primary controller and require incident the time, it is characterized in that this method may further comprise the steps:
Send one first a control message and a system management interrupt message to this CPU (central processing unit), order about this CPU (central processing unit) and leave a treatment state and the System Management Mode that this dormant state that can't spy on incident enters an executable instruction; And
Open a moderator, handle to transmit this bus-bar primary controller requirement incident to this CPU (central processing unit);
Wherein, when intact this bus-bar primary controller of this central processing unit for processing requires incident, close this moderator and carry out a system management interrupt formula, order about this CPU (central processing unit) answer and enter the dormant state that this can't spy on incident to send one second control message to this CPU (central processing unit).
7, the saving power source method of CPU (central processing unit) according to claim 6, it is characterized in that wherein said transmission one first a control message and a system management interrupt message to the step of this CPU (central processing unit) more comprises: write one first setting value to, first working storage, after intact this bus-bar primary controller requirement incident of this central processing unit for processing, this first setting value then is eliminated, after this CPU (central processing unit) is detected this first setting value and is eliminated, carry out this system management interrupt formula.
8, the saving power source method of CPU (central processing unit) according to claim 6, after it is characterized in that wherein said CPU (central processing unit) answer enters this dormant state that can't spy on incident, when if this peripheral device sends an interrupt event, this CPU (central processing unit) is left this System Management Mode, and send this first control message to this CPU (central processing unit) enter the treatment state of this executable instruction and open this moderator to leave this dormant state that can't spy on incident, handle to transmit this interrupt event to this CPU (central processing unit).
9, the saving power source method of CPU (central processing unit) according to claim 8, when it is characterized in that wherein said peripheral device sends this interrupt event, write one second setting value to, second working storage, this CPU (central processing unit) is left this System Management Mode and is removed this second setting value according to this second setting value.
10, the saving power source method of CPU (central processing unit) according to claim 6 is characterized in that wherein said system management interrupt formula is stored in a memory body.
11, a kind of saving power-supply system of CPU (central processing unit), apply to a CPU (central processing unit) and be in one can't spy on the dormant state of (non-snoop) incident and a peripheral device and send a bus-bar primary controller and require incident the time, it is characterized in that this system includes:
One memory body stores a break in service formula, carries out for this CPU (central processing unit);
One moderator transmits this bus-bar primary controller requirement incident to this CPU (central processing unit); And
One System on chip, send one first a control message and a system management interrupt message to this CPU (central processing unit), order about this CPU (central processing unit) and leave a treatment state and the System Management Mode that this can't be spied on the dormant state of incident and enter an executable instruction, to handle this bus-bar primary controller requirement incident;
Wherein, when this CPU (central processing unit) enters the treatment state of this executable instruction, opening this moderator transmits this bus-bar primary controller requirement incident to this CPU (central processing unit) and handles, when handling this bus-bar primary controller requirement incident, close this moderator and carry out this system management interrupt formula, order about this CPU (central processing unit) answer and enter the dormant state that this can't spy on incident to send one second control message to this CPU (central processing unit).
12, the saving power-supply system of CPU (central processing unit) according to claim 11 is characterized in that it more includes:
One first working storage, store one first setting value, when this System on chip sends this system management interrupt message, and write this first setting value to this first working storage, then remove this first setting value after intact this bus-bar primary controller requirement incident of this central processing unit for processing, after this CPU (central processing unit) is detected this first setting value and is eliminated, carry out this system management interrupt formula.
13, the saving power-supply system of CPU (central processing unit) according to claim 12 is characterized in that wherein said first working storage is arranged at this System on chip.
14, the saving power-supply system of CPU (central processing unit) according to claim 11, after it is characterized in that wherein said CPU (central processing unit) answer enters this dormant state that can't spy on incident, when if this peripheral device sends an interrupt event, this CPU (central processing unit) is left this System Management Mode, this System on chip and send this first control message to this CPU (central processing unit) enter the treatment state of this executable instruction and open this moderator to leave this dormant state that can't spy on incident, handle to transmit this interrupt event to this CPU (central processing unit).
15, the saving power-supply system of CPU (central processing unit) according to claim 14 is characterized in that it more includes:
One second working storage, store one second setting value, when this peripheral device sent this interrupt event, this System on chip write one second setting value to this second working storage, and this CPU (central processing unit) is left this System Management Mode and removed this second setting value according to this second setting value.
16, the saving power-supply system of CPU (central processing unit) according to claim 15 is characterized in that wherein said second working storage is arranged at this System on chip.
17, the saving power-supply system of CPU (central processing unit) according to claim 11 is characterized in that wherein said moderator is arranged at this System on chip.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100435071C (en) * | 2006-09-19 | 2008-11-19 | 威盛电子股份有限公司 | Electricity-saving method and system of central processor |
| CN101881994A (en) * | 2009-05-06 | 2010-11-10 | 鸿富锦精密工业（深圳）有限公司 | Energy-saving control system and control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5740454A (en) * | 1995-12-20 | 1998-04-14 | Compaq Computer Corporation | Circuit for setting computer system bus signals to predetermined states in low power mode |
| DE19882269T1 (en) * | 1997-03-31 | 2000-05-11 | Intel Corp | Automatic transition between ACPI-C3 and -C2 states |
| JP2000039937A (en) * | 1998-07-22 | 2000-02-08 | Toshiba Corp | Computer system and its power-saving control method |
| US6633987B2 (en) * | 2000-03-24 | 2003-10-14 | Intel Corporation | Method and apparatus to implement the ACPI(advanced configuration and power interface) C3 state in a RDRAM based system |
| CN100452005C (en) * | 2003-10-28 | 2009-01-14 | 威盛电子股份有限公司 | System and method for controlling interrput |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100435071C (en) * | 2006-09-19 | 2008-11-19 | 威盛电子股份有限公司 | Electricity-saving method and system of central processor |
| CN101881994A (en) * | 2009-05-06 | 2010-11-10 | 鸿富锦精密工业（深圳）有限公司 | Energy-saving control system and control method |
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