CN1812318A - Access buffer storaging method - Google Patents
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- CN1812318A CN1812318A CN 200510002617 CN200510002617A CN1812318A CN 1812318 A CN1812318 A CN 1812318A CN 200510002617 CN200510002617 CN 200510002617 CN 200510002617 A CN200510002617 A CN 200510002617A CN 1812318 A CN1812318 A CN 1812318A
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Abstract
This invention discloses a kind of method for accessing buffer store. Through arranging n buffer cells, write clock identification signal which cycle is n times write clock cycle and read clock identification signal which cycle is n times read clock cycle on the first-in first-out buffer, all the buffer cells are undertaken write operation successively during write clock signal cycle. When writing the first buffer cell, the write clock signal is high level, the others are low level; the write clock identification signals are sampled during the rising edge of each write clock cycle, which is in the write clock identification signal cycle. The rising edge position of the write clock identification signal is decided according to the sampled consequence; the buffer cells are began to undertaken read operation from at least the second read clock cycle after the write clock cycle corresponded to the rising edge of write clock identification signal. This method can ensure that the delay error does not exceed clock jittering range. The designing complexity of logical circuit is decreased.
Description
Technical field
The present invention relates to buffer memory, relate in particular to a kind of method of access cache.
Background technology
In a lot of fields such as 3G mobile communication base station, the delay accuracy of signal in hardware requires often very strict.For example at WCDMA (Wide-band Code Division Multiple Access, Wideband Code Division Multiple Access (WCDMA)) in the 3GPP protocol specification of system, the relative delay error is no more than 1/4chip (being roughly equal to 65ns) between the signal on two antennas of requirement transmit diversity, and for example at CPRI (Common Public RadioInterface, common public radio interface) in the agreement, require REC (Radio Equipment Control, the radio-frequency apparatus controller) equipment is better than 1/32chip (being roughly equal to 8ns) to the hardware interface delay accuracy of RE (Radio Equipment, radio-frequency apparatus) equipment.This not only has higher requirements to the delay consistency of analogue device, and the method for designing of Digital Logical Circuits has been proposed challenge.
When high-speed digital signal transmits between two veneers, because different veneers use different clocks, phase relation between two clocks is uncertain, the data that the veneer of reception data can not directly use the local clock sampling to receive, common way is to utilize FIFO (First Input First Output earlier, first in first out) buffer carries out buffer memory to the data that receive, and then by the veneer that receives data the data in the buffer is sampled and to read.
Figure 1 shows that the schematic diagram that utilizes the FIFO buffer to realize Data Receiving buffer memory between veneer, clock (hereinafter to be referred as writing clock or Clk_wr) with transmit leg is written to a buffer area successively with data, each write address (Addr_wr) adds 1, with recipient's clock (hereinafter to be referred as reading clock or Clk_rd) reading of data successively, read address (Addr_rd) at every turn and add 1.For guaranteeing not produce error code, read the address and should follow in the write address back and keep suitable distance.Figure 2 shows that the spatial cache schematic diagram of FIFO buffer, the spatial cache of FIFO buffer can be regarded a circumference as, write and read all carries out in this circumference cocycle, therefore reading the address all is unallowed above write address (being called " reading sky ") or write address above reading the situation (being called " writing full ") of address more than a week, and other situations in addition all are legal.That is to say that the design of general FIFO buffer only guarantees to avoid " reading sky " and " writing full " two kinds of situations.If the clock frequency difference of read and write, then the speed of read and write is also different, read the inevitable constantly variation of distance between address and the write address, need to adopt suitable detection method that " reading sky " and " writing full " carried out early warning, and the address is read in control or write address is done suitable pause to avoid error code, at this moment postpone inevitable constantly variation, the maximum that postpones equals the buffer size of buffer, therefore common FIFO buffer has bigger delay uncertainty, and this common FIFO buffer is not suitable for the very strict situation of delay accuracy requirement of signal in hardware.
When reading clock and writing clock all is locked under the situation on the same clock source, its clock frequency is identical, the problem that does not have relative frequency difference, but have among a small circle relative shake (jitter) between the read-write clock, below to the description of prior art and to analysis of the present invention all based on above-mentioned condition.
In the prior art, the probabilistic method of data transfer delay is that the transmitting-receiving veneer adopts unified timing pulse signal (Sync) to do Synchronous Processing between a kind of common minimizing veneer, Figure 3 shows that its schematic diagram.A timing pulse signal (Sync) is imported transmitting single plate respectively and received veneer, the data flow that transmitting single plate sent has periodic frame structure, timing pulse signal (Sync) is that the frame length with the Frame that sends is the pulse signal in cycle, when the Sync pulse arrives, just fixing first data of frame head that send; Receiving the veneer end, increased a synchronous circuit in FIFO buffer back, this synchronous circuit is equivalent to a synchronization caching device, delay uncertain data buffer memory with the output of FIFO buffer gets off earlier, fixed position from every frame (supposing that this position is n from the frame head distance) reads again when the Sync pulse arrives, and so ideally the delay of entire circuit is n.Because timing pulse signal (Sync) also needs respectively by the clock sampling of two veneers, itself also has the regular hour error timing signal after the sampling, extreme case down when clock along near upset moment just in time the time at timing pulse signal (Sync), minimum shake also can cause the timing pulse signal sampled result that the variation of 1 clock cycle is arranged, and therefore the maximum possible delay error of this method is 1 clock cycle; The data flow that require to send of this method has periodic frame structure in addition, and hardware will provide transmissions, receive the shared timing signal of both sides, and these two conditions are difficult to satisfied simultaneously sometimes.
It is of the prior art that another kind of to reduce the probabilistic method of data transfer delay between veneer be that delay by accurate Calculation and each link of control hardware reaches the constant purpose of delay with phase place.Do not have frequency difference and shake very little prerequisite relatively based on send-receive clock, do not use the FIFO buffer memory at receiving terminal, and directly use recipient's clock sampling data.All necessary accurate Calculation delay of each link on the hardware corridor and settling time, retention time, guarantee that the receive clock sampled point is along avoiding the data upset constantly, always in the stable region of data, sample, so just can guarantee that data do not have error code and delay error is less, it postpones to change the jitter range that equals between two clocks.This method mainly has following shortcoming:
A, design difficulty height: in design process, the retardation of the necessary whole signalling channel of accurate Calculation and all links of clock passage and settling time, retention time, thereby obtain correctly to receive the time window of data, also need clock phase to be adjusted in this time window by phase modulator or phase-locked loop;
B, the interdependency of design is strong, the logical versions bad adaptability: each link of whole signalling channel and clock passage postpones all must consider every possible angle, design dependence between the disparate modules is too strong, especially in the sophisticated electronic Products Development, single plate hardware circuit and the Programmable Logic Device that comprises FIFO are usually by different team develops and maintenance, when hardware device has indivedual change, need Programmable Logic Device to readjust settling time and retention time probably, be unfavorable for the stable of version, when FIFO adopts ASIC (ApplicationSpecific Integrated Circuit, when application-specific IC) realizing, more be difficult to adjust flexibly sequential;
C, poor: ideally to the tolerance of clock jitter, clock phase is adjusted between twice upset in front and back constantly of data, 0.5 clock cycle is respectively arranged before and after the maximum safe distance,, error code will take place inevitably when the read-write clock jitter surpassed for ± 0.5 clock cycle during scope.
Summary of the invention
The method that the purpose of this invention is to provide a kind of access cache, when between send-receive clock does not have two veneers of relative frequency difference, carrying out transfer of data to solve, because of clock jitter causes the uncertain problem of first in first out buffer delay error, use this method can guarantee that the delay error of first in first out buffer is no more than the jitter range of clock, reduced the design complexities of first in first out buffer logical circuit simultaneously.
For addressing the above problem, the invention provides following technical scheme:
A kind of method of access cache comprises step:
A, n buffer unit is set on the first in first out buffer;
B, the cycle of setting be n doubly write the clock cycle write clock marking signal and cycle be n doubly read the clock cycle read the clock marking signal;
C, successively all buffer units are carried out write operation writing in the clock marking signal cycle, when writing first buffer unit, writing the clock marking signal is high level, and all the other are low level;
D, read in the clock marking signal cycle each and read the rising edge of clock cycle and sample, judge the position of writing clock marking signal rising edge according to sampled result writing the clock marking signal;
E, after writing that clock marking signal rising edge is pairing to read the clock cycle at least the 2 read the clock cycle and begin buffer unit is carried out read operation.
Described buffer unit is counted n=[x]+2, wherein [x] expression rounds up to the relative jitter range of read-write clock, the relative jitter range of read-write clock is a unit with the clock cycle multiple, and when the relative jitter range of read-write clock during less than a clock cycle, the value of n is 3; When the relative jitter range of read-write clock during greater than a clock cycle, the value of n is greater than 3.
When in described step e buffer unit being carried out read operation, what at first read is first buffer unit described in the step C.
In described step D if continuously n-1 read the sampled result difference in clock marking signal cycle, the pairing beginning of first sampled result that the clock cycle is fixed in n-1 the sampled result of reading that then begins buffer unit is carried out read operation in step e read on the clock cycle.
Because the present invention has adopted above technical scheme, so have following beneficial effect:
The first in first out buffer constant limit of optimal delay that can reach is the relative jitter range of the read-write clock that provides of external hardware in theory.But the general first in first out buffer logical circuit of using always is owing to the discreteness of clock sampling, and minimum clock jitter all may cause read/write address apart from clock cycle of increase and decrease, and promptly delay error is much larger than clock jitter.And the present invention reads the position by a best is determined in the judgement of read clock signal and write clock signal relative phase relation, thereby dwindled the delay excursion of first in first out buffer to greatest extent, the delay error that has guaranteed the first in first out buffer is equal to the clock jitter scope, has at utmost guaranteed the constancy of the delay of first in first out buffer.
Description of drawings
Fig. 1 utilizes the FIFO buffer to realize the schematic diagram of Data Receiving buffer memory between veneer;
Fig. 2 is the spatial cache schematic diagram of FIFO buffer;
Fig. 3 postpones probabilistic principle schematic for adopting unified timing signal to do between synchronous minimizing veneer;
Fig. 4 is a flow chart of the present invention;
Fig. 5 is provided with schematic diagram for the buffer unit of the embodiment of the invention one;
Fig. 6 is the FIFO buffer logical circuit working timing figure of the embodiment of the invention one;
Fig. 7 is provided with schematic diagram for the buffer unit of the embodiment of the invention two;
Fig. 8 is the FIFO buffer logical circuit working timing figure of the embodiment of the invention two.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further detailed description.
Technical scheme of the present invention based on prerequisite be: read clock and write clock and all be locked on the same clock source, the frequency of send-receive clock is identical, but has the phase jitter of certain limit.
As shown in Figure 4, the present invention at first is provided with n buffer unit, n=[x on the FIFO buffer]+2, wherein [x] expression rounds up to the relative jitter range of read-write clock, and the relative jitter range of read-write clock is a unit with the clock cycle multiple; Be provided with respectively and write the clock marking signal and read the clock marking signal, the cycle of writing the clock marking signal is n times the clock cycle of writing, and the cycle of reading the clock marking signal is n times reading the clock cycle; Successively all buffer units are carried out write operation writing in the clock marking signal cycle, when first buffer unit is carried out write operation, writing the clock marking signal is high level, and when other buffer units except that first buffer unit were carried out write operation, writing the clock marking signal was low level; Read the rising edge of clock cycle and sample reading in the clock marking signal cycle each writing the clock marking signal, judge the position of writing clock marking signal rising edge according to sampled result, after writing that clock marking signal rising edge is pairing to read the clock cycle at least the second reads the clock cycle and begins above-mentioned first buffer unit is carried out read operation.
As shown in Figure 5, set up 3 buffer units at the FIFO buffer, 3 buffer units are represented with unit0, unit1 and unit2 respectively.
As shown in Figure 6, define one and write clock marking signal Flag_wr, the rising edge of writing clock Clk_wr circulates successively and writes 3 buffer units, when writing clock Clk_wr and writing unit0 at every turn, the Flag_wr set is when writing unit1, Flag_wr clear " 0 ", when writing unit2, Flag_wr remains " 0 ", the pulse signal that to write clock marking signal Flag_wr like this and be the cycle with 3 times of clock cycle.
Define one and read clock marking signal Flag_rd, the pulse signal that to read clock marking signal Flag_rd and be equally be the cycle with 3 times of clock cycle.The rising edge clock of reading of definition Flag_rd high level correspondence is edge0, and adjacent rising edge more early is edge1, and Zao rising edge is edge2 again.
Constantly sample to writing clock marking signal Flag_wr respectively at edge2, edge1, edge0, the Flag_wr signal level that samples for three times according to edge2, edge1, edge0, judge the position of Flag_wr rising edge, thereby which unit decision reads at edge0.In case determined the unit that edge0 reads, then two edge subsequently read the unit of back successively, rejudge up to next edge0 again.The difference of read-write clock phase relation can cause the Clk_rd rising edge different with the position relation of Flag_wr signal rising edge, total following 3 kinds of situations:
Case1: to Flag_wr between the edge1 rising edge is arranged at edge2;
Case2: to Flag_wr between the edge2 rising edge is arranged at edge0;
Case3: Flag_wr has a rising edge between edge1 and edge0.
In Fig. 6 to every kind of Case two kinds of border condition (referring to the situation very approaching) of having drawn again with adjacent Case, use suffix (1), (2) expression respectively, for example Case1 (2) is very approaching with Case2 (1), and Case1 (1) and Case3 (2) very near or the like, clock has shake just might become another kind of Case slightly.
A duration parameter T is set, and the FIFO buffer is read rising edge clock at each and is determined to read which unit (buffer unit) according to the following rules:
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is that the duration during all less than T that ties up between Case1 and the Case2 frequently saltus step and Case1 and Case2 is closed in the position that is not less than duration of Case1 and Case1 T or Clk_rd rising edge and Flag_wr signal rising edge, then reads buffer unit unit0 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is that the duration during all less than T that ties up between Case2 and the Case3 frequently saltus step and Case2 and Case3 is closed in the position that is not less than duration of Case2 and Case2 T or Clk_rd rising edge and Flag_wr signal rising edge, then reads buffer unit unit1 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is that the duration during all less than T that ties up between Case3 and the Case1 frequently saltus step and Case3 and Case1 is closed in the position that is not less than duration of Case3 and Case3 T or Clk_rd rising edge and Flag_wr signal rising edge, then reads buffer unit unit2 at edge0;
When discontented when being enough to situation, the maintenance standing state.
Generally read and write between the clock phase relation judged result and be and determine constantly, can stablize and select a safest unit to read.But since when clock phase place during at boundary position (as the Case1 among Fig. 6 (1), Case1 (2) ... etc.), minimum shake also can cause the clock sampling result frequently to be switched between two adjacent C ase, read in this case that any one all is safe among two adjacent unit, but should be stable read a unit and can not frequently switch otherwise can produce error code.Therefore increased in the Rule of judgment " position of Clk_rd rising edge and Flag_wr signal rising edge is closed and is tied up to ... with ... between frequent saltus step " restriction, exactly for fear of reading position frequently switching between 3 unit in this case.
Dash area is represented the distribution in the moment that this unit (buffer unit) may be read among Fig. 6, and is always constantly all far from former and later two upsets when as seen each unit is read, thereby avoided foundation, retention time to produce the situation of error code inadequately.
The FIFO buffer has been set up 3 buffer units in the above-described embodiments, is applicable to the situation of clock jitter scope less than a clock cycle.According to requirement to the clock jitter tolerance, if the clock jitter scope is greater than a clock cycle, buffer unit number that then can the FIFO buffer is set to more than 3, and the number of set buffer unit is big more, tolerance to clock jitter is good more, but delay error is also big more.Be that example describes to set up 4 buffer units at the FIFO buffer below.
As shown in Figure 7, set up 4 buffer units in the FIFO buffer, 4 buffer units are represented with unit0, unit1, unit2 and unit3 respectively.
As shown in Figure 8, define one and write clock marking signal Flag_wr, the rising edge of writing clock Clk_wr circulates successively and writes 4 buffer units, when writing clock Clk_wr and writing unit0 at every turn, the Flag_wr set, when writing unit1, Flag_wr clear " 0 " is when writing unit2, Flag_wr remains " 0 ", when writing unit3, Flag_wr remains " 0 ", the pulse signal that to write clock marking signal Flag_wr like this and be the cycle with 4 times of clock cycle.
Define one and read clock marking signal Flag_rd, the pulse signal that to read clock marking signal Flag_rd and be equally be the cycle with 4 times of clock cycle.The rising edge clock of reading of definition Flag_rd high level correspondence is edge0, and adjacent rising edge more early is edge1, and Zao rising edge is edge2 again, and more Zao rising edge is edge3.
Constantly sample to writing clock marking signal Flag_wr respectively at edge3, edge2, edge1, edge0,, judge the position of Flag_wr rising edge, thereby which unit decision reads at edge0 according to the Flag_wr signal level that samples for four times.In case determined the unit that edge0 reads, then three edge subsequently read the unit of back successively, rejudge up to next edge0 again.The difference of read-write clock phase relation can cause the Clk_rd rising edge different with the position relation of Flag_wr signal rising edge, total following 4 kinds of situations:
Case1: to Flag_wr between the edge1 rising edge is arranged at edge2;
Case2: Flag_wr has a rising edge between edge3 and edge2;
Case3: Flag_wr has a rising edge between edge0 and edge3;
Case4: to Flag_wr between the edge0 rising edge is arranged at edge1;
With identical among the embodiment one, every kind of Case has two kinds of border condition (referring to the situation very approaching with adjacent Case) again, and clock has shake just might become another kind of Case slightly.
A duration parameter T is set, and the FIFO buffer is read rising edge clock at each and is determined to read which unit (buffer unit) according to the following rules:
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case1 and Case1 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge close tie up to frequent saltus step between Case1, Case2, the Case3 and Case1, Case2, Case3 duration all less than T, then read buffer unit unit0 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case2 and Case2 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge close tie up to frequent saltus step between Case2, Case3, the Case4 and Case2, Case3, Case4 duration all less than T, then read buffer unit unit1 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case3 and Case3 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge close tie up to frequent saltus step between Case3, Case4, the Case1 and Case3, Case4, Case1 duration all less than T, then read buffer unit unit2 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case4 and Case4 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge is closed and to be tied up between Case4, Case1, the Case2 frequent saltus step and Case4, Case1, Case2, duration all less than T, then read buffer unit unit3 at edge0;
When being enough to last four kinds of situations, keep standing state when discontented,
Diagonal line hatches among Fig. 8 has partly been represented the distribution in the moment that each buffer unit may be read under above-mentioned rule, always constantly all far when as seen each unit is read from former and later two upsets, thus avoided foundation, retention time to produce the situation of error code inadequately.
Above-mentioned rule also can be as follows:
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case2 and Case2 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge close tie up to frequent saltus step between Case1, Case2, the Case3 and Case1, Case2, Case3 duration all less than T, then read buffer unit unit0 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case3 and Case3 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge close tie up to frequent saltus step between Case2, Case3, the Case4 and Case2, Case3, Case4 duration all less than T, then read buffer unit unit1 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case4 and Case4 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge close tie up to frequent saltus step between Case3, Case4, the Case1 and Case3, Case4, Case1 duration all less than T, then read buffer unit unit2 at edge0;
Closing when the position of Clk_rd rising edge and Flag_wr signal rising edge is duration of Case1 and Case1 to be not less than T, perhaps the position of Clk_rd rising edge and Flag_wr signal rising edge is closed and to be tied up between Case4, Case1, the Case2 frequent saltus step and Case4, Case1, Case2, duration all less than T, then read buffer unit unit3 at edge0;
When being enough to last four kinds of situations, keep standing state when discontented,
Dot-hatched among Fig. 8 has partly been represented the distribution in the moment that each buffer unit may be read under this rule, always constantly all far when as seen each unit is read from former and later two upsets, thus avoided foundation, retention time to produce the situation of error code inadequately.
Below only the present invention will be described with preferred embodiment, and those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (7)
1, a kind of method of access cache is characterized in that comprising step:
A, n buffer unit is set on the first in first out buffer;
B, respectively be provided with the cycle be n times of clock cycle write clock marking signal and cycle be n doubly read the clock cycle read the clock marking signal;
C, writing in the clock marking signal cycle successively to the buffer unit write operation, when writing first buffer unit, writing the clock marking signal is high level, and all the other are low level;
D, read the rising edge of clock cycle and sample reading in the clock marking signal cycle each, judge the position of writing clock marking signal rising edge according to sampled result writing the clock marking signal;
E, after writing that clock marking signal rising edge is pairing to read the clock cycle at least the 2 read the clock cycle and begin buffer unit is carried out read operation.
2, the method for access cache according to claim 1 is characterized in that: described buffer unit is counted n=[x]+2, wherein [x] expression rounds up to the relative jitter range of read-write clock.
3, the method for access cache according to claim 2 is characterized in that: the relative jitter range of described read-write clock is a unit with the clock cycle multiple.
4, the method for access cache according to claim 3 is characterized in that: when the relative jitter range of read-write clock during less than a clock cycle, the value of n is 3.
5, the method for access cache according to claim 3 is characterized in that: when the relative jitter range of read-write clock during greater than a clock cycle, the value of n is greater than 3.
6, the method for access cache according to claim 1 is characterized in that: when in described step e buffer unit being carried out read operation, what at first read is first buffer unit among the step C.
7, the method for access cache according to claim 1, it is characterized in that: in described step D if continuously n-1 read the sampled result difference in clock marking signal cycle, the pairing beginning of first sampled result that the clock cycle is fixed in n-1 the sampled result of reading that then begins buffer unit is carried out read operation in step e read on the clock cycle.
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| CNB2005100026178A CN100558032C (en) | 2005-01-24 | 2005-01-24 | The method of access cache |
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| CNB2005100026178A CN100558032C (en) | 2005-01-24 | 2005-01-24 | The method of access cache |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110737615A (en) * | 2018-07-19 | 2020-01-31 | 海鹰航空通用装备有限责任公司 | data access method and device |
| CN111555791A (en) * | 2020-03-31 | 2020-08-18 | 北京控制工程研究所 | High-reliability high-frequency satellite wireless data acquisition system and method |
| CN112328523A (en) * | 2020-10-28 | 2021-02-05 | 深圳市宏旺微电子有限公司 | Method, device and system for transmitting double-rate signal |
| WO2022226820A1 (en) * | 2021-04-28 | 2022-11-03 | Yangtze Memory Technologies Co., Ltd. | Clock signal return scheme for data read in page buffer of memory device |
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2005
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110737615A (en) * | 2018-07-19 | 2020-01-31 | 海鹰航空通用装备有限责任公司 | data access method and device |
| CN110737615B (en) * | 2018-07-19 | 2021-06-08 | 海鹰航空通用装备有限责任公司 | Data access method and device |
| CN111555791A (en) * | 2020-03-31 | 2020-08-18 | 北京控制工程研究所 | High-reliability high-frequency satellite wireless data acquisition system and method |
| CN111555791B (en) * | 2020-03-31 | 2022-04-08 | 北京控制工程研究所 | High-reliability high-frequency satellite wireless data acquisition system and method |
| CN112328523A (en) * | 2020-10-28 | 2021-02-05 | 深圳市宏旺微电子有限公司 | Method, device and system for transmitting double-rate signal |
| CN112328523B (en) * | 2020-10-28 | 2023-09-08 | 深圳市宏旺微电子有限公司 | Method, device and system for transmitting double-rate signal |
| WO2022226820A1 (en) * | 2021-04-28 | 2022-11-03 | Yangtze Memory Technologies Co., Ltd. | Clock signal return scheme for data read in page buffer of memory device |
| US11694752B2 (en) | 2021-04-28 | 2023-07-04 | Yangtze Memory Technologies Co., Ltd. | Clock signal return scheme for data read in page buffer of memory device |
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| CN100558032C (en) | 2009-11-04 |
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