CN1812095A - Low voltage logic operation using higher voltage supply levels - Google Patents
Low voltage logic operation using higher voltage supply levels Download PDFInfo
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- CN1812095A CN1812095A CN 200510114988 CN200510114988A CN1812095A CN 1812095 A CN1812095 A CN 1812095A CN 200510114988 CN200510114988 CN 200510114988 CN 200510114988 A CN200510114988 A CN 200510114988A CN 1812095 A CN1812095 A CN 1812095A
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Abstract
A processing system comprises a first processing module and a second processing module that communicates with the first processing module. The first and second processing modules are connected in series between first and second reference potentials. An operating system communicates with the first and second processing modules and performs at least one of load balancing and/or throttling of the first and second processing modules to reduce a difference in current consumption between the first and second processing modules.
Description
Technical field
The present invention relates to use the operation of the grand and/or module of the low pressure compound logic of higher voltage power supply electrical level and lower current levels.
Background technology
The decennary in the past progress of complementary metal oxide semiconductors (CMOS) (CMOS) technology has produced littler device by the transistor of integrated greater number.For example, powerful more than 1000 times than the microprocessor of making before 10 years of current microprocessor.
The power consumption of microprocessor is also increasing.Now, the power consumption of some microprocessors surpasses 100W.The voltage supply level that the modern processors that uses low voltage CMOS technology to make up adopts seldom surpasses 1V.The levels of current that need surpass as a result, 100A based on the microprocessor of CMOS.
Physical obstacle begins to limit the magnitude of current of these devices of flowing through.A kind of obstacle relates to and the relevant voltage drop of the distribution of electric power in these microprocessors.The voltage drop that the dead resistance of 1m Ω (milliohm) in Chip Packaging and/or printed circuit board (PCB) (PCB) bus plane can produce 100mV.In fact, it is very difficult under the condition that does not significantly increase material and relevant treatment cost dead resistance being reduced to less than 1M Ω (megaohm).
For example, the resistance of the golden closing line in the general semiconductor packages has the resistance of about 100M Ω 1 micron of diameter under the condition of length 5mm.For with the general supply resistance limits below 1M Ω, each power supply connects (V
DDAnd V
SS) must be restricted to Ω less than 0.5M.This method need surpass 400 closing lines.Because other sources of dead resistance will need more closing line.
A kind of method has been eliminated closing line and has been used flip-chip (flip chip) encapsulation technology.This method has solved the subproblem in the packaged resistance problem.The item of other considerations comprises the metallic resistance in the semiconductor self, the metallic resistance of Flip-Chip Using and the also necessary phase coadaptation of metallic resistance of printed circuit board (PCB) (PCB).Along with chip continues to dwindle, the trace of wiring must be done narrowlyer.As a result, must use thinner metal material, and this has increased dead resistance.
The application is the U.S. Patent application No.11/098 that submitted on April 4th, 2005,129 continuation application, above-mentioned U.S. Patent application No.11/098,129 require the U.S. Provisional Application No.60/631 that submitted on November 29th, 2004, the U.S. Provisional Application No.60/663 that on March 21st, 552 and 2005 submitted, 933 priority.The disclosure of above-mentioned application here is included in as a reference.
Summary of the invention
A kind of circuit comprise first module and with second module of first module communication.First and second modules are connected in series between first and second reference potentials.The current balance module is communicated with node between first and second modules, and the current drain that reduces between first and second modules is poor.
In other respects, the current balance module comprises buck converter (buck converter).Buck converter comprises the conductive switch that is communicated with the 3rd reference potential.Freely turning round switch (freewheelingswitch) is communicated with the 4th reference potential and conductive switch.Inductance element and described conductive switch and freely turn round switch and described node is communicated with.Capacity cell is communicated with the 4th reference potential and described node.
In other respects, the current balance module comprises 2: 1 DC/DC converters.The DC/DC converter comprised first and second conductive switchs in 2: 1.First and second inductance elements are communicated with first and second conductive switchs.First and second freely turn round switch is communicated with first and second conductive switchs, so that a current path to be provided in the non-conduction period.The DC/DC converter also comprised drive signal generator in 2: 1, the drive signal that is used to produce control first and second conductive switchs and freely turns round switch.First and second inductance elements are wrapped on the public core.First and second conductive switchs, first and second inductance elements and first and second freely turn round switch and connect with the buck configuration, make output voltage be approximately half of input voltage amplitude.
In other respects, the current balance module comprises equalizer switch capacitor element.Equalizer switch capacitor element comprises first capacity cell with first end and second end, and wherein first end of first capacity cell is communicated with first module and first reference potential, and second end of first capacity cell is communicated with described node.Second capacity cell has first end that is communicated with second module and second reference potential and second end that is communicated with described node.The 3rd capacity cell has first and second ends.A plurality of switches are selectively connected thereto first and second modules with first, second and the 3rd electric capacity and optionally disconnect and is connected the current drain of balanced first and second modules.Described a plurality of switch comprises first switch, second switch, the 3rd switch and the 4th switch, wherein first switch has first end that is communicated with first end of first capacity cell and second end that is communicated with first end of the 3rd capacity cell, second switch has first end that is communicated with first end of second capacity cell and second end that is communicated with second end of the 3rd capacity cell, the 3rd switch has first end that is communicated with first end of the 3rd capacity cell and second end that is communicated with described node, and the 4th switch has first end that is communicated with second end of the 3rd capacity cell and second end that is communicated with described node.Drive signal generator produces the drive signal that is used for controlling described a plurality of switches.
In other respects, the current balance module comprises that linearity recommends (push-pull) adjuster.Linearity is recommended adjuster and is comprised that first and second linearities recommend adjuster.The first rank linearity is recommended second terminal that adjuster comprises first operational amplifier (opamp), has the first transistor of the control input end that is communicated with the output of first operational amplifier, the first terminal that is communicated with the 3rd reference potential and be communicated with described node.The second rank linearity is recommended second terminal that adjuster comprises second operational amplifier (opamp), has the transistor seconds of the control input end that is communicated with the output of second operational amplifier, the first terminal that is communicated with described node and be communicated with the 4th reference potential.Linearity is recommended adjuster and is also comprised the resistive element with first end and second end, and first end of resistive element is communicated with the first input end of first and second operational amplifiers, and second end of resistive element is communicated with described node.
In other respects, the current balance module comprises hysteresis comparator (hysteresis comparator) module.The hysteresis comparator module comprises at least one in adjustable bias module, BREATHABLE BANDWIDTH module and/or the adjustable delay module.Circuit is an integrated circuit.
In other respects, DC/DC converter receiving inputted signal and produce output signal.The 22: the 1DC/DC converter has the input that is communicated with the output of DC/DC converter and with 2: the output that the input of 1DC/DC converter is communicated with.
In other respects, provide third and fourth module.First, second, third and four module between first and second reference potentials, be connected in series.The current balance module comprises the one 2: 1 DC/DC converter, the first node between the one 2: 1 DC/DC converter and first reference potential, first and second modules and second and three module between Section Point be communicated with.The 22: 1 DC/DC converter is communicated with the 3rd node and second reference potential between Section Point, third and fourth module.The 32: 1 DC/DC converter is communicated with first reference potential, Section Point and second reference potential.
In other respects, a kind of equipment comprises circuit, and comprises that further N is to circuit.First module comprises that N is to first circuit in a couple in the circuit.Second module comprises that N is to the second circuit in a couple in the circuit.N comprises treatment circuit to circuit.Three module comprises that N is to another the first internal circuit in the circuit.Four module comprises that N is to another the internal second circuit in the circuit.Third and fourth module is connected in series between first and second reference potentials, and the current balance module is communicated with node between third and fourth module.First, second, third and four module comprise signal processing module.First, second, third and four module comprise the graphics pipeline module.
In other respects, a kind of treatment system comprises equipment.First module comprises that first CPU (CPU) and second module comprise the 2nd CPU.Operating system is communicated by letter with first and second CPU, and carries out the load balancing of first and second CPU and/or at least one in the throttling, and is poor with the current drain that reduces between first and second CPU.
In other respects, first and second CPU are realized by single integrated circuit.The current balance module comprises 2: 1 DC/DC converters with first and second inductors.Assembly in 2: 1 DC/DC converters except that first and second inductors is realized by integrated circuit.
In other respects, a kind of system comprises treatment system, and further comprise printed circuit board (PCB) (PCB), the pin that is arranged in first and second slots on the PCB and stretches out and held by first and second slots from integrated circuit.First and second inductors are attached to integrated circuit, and are disposed between integrated circuit and the PCB.
The second channel module that a kind of network equipment comprises first channel module, be connected in series with first channel module, the 3rd channel module that is connected in series with the second channel module and the 4th channel module that is connected in series with the 3rd channel module.The first and the 4th channel module is connected in series between first and second reference potentials.Be equal on the first, second, third and the 4th channel module function.
In other respects, between a kind of current balance module and first and second channel modules, between the second and the 3rd channel module and the node between third and fourth channel module be communicated with, and the current drain that reduces between the first, second, third and the 4th channel module is poor.This network equipment and 1000Base-T operating such.This network equipment and 10GBase-T operating such.
In other respects, the current balance module comprises buck converter.The current balance module comprises 2: the 1DC/DC converter.The current balance module comprises equalizer switch capacitor element.The current balance module comprises that linearity recommends adjuster.The current balance module comprises the hysteresis comparator module.
A kind of treatment system comprises first processing module and second processing module of communicating by letter with first processing module.First and second processing modules are connected in series between first and second reference potentials.Operating system is communicated by letter with first and second processing modules, and carries out the load balancing of first and second processing modules and/or at least one in the throttling, and is poor with the current drain that reduces between first and second processing modules.
In other respects, the current balance module is communicated with node between first and second processing modules, and the current drain that reduces between first and second processing modules is poor.
In other respects, the current balance module comprises buck converter.The current balance module comprises 2: the 1DC/DC converter.The current balance module comprises equalizer switch capacitor element.The current balance module comprises that linearity recommends adjuster.The current balance module comprises the hysteresis comparator module.First and second processing modules comprise the first and second graphics pipeline modules.
First and second processing modules are all realized by single integrated circuit.The current balance module comprises 2: 1 DC/DC converters with first and second inductors.Assembly in 2: 1 DC/DC converters except that first and second inductors is realized by integrated circuit.
A kind of system comprises treatment system, and further comprise printed circuit board (PCB) (PCB), the pin that is arranged in first and second slots on the PCB and stretches out and held by first and second slots from integrated circuit.First and second inductors are attached to integrated circuit, and are disposed between integrated circuit and the PCB.
A kind of circuit be included in be connected in series between first and second reference potentials 2
nIndividual module.2
n-1 node is set at 2
nBetween the adjacent block of individual module.2
n-12: 1 DC/DC converter and 2
nCorresponding node in-1 node is communicated with.
In other respects, 2
n-12: 1 DC/DC converter arrangement is in n bar branch road.First branch road comprises 2
nIn-1 2: 1 DC/DC converter one, second branch road comprises 2
n-12: in the 1DC/DC converter two, and the n branch road comprises 2
nIn-1 2: 1 DC/DC converter 2
N-1Individual.Module comprises that compound logic is grand.Module comprises application-specific integrated circuit (ASIC) (ASIC).Module comprises processing module.
A kind of method comprises: use first module to carry out first function; Use with second module of first module communication and carry out second function, first and second modules are connected in series between first and second reference potentials; And the current drain that reduces between first and second modules is poor.
In other respects, described method comprises and uses buck converter to carry out the described step that reduces.Described method comprises uses 2: 1 DC/DC converters to carry out the described step that reduces.Described method comprises uses equalizer switch capacitor element to carry out the described step that reduces.Described method comprises that using linearity to recommend adjustment module carries out the described step that reduces.Described method comprises uses the hysteresis comparator module to carry out the described step that reduces.
A kind of method of operational network equipment comprises first communication channel is provided; The second communication of connecting with first communication channel channel is provided; The third communication of connecting with second communication channel channel is provided; And provide the four-way of connecting to believe channel with third communication channel.First and four-way letter channel be connected in series between first and second reference potentials, and wherein first, second, third and four-way letter channel function on be equal to.
In other respects, described method comprise reduce first, second, third and the current drain of four-way letter interchannel poor.The described network equipment and 1000Base-T operating such.This network equipment and 10GBase-T operating such.
In other respects, described method comprises and uses buck converter to carry out the described step that reduces.Described method comprises uses 2: 1 DC/DC converters to carry out the described step that reduces.Described method comprises uses equalizer switch capacitor element to carry out the described step that reduces.Described method comprises that using linearity to recommend adjustment module carries out the described step that reduces.Described method comprises uses the hysteresis comparator module to carry out the described step that reduces.
A kind of method comprises first processing module is provided; Second processing module of communicating by letter with first processing module is provided, and wherein first and second processing modules are connected in series between first and second reference potentials; And carry out the load balancing of first and second processing modules and/or at least one in the throttling, poor with the current drain that reduces between first and second processing modules.
In other respects, described method comprises that the current drain that reduces between first and second processing modules is poor.
In other respects, described method comprises and uses buck converter to carry out the described step that reduces.Described method comprises uses 2: 1 DC/DC converters to carry out the described step that reduces.Described method comprises uses equalizer switch capacitor element to carry out the described step that reduces.Described method comprises that using linearity to recommend adjustment module carries out the described step that reduces.Described method comprises uses the hysteresis comparator module to carry out the described step that reduces.
First and second processing modules are all realized by single integrated circuit.The DC/DC converter comprised first and second inductors in 2: 1.Assembly in 2: 1 DC/DC converters except that first and second inductors is realized by integrated circuit.
First and second slots are disposed on the PCB, and pin stretches out from integrated circuit and held by first and second slots.First and second inductors be attached to integrated circuit and be disposed in integrated circuit and PCB between.
A kind of method, comprise be provided at be connected in series between first and second reference potentials 2
nIndividual module; Provide and be set at 2
nBetween the adjacent block of individual module 2
n-1 node; And be provided for carrying out 2 of conversion
n-12: 1 DC/DC converter, wherein 2
nIn-1 2: 1 DC/DC converter each and 2
nCorresponding node in-1 node is communicated with.
In other respects, 2
n-12: 1 DC/DC converter is disposed in the n bar branch road.First branch road comprises 2
nIn-1 2: 1 DC/DC converter one, second branch road comprises 2
n-12: in the 1DC/DC converter two, and the n branch road comprises 2
nIn-1 2: 1 DC/DC converter 2
N-1Individual.2
nIndividual module comprises that compound logic is grand.2
nIndividual module comprises application-specific integrated circuit (ASIC) (ASIC).2
nIndividual module comprises processing module.
A kind of circuit comprises first device that is used to carry out first function; And second device that is used to carry out second function and communicates by letter with first device.First and second devices are connected in series between first and second reference potentials.The current balance device is communicated with node between first and second devices, and it is poor to reduce first and second the current drains between installing.
In other respects, the current balance device comprises buck converter.Buck converter comprises the switch that is communicated with the 3rd reference potential conductive switch device.Switch is communicated with the 4th reference potential and conductive switch device with freely turning round switching device.The inductance device that is used to provide inductance and described conductive switch device and freely turn round switching device and described node is communicated with.Be used to provide the capacitive means of electric capacity to be communicated with the 4th reference potential and described node.
In other respects, the current balance device comprises that conversion was with 2: 1 DC/DC converting means.2: the 1DC/DC converting means comprises the first and second conductive switch devices that switch is used.Be used to provide first and second inductance devices of inductance to be communicated with the first and second conductive switch devices.What switch was used first and second freely turns round switching device and is communicated with the first and second conductive switch devices, so that a current path to be provided in the non-conductive period.The DC/DC converting means also comprised driving signal generator in 2: 1, the drive signal that is used to produce the control first and second conductive switch devices and freely turns round switching device.First and second inductance devices are wrapped on the public core.The first and second conductive switch devices, first and second inductance devices and first and second freely turn round switching device and connect with the buck configuration, make output voltage be approximately half of input voltage amplitude.
In other respects, the current balance device comprises the equalizer switch capacitive means that is used for switching capacity.The equalizer switch capacitive means comprises first capacitive means that is used to provide electric capacity with first end and second end, and wherein first end of first capacitive means is communicated with first device and first reference potential, and second end of first capacitive means is communicated with described node.Be used to provide second capacitive means of electric capacity to have first end that is communicated with second device and second reference potential and second end that is communicated with described node.Be used to provide the 3rd capacitive means of electric capacity to have first and second ends.A plurality of switching devices that switch is used are selectively connected thereto first and second devices with first, second and the 3rd capacitive means and optionally disconnect and being connected, come balanced first and second current drains that install.Described a plurality of switching device comprises first switching device that switch is used, the second switch device, the 3rd switching device and the 4th switching device, wherein first switching device has first end that is communicated with first end of first capacitive means and second end that is communicated with first end of the 3rd capacitive means, the second switch device has first end that is communicated with first end of second capacitive means and second end that is communicated with second end of the 3rd capacitive means, the 3rd switching device has first end that is communicated with first end of the 3rd capacitive means and second end that is communicated with described node, and the 4th switching device has first end that is communicated with second end of the 3rd capacitive means and second end that is communicated with described node.Driving signal generator produces the drive signal that is used for controlling described a plurality of switching devices.
In other respects, the current balance device comprises that the linearity of regulating usefulness recommends adjusting device.Linearity is recommended adjusting device and is comprised that first and second linearities recommend adjuster.The first rank linearity is recommended second terminal that adjuster comprises first operational amplifier (opamp), has the first transistor of the control input end that is communicated with the output of first operational amplifier, the first terminal that is communicated with the 3rd reference potential and be communicated with described node.The second rank linearity is recommended second terminal that adjuster comprises second operational amplifier (opamp), has the transistor seconds of the control input end that is communicated with the output of second operational amplifier, the first terminal that is communicated with described node and be communicated with the 4th reference potential.Linearity is recommended adjusting device and is also comprised the resistive element with first end and second end, and first end of resistive element is communicated with the first input end of first and second operational amplifiers, and second end of resistive element is communicated with described node.
In other respects, the current balance device comprises the hysteresis comparator device that is used for euqalizing current.The hysteresis comparator device comprises the adjustable bias device that is used for adjusting biasing, be used to adjust the BREATHABLE BANDWIDTH device of bandwidth and/or be used to adjust at least one of adjustable delay device of delay.
In other respects, circuit is an integrated circuit.The DC/DC converting means receiving inputted signal that conversion is used also produces output signal.The 22: the 1 DC/DC converting means that conversion is used has input that is communicated with the output of DC/DC converting means and the output that is communicated with the input of 2: 1 DC/DC converting means.
In other respects, circuit comprises third and fourth device that is used to carry out third and fourth function.The first, second, third and the 4th device is connected in series between first and second reference potentials.The current balance device comprises the one 2: 1 DC/DC converting means, the 22: 1 DC/DC converting means and the 32: the 1 DC/DC converting means that conversion is used, and first node between the one 2: 1 DC/DC converting means and first reference potential, first and second devices and the Section Point between the second and the 3rd device are communicated with.The 3rd node and second reference potential between the 22: 1 DC/DC converting means and Section Point, third and fourth device are communicated with.The 32: 1 DC/DC converting means is communicated with first reference potential, Section Point and second reference potential.
A kind of equipment comprises circuit, and comprises that further N is to circuit.First device comprises N to first circuit in a couple in the circuit, and second device comprises that N is to the second circuit in a couple in the circuit.N comprises the processing unit of handling usefulness to circuit.The 3rd device that is used for carrying out the 3rd function comprises N another first internal circuit to circuit.The 4th device that is used for carrying out the 4th function comprises N another internal second circuit to circuit.Third and fourth device is connected in series between first and second reference potentials, and the current balance device is communicated with node between third and fourth installs.The first, second, third and the 4th device comprises the signal processing apparatus of handling usefulness.
In other respects, Graphics Processing Unit (GPU) comprises described equipment.The first, second, third and the 4th device comprises the graphics pipeline device that is used for processing graphics.
In other respects, a kind of treatment system comprises described equipment.First device comprises that first processing unit and second device of handling usefulness comprise second processing unit of handling usefulness.Operating system is communicated by letter with first and second processing unit, and carries out the load balancing of first and second processing unit and/or at least one in the throttling, and is poor with the current drain that reduces between first and second processing unit.First and second processing unit are all realized by single integrated circuit.
In other respects, the current balance device comprises that conversion with first and second inductance devices was with 2: 1 DC/DC converting means.Assembly in 2: 1 DC/DC converting means except that first and second inductance devices is realized by integrated circuit.A kind of system comprises treatment system, and further comprise printed circuit board (PCB) (PCB), the pin that is arranged in first and second slots on the PCB and stretches out and held by first and second slots from integrated circuit.First and second inductance devices are attached to integrated circuit, and are disposed between integrated circuit and the PCB.
A kind of network equipment comprise first CU channel unit that is used to provide first communication channel, with first CU channel unit be connected in series the second channel device that is used to provide the second communication channel, being connected in series to be used to provide the 3rd CU channel unit of third communication channel and to be connected in series with the 3rd CU channel unit with the second channel device is used to provide the 4th CU channel unit of four-way letter channel.The first and the 4th CU channel unit is connected in series between first and second reference potentials, and the first, second, third and the 4th CU channel unit is equal on function.
In other respects, between a kind of current balance device that is used for euqalizing current and first and second CU channel unit, between the second and the 3rd CU channel unit and the node between third and fourth CU channel unit be communicated with, and the current drain that reduces between the first, second, third and the 4th CU channel unit is poor.This network equipment and 1000Base-T operating such.This network equipment and 10GBase-T operating such.
In other respects, the current balance device comprises buck converter.The current balance device comprises 2: 1 DC/DC converting means that conversion is used.The current balance device comprises the equalizer switch capacitive means that is used for switching capacity.The current balance device comprises that the linearity of regulating usefulness recommends adjusting device.The current balance device comprises the hysteresis comparator device that is used for euqalizing current.The hysteresis comparator device comprises the adjustable bias device that is used for adjusting biasing, be used to adjust the BREATHABLE BANDWIDTH device of bandwidth and/or be used to adjust at least one of adjustable delay device of delay.
A kind of treatment system comprises first processing unit of handling usefulness and processing second processing unit of communicating by letter with first processing unit.First and second processing unit are connected in series between first and second reference potentials.Be used to provide the operating means of operating system to communicate by letter, and carry out the load balancing of first and second processing unit and/or at least one in the throttling with first and second processing unit, poor with the current drain that reduces between first and second processing unit.
In other respects, the current balance device is communicated with node between first and second processing unit, and the current drain that reduces between first and second processing unit is poor.
In other respects, the current balance device comprises buck converter.The current balance device comprises 2: 1 DC/DC converting means that conversion is used.The current balance device comprises the equalizer switch capacitive means that is used for switching capacity.The current balance device comprises that the linearity of regulating usefulness recommends adjusting device.The current balance device comprises the hysteresis comparator device that is used for euqalizing current.The hysteresis comparator device comprises the adjustable bias device that is used for adjusting biasing, be used to adjust the BREATHABLE BANDWIDTH device of bandwidth and/or be used to adjust at least one of adjustable delay device of delay.Processing unit comprises the graphics pipeline device that is used for processing graphics.
First and second processing unit are all realized by single integrated circuit.The current balance device comprises that conversion with first and second inductance devices that are used to provide inductance was with 2: 1 DC/DC converting means.Assembly in 2: 1 DC/DC converting means except that first and second inductance devices is realized by integrated circuit.
A kind of system comprises treatment system, and further comprise printed circuit board (PCB) (PCB), the pin that is arranged in first and second slots on the PCB and stretches out and held by first and second slots from integrated circuit.First and second inductors are attached to integrated circuit, and are disposed between integrated circuit and the PCB.
A kind of circuit comprises: be connected in series between first and second reference potentials and be used for carrying out respectively 2
n Plant 2 of function
nIndividual device is set at 2
nBetween the neighboring devices of individual device 2
n-1 node, and conversion use 2
n-12: 1 DC/DC converting means.2
nIn-1 2: 1 DC/DC converting means each and 2
nA corresponding node of-1 node is communicated with.
In other respects, 2
n-12: 1 DC/DC converting means is disposed in the n bar branch road.First branch road comprises 2
nIn-1 2: 1 DC/DC converting means one, second branch road comprises 2
nIn-1 2: 1 DC/DC converting means two, and the n branch road comprises 2
nIn-1 2: 1 DC/DC converting means 2
N-1Individual.2
nIndividual device comprises that compound logic is grand, application-specific integrated circuit (ASIC) (ASIC) and/or handle the processing unit of usefulness.
By detailed description hereinafter, the applicable other field of the present invention will become clear.Should be appreciated that to be used to illustrate that the detailed description of the preferred embodiment for the present invention and specific embodiment are only used for illustrational purpose, rather than want to limit the scope of the invention.
Description of drawings
To more fully understand the present invention by detailed explanation and accompanying drawing, wherein:
Figure 1A and Figure 1B are the functional block diagrams that shows grand with the compound logic that piles up of two times of normal voltage level and half normal levels work in module respectively;
Fig. 2 A and Fig. 2 B are the functional block diagrams that shows the grand and module of the compound logic that piles up with current balance module respectively;
Fig. 3 A and Fig. 3 B show the functional block diagram that is carried out the grand and module of the balanced compound logic that piles up by buck converter;
Fig. 4 A and Fig. 4 B show the functional block diagram that is carried out the grand and module of the balanced compound logic that piles up by 2: 1 DC/DC converters;
Fig. 5 A and Fig. 5 B show the functional block diagram that is carried out the grand and module of the balanced compound logic that piles up by the first exemplary equalizer switch capacitor element;
Fig. 6 A and Fig. 6 B show the functional block diagram that is carried out the grand and module of the balanced compound logic that piles up by the second exemplary equalizer switch capacitor element;
Fig. 7 A and Fig. 7 B show by linearity and recommend the functional block diagram that adjuster carries out the grand and module of the balanced compound logic that piles up;
Fig. 8 A and Fig. 8 B show the functional block diagram that is carried out the grand and module of the balanced compound logic that piles up by hysteresis comparator;
Fig. 9 A shows according to prior art and uses DC/DC converter and 2: the 1 converters functional block diagram to module or grand supply voltage and current;
Fig. 9 B shows the functional block diagram of implementations more according to the present invention to two modules of piling up or grand supply voltage and current;
Fig. 9 C shows the functional block diagram of the implementation other according to the present invention to four modules of piling up or grand supply voltage and current;
Figure 10 A shows the functional block diagram of the communication equipment that comprises a plurality of communication channels, and wherein each communication channel has a signal processor;
Figure 10 B shows the functional block diagram to the communication equipment supply voltage and current of Figure 10 A;
Figure 11 A shows the functional block diagram of the Graphics Processing Unit (GPU) that comprises a plurality of graphics pipeline modules;
Figure 11 B shows the functional block diagram to the connection of the graphics pipeline module supply voltage and current of Figure 11 A;
Figure 12 shows the functional block diagram of first and second processors, power regulation module and optional current balance module, wherein the current drain of balanced first and second processing of power regulation module;
Figure 13 A shows first and second processors, frequency equilibrium module and optional 2: the functional block diagram of 1DC/DC converter, and wherein the frequency equilibrium module reduces poor between the operating frequency of first and second processors, to reduce the unbalanced of electric current;
Figure 13 B shows the functional block diagram of the exemplary layout of first and second processors on the semiconductor element and 2: 1 DC/DC converters;
Figure 13 C shows the packaging part of semiconductor element of Figure 13 B and the end view of the external inductance on the PCB; And
Figure 14 shows the functional block diagram of first and second processors, operating system and optional current balance module, wherein the current drain of balanced first and second processors of operating system.
Embodiment
Explanation to (one or more) preferred embodiment only is exemplary below, is not to limit the present invention and application or use.For the sake of clarity, will use identical label to identify similar element in the accompanying drawing.As used herein, the processor (share, special-purpose or group) that term module refers to application-specific integrated circuit (ASIC) (ASIC), electronic circuit, the one or more softwares of execution or firmware program and memory, microprocessor subsystem, combinational logic circuit, compound logic is grand and/or other suitable assemblies of described function are provided.
With reference to Figure 1A and Figure 1B, the present invention self piles up to overcome actual dead resistance obstacle many group devices (for example compound logic is grand and/or module).In Figure 1A, compound logic grand 20 and 24 self piles up and is connected V
DDAnd V
LBetween.In some implementations, V
LCan be ground.In Figure 1B, module 30 and 34 self is piled up and is connected V
DDAnd V
LBetween.If compound logic grand 20 and 24 or the multiplicity of module 30 and 34 by approximate two equal portions that are divided into, and if this two halves approximately equal ground operation, then the electric current demand is approximately non-half of device of piling up.
The working voltage of the device that piles up is non-twice of piling up device.Yet, can not guarantee compound logic grand 20 and 24 or module 30 and 34 both will consume essentially identical levels of current.The problem that this seemingly may solve hardly is unless can make two halves absorb the essentially identical magnitude of current.The voltage drop of in fact having no idea to guarantee this two halves is to be applied to half of total voltage on the entire device.
With reference now to Fig. 2 A and Fig. 2 B,, current balance module 50 according to the present invention is connected to V
DD, V
LAnd/or logic macro 20 and 24 or module 30 and 34 between node 52 at least one.Current balance module 50 is attempted stable market supply to logic macro 20 and 24 or the magnitude of current of module 30 and 34.Particularly, current balance module 50 is with (V
DD-V
L) approximate 1/2 compound logic grand 20 and 24 that is fed among Fig. 2 A in each or Fig. 2 B in module 30 and 34 in each.Exemplary current balance module 50 comprises that buck converter, 2: 1 DC/DC converters, linearities recommend adjuster, low pressure drop (low drop-out, LDO) adjuster, equalizer switch capacitor element, switched inductors device, capacitive/inductive device, hysteresis comparator and/or other similar devices, this will further describe hereinafter.
With reference to figure 3A and Fig. 3 B, the grand or module of the shown compound logic that piles up is carried out equilibrium by buck converter 68.Buck converter 68 can have the topological structure shown in Fig. 3 A and the 3B and/or any other suitable topological structure.Buck converter 68 comprises conductive switch 70 and freely turns round switch 72.Control module 73 produces the drive signal that is used for switch 70 and 72.Control module 73 can sense node 52 places voltage and/or electric current, and come control switch based on this.In some implementations, switch 70 and 72 has inverse state.One end of inductance element 78 is connected between switch 70 and 72, the other end be connected compound logic grand 20 and 24 or module 30 and 34 between.Buck converter 68 absorbs or sends electric current to provide balanced.
With reference now to Fig. 4 A and Fig. 4 B,, show a kind of implementation, thereby be used for making the voltage approximately equal of seeing on this two halves at euqalizing current between the two halves.In Fig. 4 A, balanced action is to have passed through to utilize 2: 1 DC/DC converters 100 of coupling inductor 104 to finish.The U.S. Patent application No.10/693 that further details of operation was submitted on October 24th, 2003 sets forth among 787 " the Voltage Regulator ", and this patent application is incorporated into this by reference in full.
2: 1 DC/DC converters 100 comprise two buck converters with the phase difference work of 180 degree, with from input voltage V
DDProduce output voltage V
OUTEach buck converter comprises conductive switch 110a or 110b, freely turns round switch 114a or 114b and inductor 104a or 104b.Output capacitance 118 is carried out filtering to the output voltage of each buck converter.Owing to have negligible ripple current, so the value of output capacitance 118 can be reduced.In addition and since the input and output of 2: 1 DC/DC converters 100 between close-coupled, any electric capacity of input all with output capacitance 118 collaborative works, so that the shunt capacitance of output place load effectively to be provided.Control module 119 produces the drive signal that is used for switch 110a, 110b, 114a and 114b.Control module 119 can sense node 52 places voltage or electric current, and come control switch based on this.
Start-up circuit 130 optionally is provided, and is maintained at less than V between the starting period to guarantee node 52
DDThe voltage place.In some implementations, node is maintained at approximate V between the starting period
DD/ 2.In some implementations, start-up circuit 130 comprises one or more capacitors.Perhaps, V
DDCan increase between the starting period or the slope on rise and prevent the overvoltage at module two ends, and guarantee that node 52 is in and be maintained at approximate V between the starting period
DD/ 2 and/or less than threshold voltage V
TH(threshold voltage V
THLess than V
DD) at least a situation.Threshold value V
THShould be less than the voltage that will cause grand and/or module damage.
In Fig. 4 B, the output capacitance 118 of Fig. 4 A is marked as 118B.Can add another electric capacity 118A alternatively to guarantee grand and/or module receives and is no more than V between the starting period
THAnd/or approximate V
DD/ 2 voltage.Perhaps, V
DDCan on increase or slope between the starting period, rise and prevent overvoltage grand and/or the module two ends.Can also use the method for other deboosts between the starting period.In some implementations, the capacitance of electric capacity is set to equal substantially.
In some implementations, inductor 104a and 104b can close-coupled be in the same place, and have and be approximately 1 coupling coefficient K.Inductor 104a and 104b can be wrapped in the electrical inductor assembly 104 that the high coupling coefficient between inductor 104a and the 104b is provided with formation on the shared magnetic core.Select the polarity of inductor winding, the DC electric current of feasible flow through inductor 104a and 104b is approximate offsets the magnetic core of electrical inductor assembly 104 thereby the DC electric current of approximate zero is flowed through.Therefore, inductor 104a and 104b can use the core of the reduced size of being made by low magnetic permeability material, make the littler and cost of the size (volume) of electrical inductor assembly 104 reduce.In addition, consider the transient load electric current, the transient response of 2: 1 DC/DC converters 100 is owing to the counteracting of each inductance is improved.
Any overcurrent, no matter be from or enter the compound logic that piles up grand 20 and 24 or the node 52 of module 30 and 34, all will be absorbed back main power source with approximate 95% efficient by 2: 1 DC/DC converters 100.After startup, 2: 1 DC/DC converters 100 guarantee compound logics grand 20 and 24 or the two halves of module 30 and 34 on the voltage approximately equal seen.Suppose that this two halves has the highest 25% mismatch aspect levels of current, then 2: 1 DC/DC converters 100 need to absorb or send entire device half electric current 25%, perhaps 1/8 of whole electric current.
With reference to the initial current demand is the microprocessor example of 100A, and DC/DC converter 100 need absorb or send the electric current less than 12.5A in 2: 1.This can easily utilize integrated power MOSFET in the microprocessor die and single 1: 1 coupling inductor 104 that is installed under the microprocessor package part to realize, as Figure 13 A～13C that describes below is shown.
The U.S. Patent application No.10/810 that submits on March 26th, 2004, the U.S. Patent application No.10/693 that 452 " VoltageRegulator ", on October 24th, 2003 submit, the U.S. Patent application No.10/754 that 787 " Voltage Regulator " and on January 8th, 2004 submit, shown in 187 " the Digital Low Dropout Regulator " and buck converter and 2: 1 converter topology structures that other are suitable be described, they are incorporated into this by reference in full.
With reference now to Fig. 5 A and Fig. 5 B,, compound logic grand 20 and 24 or the stacked structure of module 30 and 34 not only useful for high power semiconductor device, and for purpose is the low-power integrated-circuit of use in the hand-held market (for example PDA(Personal Digital Assistant), MP3 player, portable satellite broadcasting, cell phone etc.), also be useful.In many handheld application, can use a limited number of DC/DC converter to produce the required different low voltage power supply level of operation modem semi-conductor devices.
Compound logic is grand or module can under low pressure be worked and combination stacked voltage can be used for moving the application of the simulation part of integrated circuit for two, the compound logic that piles up grand 20 and 24 or module 30 and 34 be suitable for.For example, the device with 1.8V simulation power supply can be used for the two halves of the embedded logic that moves under 0.9V is powered.Current difference between the two halves still needs to solve.
In this case, equalizer switch capacitor element 150 can be used between two halves back and forth switching current, and is shown as Fig. 5 A and Fig. 5 B.The electric current and/or the voltage at control module 154 sense node 164 places, and control switch 158 and 160 are to change capacitor C
1And C
2Discharge and recharge.Equalizing capacitor C
1And C
2Reciprocating action can be used for guaranteeing the voltage approximately equal of two halves, even when between two halves, having electric current demand unbalanced.In some implementations, C
1Capacitance be set to equal substantially C
2Capacitance, to prevent between the starting period overvoltage at module 20 and 24 two ends.In other words, between the starting period, node 164 is held less than V
THAnd/or be approximately equal to V
DD/ 2.Although show equalizer switch capacitor element, those skilled in the art will recognize that, also can use switched inductors device and/or switching capacity/inductance component.
With reference now to Fig. 6 A and Fig. 6 B,, the another kind of equalizer switch capacitor element that illustrates comprises capacitor C
1, C
2And C
3, switch 180,182,184 and 186.Switched capacitor module 192 control switchs 180～186 are to absorb from the electric current of node 192 or to send electric current to node 192.In some implementations, switch 180 and 184 is as a pair of and by switch, and switch 182 and 186 is also as a pair of and by switch, and they have opposite state.Switching capacity module 190 can sense node 192 places curtage, and come control switch based on this.Equalizing capacitor C
1, C
2And C
3Reciprocating action can be used for guaranteeing the voltage approximately equal of two halves, even when between two halves, existing the electric current demand unbalanced.
With reference now to Fig. 7 A and Fig. 7 B,, under the condition of some efficient of forfeiture, can use linearity to recommend adjuster 200.If two halves is designed to relative equilibrium, then Sang Shi efficient should be minimum.This method is significantly better than linear regulator, and linear regulator generally only has 50% efficient.However, also can use linear regulator in some implementations.
Linearity is recommended adjuster 200 and is comprised first and second operational amplifiers 204 and 208, and operational amplifier 204 and 208 output are communicated with the control terminal of transistor T 1 and T2 respectively.In some implementations, transistor T 1 and T2 are the CMOS transistors.The first terminal of transistor T 1 is coupled to V
DDSecond terminal of transistor T 1 is coupled to the first terminal of transistor T 2.Second terminal of transistor T 2 is coupled to V
LHigher voltage thresholds V is coupled in the positive input of operational amplifier 204
UL, and low voltage threshold value V is coupled in the input of the positive of operational amplifier 208
LLThe anti-phase input of operational amplifier 204 and an end of resistance R are coupled in the anti-phase input of operational amplifier 208.The other end of resistance R is coupled to second and the first terminal of first and second transistor Ts 1 and T2 respectively.Second and the first terminal of first and second transistor Ts 1 and T2 also is coupled to node 210 between first and second logic macros 20 and 24 among Fig. 7 A or the node 210 between first and second modules 30 and 34 among Fig. 7 B respectively.
When node 210 compares target voltage
Little first threshold
The time, the voltage that top logic macro or module descend is too much.Top operational amplifier 204 of short duration turn-on transistor T1, transistor T 1 is with V
DDBe applied to node 210.The V at node 210 places
DDDraw high the voltage at logic macro or module 24 or 34 two ends, and reduced the voltage at logic macro or module 20 or 30 two ends.Work as V
DDWhen being applied to node 210, operational amplifier 204 turn-offs T1, and process is repeated until that difference is less than first threshold.
When node 210 compares target voltage
Big second threshold value
The time, the voltage that following logic macro or module descend is too much.Following operational amplifier 208 of short duration turn-on transistor T2, transistor T 2 is with V
LBe applied to node 210.The V at node 210 places
LDraw high the voltage at logic macro or module 20 or 30 two ends, and reduced the voltage at logic macro or module 24 or 34 two ends.Work as V
LWhen being applied to node 210, operational amplifier 208 turn-offs T2, and process is repeated until that difference is less than first threshold.
Can recognize, can use the adjuster of any kind.Except above-described implementation, can use other types the DC/DC converter, recommend adjuster and switching capacity device.Can also use the adjuster of other types, include but not limited to hysteresis comparator.For example, suitable hysteresis comparator comprises the U.S. Patent application No.10/602 that on June 23rd, 2003 submitted, those hysteresis comparators that also illustrate shown in 997 " the Simplified Comparator with Digitally Controllable Hysteresis andBandwidth ", it is incorporated into this by reference in full.
In Fig. 7 B, first and second capacitor C are provided
1And C
2With the voltage limit at module between the starting period 30 and 34 two ends is less than V
THAnd/or be approximately equal to V
DD/ 2.In some implementations, capacitor C
1Capacitance equal C substantially
2Capacitance.In other words, node 210 is maintained at approximate V between the starting period
DD/ 2.
With reference now to Fig. 8 A and 8B,, hysteresis comparator 250 and 254 is used for adjusting logic macro 20 and 24 or the voltage at module 30 and 34 two ends.Comparator 250 receives V
DD, higher voltage thresholds V
ULAnd the voltage at node 210 places.In some implementations, comparator 250 has fixing or adjustable bias 256, bandwidth 258 and/or postpone 260.If adjustable, then comparator 254 receives the one or more corresponding input that is used to adjust accordingly.Comparator 254 receives V
L, low voltage threshold value V
LLAnd the voltage at node 210 places.
When node 210 compares target voltage
Little higher thresholds
The time, the voltage that top logic macro or module descend is too much.Comparator 250 is with V
DDBe applied to node 210.The V at node 210 places
DDDraw high the voltage at logic macro or module 24 or 34 two ends, and reduced the voltage at logic macro or module 20 or 30 two ends.Work as V
DDBe applied to 210 1 of nodes and postpone after the period, comparator 250 stops V
DDBe applied to node 210.Process is repeated until that difference is less than higher thresholds.
When node 210 compares target voltage
Big low threshold value
The time, the voltage that following logic macro or module descend is too much.Comparator 254 is with V
LBe applied to node 210.The V at node 210 places
LDraw high the voltage at logic macro or module 20 or 30 two ends, and reduced the voltage at logic macro or module 24 or 34 two ends.Work as V
LBe applied to 210 1 of nodes and postpone after the period, comparator 254 stops V
LBe applied to node 210.Process is repeated until that difference is less than low threshold value.
In addition, those skilled in the art will recognize that,, also can use inferior the piling up of other grades although show the logic macro of two-stage and piling up of module.Can also use other equalization methods.
With reference now to Fig. 9 A,, DC/DC converter 300 receiving inputted signals also produce 4V and the output of 25A.The one 2: 1 converter 304 is transformed to the input of 4V, 25A the output of 2V, 50A.Second converter 308 is transformed to the input of 2V, 50A the output of 1V, 100A.Grand or the module 312 of encapsulation can be connected to the output of 2: 1 converters 308 via resistance 310 (dead resistance that on behalf of trace, it can be connected with other) on printed circuit board (PCB) (PCB) 314.Can recognize that the loss that is produced by dead resistance 310 equals I
2R, wherein I is the electric current of dead resistance R of flowing through.With reference now to Fig. 9 B,,, as mentioned above,, loss can be reduced 4 times by between a pair of grand or module of 324 and 328 places sign, connecting 2: 1 converters 320 (or other current balance modules) according to the present invention.
With reference now to Fig. 9 C,, other module can connect 2: 1 other converters.In Fig. 9 C, four modules or grand 340,342,344 and 346 are connected in series, and have node 347,348 and 349 in the middle of their.The one 2: 1 converter 330 is connected to the output, module or grand 340 and node 348 of DC/DC converter 300.Node 348 is also connected to 2: 1 converters 334 and 336 and module or grand 342 and 344.2: 1 converters 334 are also connected to the output, module or grand 340 and node 347 and 348 of DC/DC converter 300, as shown in the figure.Converter 336 was also connected to node 348 and 349 in 2: 1, as shown in the figure.2: 1 converters 320 can be handled all less than 2: 1 converter 308,2: 1 converters 38 and flow to the electric current of PCB.On the contrary, 2: 1 converters 320 only need to handle the current mismatch of piling up between the device.
More usually, comprise 2 when circuit
nIndividual module or when grand, it will comprise 2
n-12: 1
The DC/DC converter.2: the 1DC/DC converter can be with the arranged in form of n branch road.2
n-12: 1 DC/DC converter has 2 between contiguous DC/DC converter
n-1 node.2
nIn-1 2: 1 DC/DC converter each is connected to 2
nCorresponding one of-1 node.
For example in Fig. 9 C, two branch roads 350 and 352 are arranged.First branch road 350 comprises 2: 1 converter and second branch road comprises two 2: 1 DC/DC converters.More usually, first branch road comprises 2
0=12: 1 DC/DC converter, second branch road comprises 2
1=22: 1 DC/DC converters, the 3rd branch road comprises 2
2=42: 1 DC/DC converters ..., and the n branch road comprises 2
N-1Individual 2: 1 DC/DC converters.
With reference now to Figure 10 A and Figure 10 B,, generally include a plurality of communication channel 364-1,364-2,364-3 and 364-4 (being referred to as channel 364) such as the communication equipment 360 of router, switch or other network equipments.Although only show four signal processor module, can use extra signal processor right.Each channel 364 comprises signal processor 366-1,366-2,366-3 and 366-4 (being referred to as signal processor 366).Because each in the signal processor 366 has identical design usually, so signal processor module 366 trends towards sucking the approximately uniform magnitude of current during operation.Current balance module 370 (as mentioned or hereinafter described) can be provided and be used for the difference that euqalizing current consumes.Because the mismatch degree will be very low,, can certainly use other current balance module so can use inefficient device (for example linear ldo regulator).For example, communication channel can meet 1000Base-T ethernet standard, 10Gbase-T ethernet standard or other current or following ethernet standards or other standards.
With reference now to Figure 11 A and Figure 11 B,, Graphics Processing Unit (GPU) 380 comprise a plurality of graphics pipeline module 382-1,383-2 ... and 382-N (being referred to as graphics pipeline module 382).Because each in the graphics pipeline module 382 has identical design, so graphics pipeline module 382 trends towards sucking the identical magnitude of current during operation.Current balance module 390 (as mentioned or hereinafter described) can be provided and be used for the difference that euqalizing current consumes.
With reference now to Figure 12,, first and second processors 400 are communicated by letter with power regulation module 404 with 402, power regulation module 404 balanced first and second processors 400 and 402 current drain.In some implementations, power regulation module 404 be based on hardware, based on software and/or based on hardware and software.In some implementations, the relative operating frequency of power regulation module 404 adjustment first and second processors is attempted euqalizing current consumption.Power regulation module 404 can also use the load balancing of first and second processors 400 and 402 and/or throttling to attempt euqalizing current consumption.In some implementations, power regulation module 404 is used in combination with optional current balance module 406, as mentioned and hereinafter described like that.In other words, power regulation module 404 is carried out thick equilibriums and the current balance module is carried out meticulous current balance.
With reference now to Figure 13 A, Figure 13 B and Figure 13 C,, power management module 404 comprise frequency equilibrium module 404 '.Optional 2: 1 DC/DC converters 406 ' also can be used to euqalizing current consumption further.In Figure 13 B, 2: 1 DC/DC converters 406 ' and the exemplary layout of first and second processors 400 and 402 be shown as and be manufactured on the semiconductor element 408.In Figure 13 C, the semiconductor element 408 of Figure 13 B is connected to PCB 412 by first and second slots 414 and 416 that are arranged on the PCB 412.In certain embodiments, the above-described inductor 420 and 422 that is associated with 2: 1 DC/DC converters 406 is disposed between semiconductor element 408 and the PCB 412.Pin 426 stretches out and is received by slot 414 and 416 from tube core 408.Although the power management module that illustrates 404 comprise frequency equilibrium module 404 ', those skilled in the art will recognize that, can with above and/or any mode described below carry out the hardware and/or the software equilibrium of electric current.
With reference now to Figure 14,, power regulation module 404 comprises operating system 404 ".OS 404, and " or chip can carry out load balancing for first and second processors 400 and 402 by distributing thread." or chip can carry out throttling to first and/or second processor 400 and 402 to OS404, makes that the current unevenness weighing apparatus is very little.For example, CPU speed can followingly be provided with:
| Speed | ||||
| CPU1 or CPU2 | 1GHZ | 2GHZ | 3GHZ | 4GHZ |
| CPU2 or CPU1 | 0GHZ | 1GHZ | 2GHZ | 3GHZ |
1/2 each CPU of operation with peak frequency is more efficient, because each CPU can be with lower voltage operation.In some implementations, one operating frequency among the CPU is lowered and/or is increased, with the current drain of balanced other CPU.Perhaps, can at least one CPU, carry out do-nothing operation (dummy operation), with equilibrium otherwise with the current unevenness weighing apparatus that takes place.
Again with reference to figure 4A, Fig. 4 B, Fig. 5 A and Fig. 7 B, circuit and/or capacitor are used to guarantee that the voltages at nodes between grand and/or the module remains on V between the starting period
THUnder and/or be in approximate V
DD/ 2.Those skilled in the art will recognize that other implementations that illustrate and illustrate also can comprise and be used between the starting period node between grand and/or the module being maintained V here
THUnder and/or at approximate V
DDThe circuit at/2 places and/or capacitor.
Those skilled in the art can recognize from above stated specification that now broad teachings of the present invention can realize in a variety of forms.Therefore, although combine specific embodiment the present invention is described, but true scope of the present invention should not limited by them, because after having studied accompanying drawing, specification and claim, other modification will become apparent for those of ordinary skills.
Claims (4)
1. treatment system comprises:
First processing module;
Second processing module of communicating by letter with described first processing module,
Wherein said first and second processing modules are connected in series between first reference potential and second reference potential;
With the operating system that described first and second processing modules are communicated by letter, this operating system is carried out the load balancing of described first and second processing modules and/or at least one in the throttling, and is poor with the current drain that reduces between described first and second processing modules.
2. treatment system as claimed in claim 1 also comprises:
The current balance module that is communicated with node between described first and second processing modules, the current drain that this module reduces between described first and second processing modules is poor.
3. method comprises:
First processing module is provided;
Second processing module of communicating by letter with described first processing module is provided,
Wherein said first and second processing modules are connected in series between first reference potential and second reference potential;
Carry out the load balancing of described first and second processing modules and/or at least one in the throttling, poor with the current drain that reduces between described first and second processing modules.
4. method as claimed in claim 3 also comprises:
The current drain that reduces between described first and second processing modules is poor.
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|---|---|---|---|
| US63155204P | 2004-11-29 | 2004-11-29 | |
| US60/631,552 | 2004-11-29 | ||
| US66393305P | 2005-03-21 | 2005-03-21 | |
| US60/663,933 | 2005-03-21 | ||
| US11/098,129 | 2005-04-04 | ||
| US11/098,129 US7594127B2 (en) | 2004-11-29 | 2005-04-04 | Low voltage logic operation using higher voltage supply levels |
| US11/179,106 | 2005-07-12 | ||
| US11/179,106 US7702929B2 (en) | 2004-11-29 | 2005-07-12 | Low voltage logic operation using higher voltage supply levels |
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| CN1812095A true CN1812095A (en) | 2006-08-02 |
| CN1812095B CN1812095B (en) | 2011-04-13 |
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| CN 200510114983 Active CN1812094B (en) | 2004-11-29 | 2005-11-16 | Low voltage logic operation using higher voltage supply levels |
| CN 200510114988 Active CN1812095B (en) | 2004-11-29 | 2005-11-16 | Low voltage logic operation using higher voltage supply levels |
| CN 200510114984 Active CN1812238B (en) | 2004-11-29 | 2005-11-16 | Low-voltage logical operation using higher voltage power supply electrical level |
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| CN105045364A (en) * | 2015-07-21 | 2015-11-11 | 北京比特大陆科技有限公司 | Serial power supply circuit, virtual digital coin mining machine and computer server |
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| JPH10163842A (en) * | 1996-11-25 | 1998-06-19 | Fujitsu Ltd | Semiconductor integrated circuit |
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Effective date of registration: 20200424 Address after: Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Ford street, Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. Effective date of registration: 20200424 Address after: Ford street, Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Hamilton, Bermuda Patentee before: Marvell International Ltd. Effective date of registration: 20200424 Address after: Hamilton, Bermuda Patentee after: Marvell International Ltd. Address before: Babado J San Michael Patentee before: MARVELL WORLD TRADE Ltd. |
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| TR01 | Transfer of patent right |