CN1806341A - Field effect transistor, especially a double diffused field effect transistor, and method for the production thereof - Google Patents

Field effect transistor, especially a double diffused field effect transistor, and method for the production thereof Download PDF

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Publication number
CN1806341A
CN1806341A CNA2004800164222A CN200480016422A CN1806341A CN 1806341 A CN1806341 A CN 1806341A CN A2004800164222 A CNA2004800164222 A CN A2004800164222A CN 200480016422 A CN200480016422 A CN 200480016422A CN 1806341 A CN1806341 A CN 1806341A
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groove
effect transistor
bonding pad
field
controlled area
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CN100583448C (en
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K·米勒
K·勒施劳
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

The invention relates to, amongst other things, a field effect transistor (10) wherein a control area (36) and a connection area (40) are arranged in an insulation trench (34) thereof. A field effect transistor (10) with excellent electrical properties is provided by virtue of said arrangement.

Description

Field-effect transistor, particularly bilateral diffusion field-effect tranisistor, and manufacture method
The present invention relates to field-effect transistor, it mainly comprises following element:
The drift region,
Connect the groove of drift region, it comprises a slot wedge, some sidewalls and trench bottom.
The field-effect transistor controlled area also is called grid, and it is positioned in the groove.
Two field-effect transistor bonding pads are also referred to as source-drain area, and current flowing is wherein arranged, and this electric current also flows through inversion channel and drift region, and
Form this tagma of field-effect transistor inversion channel, it is opened by dielectric and controlled area insulation.
The present invention relates to have the MOS transistor or DMOS (double-diffused metal oxide semiconductor) transistor of drift path, wherein the contact of controlled area and bonding pad is in the plane, and the result can constitute an integrated circuit (IC) apparatus.For example in the DMOS transistor, bonding pad and this tagma produce by diffusion.The drain region is connected with the drift region.The source region is connected with this tagma.
An object of the present invention is to describe in detail a kind of field-effect transistor, its manufacturing is simple and volume is little, especially has good electrical characteristic.In addition, also to describe a kind of method of making field-effect transistor in detail.
The purpose of this relevant field-effect transistor can utilize a kind of field-effect transistor with the described feature of back claim 1 to reach.Its various forms has detailed description in the dependent claims.
Except the feature of speaking of in the foreword in the above, field-effect transistor of the present invention also comprises following feature:
Outside groove, settle a bonding pad, best mode according to the zone that is connected to form the field-effect transistor inversion channel, and
Another bonding pad or its part are placed in the groove, also have the controlled area of field-effect transistor in groove, and this another bonding pad preferably connects the bonding pad of drift region.
This means that under the situation of field-effect transistor of the present invention one in controlled area and the bonding pad all is to be placed in the same groove.Can reduce actual required chip area by this arrangement.Especially all the more so when having required groove for the purpose that insulate.Allow groove have certain depth that the length of drift path for example can be born less than 30 volts or less than 40 volts drain-source voltage, or greater than 30 volts or 40 volts, particularly less than 100 volts voltage.
Also can obtain to have the field-effect transistor that low initial resistivity RON multiply by area and high unit are saturation current ISAT according to device of the present invention.The arrangement in groove of controlled area and bonding pad makes only needs few several steps in the production method.In addition, realize that different field-effect transistor characteristic electrons also has number of ways.
By in a kind of form of field-effect transistor of the present invention, insulating material is positioned between the trench bottom and controlled area under the controlled area.Boundary between controlled area and insulating material is in the groove the first half that comprises the controlled area or comprise on the groove of controlled area in 1/3 part.In a kind of improved form, two interregional borders are with parallel at the bottom of the deep trench.The zone of tape insulation material is used for setting the length of drift path.Therefore the controlled area only extends for example degree of depth of 500nm downwards.But the deep-seated of fill insulant is put and is arrived still that for example 1 μ m is above even the degree of depth of 8 μ m in the groove.Long insulating regions makes does not need extra chip area just can obtain high dielectric strength.But, the insulating regions electric conducting material that also can be used in each limit electric insulation is filled.
In another form, groove reaches under the controlled area than darker under the bonding pad in reaching.In a kind of improved form, groove reaches under the controlled area than dark one times or twice under the bonding pad in reaching.This moment, the drift region was in dark insulating material both sides, and the length of result drift region under identical gash depth almost doubles.
In another form, groove is dark under interior bonding pad than under the controlled area.This situation is created in the occasion of shallow trench, and promptly the degree of depth of groove is less than 1 μ m, particularly less than the occasion of 500nm.Under this occasion, the bottom of shallow trench must be passed in interior bonding pad, could contact reliably with the drift region.
In another form, groove does not contain single-crystal semiconductor material.Groove can be filled with polycrystalline semiconductor material and electrical insulating material by plain mode.
Mix by first doping type in the controlled area, preferably the n type mixes.In a kind of improved form, equally also mix by first doping type in the bonding pad, and promptly the n type mixes, and preferably allows the bonding pad do the doping of severe, and for example every cubic centimetre has 10 19Or 10 20Foreign atom.
The zone suggestion that forms inversion channel is mixed with the P type.Preferably mix by first doping type especially n type in the drift region.For producing bigger voltage drop, the doping of drift region is low weight.For example, doped region has 10 for every cubic centimetre 15Foreign atom.
In another improved form, the doping of interior bonding pad is heavier than the doping of drift region.Also have in a kind of improved form, outer bonding pad, the join domain of drift region and inversion channel is positioned in the single-crystal semiconductor material (preferably monocrystalline silicon).
In another form, field-effect transistor is integrated in the integrated circuit, other also is housed with the element that interconnection line connects in this integrated circuit, for example is used for the control circuit element of Driving Field effect transistor.But, also can make resolution element to field-effect transistor of the present invention or its a kind of form.
In one form, this field-effect transistor comprises one than the drift region layer that mixes of severe more, and it is field-effect transistor and insulated substrate, and substrate then mixes by the different doping type of severe doped layer therewith.This form is used in two kinds of circuit of band bipolar transistor and field-effect transistor, BiCMOS circuit for example, and when field-effect transistor be to be created in a kind of like this integrated circuit, wherein have only field-effect transistor, and except that parasitic transistor, do not have what bipolar transistor.
In another form, groove just in time reaches the severe doped layer, makes the severe doped layer also be used as a bonding pad of drift region.In also having a kind of form, groove is positioned in and leaves distance of severe doped layer.Utilize this structure, also can be with the zone between groove and severe doped layer as drift path.
In another form, groove has two ends, and another controlled area preferably is placed in the groove.In this form, preferably groove is made form of straight lines.This form is particularly suitable for some specific metals, and this moment is because electric migration process can only be carried particular current density.
In another form, groove forms a ring, and annular controlled area is preferably around interior bonding pad.Utilize this ring-shaped groove on little chip area, to produce field-effect transistor.
The invention still further relates to a kind of method of producing field-effect transistor, particularly, make abovementioned technology can be used for this method by field-effect transistor of the present invention or its a kind of form.In the method, can implement following steps, but to listed order without any restriction:
In the drift region, introduce groove,
With this groove of filling insulating material,
Insulating material is made certain figure, produce otch in the controlled area of field-effect transistor thus, and produce otch in the bonding pad of field-effect transistor, back a kerf is what to separate with preceding a kerf,
Be preferably in interior at least one bonding pad of groove with gate oxidation and opening, this can etch away by lithography step and with the gate oxide in the bonding pad and realize,
The material that electric conducting material maybe can be converted into electric conducting material is introduced in two otch; Electric conducting material can be used as grid on the one hand, can be used as the drain contact of crystal region on the other hand.
Formation is placed in the bonding pad of groove outside, and forms the zone that constitutes field-effect transistor inversion channel district before or after forming groove.
In one form, groove is kept this gash depth by intensification at another regional area at least at a regional area at least, thereby produces the many trench regions with mutually different gash depth.This form just can realize without extra treatment step, and is especially all the more so in the time in the integrated circuit that comprises field-effect transistor dark insulated trench and shallow insulated trench must being arranged.
In a form of this method, each otch is etched into channel bottom always, and insulating material is moved in the trench wall district of controlled area otch.After this, by thermal oxidation, produce high quality oxide on the trench wall zone that is not capped in the otch of controlled area, promptly gate oxide then moved on to this oxide in the otch of bonding pad before adding electric conducting material again.
In another embodiment of this method, otch differs and heads straight for channel bottom, and allows kerf bottom leave for example above distance of 100nm of one of channel bottom.But insulating material is moved in the trench wall district of controlled area otch.Then, by means of thermal oxidation, in the otch of controlled area, produce high-quality dielectric.Then the otch of bonding pad is deepened to channel bottom always.
In another embodiment of this method, the bonding pad is created in the groove outside in the mode that connects slot wedge, and this bonding pad preferably has independent injection scope, and its doping is lighter than the bonding pad.
Exemplary embodiments more of the present invention are described with reference to the accompanying drawings, wherein:
Fig. 1 represents a shallow insulated trench DMOS transistor;
Fig. 2 represents a dark insulated trench DMOS transistor;
Fig. 3 represents a DMOS transistor with insulated trench of the variable grooves degree of depth;
Fig. 4 represents an annular DMOS transistor;
Fig. 5 represents a bar shaped DMOS transistor.
Fig. 1 is a DMOS transistor 10, and it is the part of an integrated circuit.This integrated circuit is made on the substrate 12, and the latter is made of for example slight P type doped silicon.Be a doped epitaxial layer 14 on the surface of substrate 12, its thickness is greater than 1.5 μ m or greater than 2.0 μ m.
In n type epitaxial loayer 14, along with the increase of substrate 12 distances forms:
N type dopant well 16,
P type doped channel form district 18,20 and
The bonding pad, source 22,24 that severe n type mixes on epitaxial loayer 14 surfaces is respectively applied for the severe P type doping bonding pad 26,28 of raceway groove bonding pad 18 and 20, and the slight n type doping lengthening zone 30,32 that is respectively applied for bonding pad, source 22 and 24.Lengthening zone 30,32 can be selected on demand, can in another exemplary embodiments.
The core of transistor 10 comprises shallow trench 34, has two severe n type doped gate zones 36,38 to be placed in fringe region in this groove, and severe n type doped drain 40 is placed in core.Drain region 40 is insulated zone 42 and isolates with grid region 36, and is insulated zone 44 and isolates with grid region 38. Insulating regions 42 and 44 is in the groove 34 similarly.On the channel bottom below the grid region 36 and 38 of the trench wall of groove 34 and groove 34 is a thin dielectric layer, it make grid region 36 and 38 and n type dopant well 16 isolate, and isolate with channel formation region 18,20 respectively, and isolate with lengthening district 30 and 32 respectively.As an example, silicon dioxide or some other material are suitable as insulating material.
Also have other insulated trenchs 46 to 52 and 34 formation of groove, they have the identical degree of depth, as 0.5 μ m.Transistor 10 connects insulated trenchs 48 and 50 and some isolation wells that below will further specify and other element electric insulation of integrated circuit (IC) apparatus by two.In an exemplary embodiments, some zones that these two insulated trenchs 48 and 50 also are annular insulated trenchs (referring to following explanation) to Fig. 4.
In the exemplary embodiments of reference Fig. 1 illustration, body bonding pad 26, bonding pad, source 22, and lengthening district 30 all is between insulated trench 48 and the groove 34.Lengthening district 32, bonding pad, source 24, and body bonding pad 28 all is between insulated trench 34 and 50.
With the transistor 10 of field effect work side by side, also have some npn and pnp bipolar transistor in its right and left side integrated circuit (IC) apparatus.On the left side of transistor 10, there is a P type doping buried horizon 54 to be in the zone of the zone of substrate 12 and epitaxial loayer 14, this buried horizon is as the insulation bipolar transistor.On the right of transistor 10, same buried horizon 56 as the insulation bipolar transistor is on the identical height with buried horizon 54.Buried horizon 54 is connected with severe P type doping bonding pad 60 by epitaxial loayer 14 lip-deep P type doping bonding pads 58.Buried horizon 56 is connected with severe P type doping bonding pad 64 by epitaxial loayer 14 lip-deep P type doping bonding pads 62.Bonding pad 60 is between insulated trench 46 and 58.In contrast, bonding pad 64 is between insulated trench 50 and 52.
Being positioned at below the field-effect transistor 10 is the buried horizon 70 that a severe n type mixes, and its sub-fraction is in the epitaxial loayer 14, and major part is in the p type doped substrate 12.Buried horizon is used for transistor 10 and substrate 12 insulation.In another embodiment, there is not buried horizon.
Do not have epitaxial loayer 14 to can be made into transistor 10 yet, for example come to this special the making in the transistorized technology of CMOS.N type trap 16 extends in the p type doped substrate 12 or in the p type trap of n type substrate at that time.
Fig. 1 has also shown some metallic contacts, that is:
Left side body contact 72 passes to body bonding pad 26,
Left side source contact 74 leads to source region 22,
Left side gate contact 76 leads to gate region 36,
Drain contact 78, conduction is connected to drain region 40,
Right side gate contact 80 is connected to gate region 38,
Right side source contact 82 is connected to source region 24, and
Right side body contact 84 is connected to bonding pad 28.
As shown in Figure 1, left side body contact 72 and 74 each other in an electrically conductive linking to each other of left side source contact.In addition, right side source contact 82 and 84 each other in an electrically conductive linking to each other of right side body contact.Usually left side source contact 74 also is that conduction is connected to right side source contact 82.Same left side gate contact 76 links to each other with right side gate contact 80 is also each other in an electrically conductive.In another exemplary embodiments, two gate contacts drive separately from each other, therefore do not link to each other.This is suitable for too to two source contacts.
Drain region 40 is passed groove 34 and is ended in the n type trap 16, thereby in transistor 10 runnings, 40 lower bottom part forms a drift path from the drain region along the direction of left side channel region 86, and 40 lower bottom part forms another drift path from the drain region along the direction of right side channel region 88 simultaneously.The formation of channel region is respectively by the voltage control on grid region 76 and 80.
In another exemplary embodiments, if prevent the transistorized generation of parasitic npn with other measure, then not conduction connection between body contact 72,84 and source contact 74,82.The dielectric strength of required transistor 10 is depended in the doping of n type trap 16.
Fig. 2 is a DMOS field-effect transistor 110, except the difference that the following describes, its structure and production and field-effect transistor 10 are similar, therefore those elements that top Fig. 1 has been illustrated no longer explain, these elements have identical reference symbol in Fig. 2, but add individual 1 in front.Therefore, the n type trap 116 of transistor 110 is equivalent to the n type trap 16 of transistor 10.
Under the situation of transistor 110, groove 134 extends buried horizon 170.Under exemplary embodiments situation shown in Figure 2, groove 134 is dark insulated trenchs, and its degree of depth for example has the degree of depth of 1.2 μ m greater than 1 μ m.In contrast, in another exemplary embodiments, groove 134 is shallow insulated trenchs.
Grid region 136 and 138 only extends the top of groove 134, for example the degree of depth of extending 0.5 μ m from n type epitaxial loayer 114 surfaces.Below grid region 136 as far as the zone of channel bottom by the filling insulating material of insulating regions 142, this insulating material is also further isolated grid region 136 and drain region 140.As far as the same filling insulating material by insulating regions 144 in the zone of channel bottom, this insulating material is also further isolated grid region 138 and drain region 140 below grid region 138.This drain region 140 is passed the channel bottom of groove 134 and is ended in the buried horizon 170.
Under the situation of transistor 110 shown in Figure 2, because the depth ratio groove 34 of groove 134 big (though it is not in the part below the channel bottom), the drift path in n type trap 116 has extended, so drain-source voltage can be higher.
Under by the situation that Fig. 2 did to change, drift current also flows along straight line path, thereby can not form peak field in the bending place, then is still this situation by the change that Fig. 1 did, and can see the inflection point of groove 34 lower channel edges.
In also having a kind of exemplary embodiments, transistor 110 does not have epitaxial loayer, thereby n type trap 116 extends in the substrate 112.In the another kind of exemplary embodiments, there is not buried horizon 170 with or without epitaxial loayer 114.
Fig. 3 is a DMOS field-effect transistor 210, except the difference of speaking of below, its structure and generation and field-effect transistor 10 are similar, and therefore those elements that top Fig. 1 has been illustrated no longer explain, these elements have identical reference symbol in Fig. 3, but add individual 2 in front.Therefore, the n type trap 216 of transistor 210 is equivalent to the n type trap 16 of transistor 10.
Different with transistor 10, there is not following element for the situation of transistor 210:
Epitaxial loayer 14, thus n type trap 216 be in the substrate 212,
Buried horizon 54 and 56, and the bonding pad that connects these layers.
The center groove 234 of transistor 210 has shallow trench region 300 in the middle of and two to be in outer deep trench districts 302 and 304 below grid region 236 and 238.Deep trench district 242 and 244 is bottoms electric insulation and that admit insulating regions 242 and 244.Deep trench district 242 and 244 extends the degree of depth of 6 μ m for example even 20 μ m.Leak bonding pad 240 and be in the groove 234 shallow trenchs part, and end at more depths, n type trap 216 internal ratio shallow trench zones 300, for example dark 100nm or 200nm above (as 500nm).Because deep trench zone 302 and 304 is arranged, drift path 306 and 308 length are approximately than long one times of the degree of depth in deep trench zone.When the degree of depth in deep trench zone was 5 μ m, drift path 306 and 308 length will be for example respectively greater than 10 μ m.Not needing to increase chip just can obtain these journeys by raft down the Yangtze River at the area of horizontal direction and move the path.
Transistor 210 also can have a severe doping buried insulation layer.But in another exemplary embodiments, it is so far away that deep trench zone 302 and 304 does not reach insulating barrier.But also can adopt epitaxial loayer.
Fig. 4 is some annular DMOS transistors 400 to 410, and their structure all resembles the transistor 10 in first exemplary embodiments.In other exemplary embodiments, the structure of transistor 400 to 410 is all similar with transistor 110 or transistor 210.Transistor 400 to 410 is in parallel, thus if 400 to 410 parallel connections of 50 or 100 transistors, but then switch up to the electric current of 3A (ampere).So big electric current needs in control circuits such as driving hard disc of computer.For device as shown in Figure 4, required area is very little.
Fig. 5 is a kind of bar shaped DMOS transistor 420, the transistor 10 in its structure image first exemplary embodiments, but two row drain contacts 478,479 are arranged on drain region 440.Can freely select the length L of transistor 420 according to the electric current of wanting switch.In addition, also can many bar shaped transistors 420 are in parallel mutually.Bar shaped transistor 420 is particularly suitable for the occasion that the metallization of drain contact 478,479 only allows limited electric current to flow through.
In other exemplary embodiments, some modification as shown in Figure 4 are being equipped with some hexagons (promptly cellular) transistor.
The following describes the production stage of making transistor 10.At this moment carry out following method step successively:
On the epitaxial loayer 14 that grows on the substrate 12, produce n type trap 16,
Also use hard mask by means of photoetching technique, etching groove 34 and installation groove 46 to 52, and then with silica-filled.Adopting CMP (chemico-mechanical polishing) technology then is common STI technologies such as (shallow trench isolations), with the silicon dioxide planarization.
Make grid region 36 and 38 and zone such as drain region 40 by the photoetching technique of another layer.Then, at these regional etching silicon dioxides, make on its silicon that stops at n type trap 16.
Produce thin dielectric by means of thermal oxidation etc. at the bottom section of trench wall zone and not topped groove 34.
Select the otch in drain region 78 by another photoetching technique.Then, for example utilize reactive ion etching or wet-chemical chamber to remove the thin dielectric layer of 78 kerf bottom once more in the drain region.
In next procedure, polysilicon is deposited in the otch in grid region 36,38 and drain region 40.Polysilicon mixes on the spot or utilizes follow-up diffusion or injection to mix.
Make the polysilicon planarization that severe n type mixes by methods such as CMP.Suitable, also can utilize photoetching polysilicon to be moved to the outside of groove 34.
Utilize photoetching to determine the position in this tagma 18,20.Then mainly by means of diffusion or inject P type mix (or be that n type mix for P raceway groove DMOS) is made in this tagma.After this or can also produce the n type trap of complementary field-effect transist before this.
Define bonding pad 30,32 by photoetching process, and utilize diffusion or injection etc. to carry out slight n type and mix.
Define source region 22,24 by another photoetching process, then for example utilize diffusion or injection etc. to carry out severe n type and mix.And
Define the bonding pad 26,28 in this tagma 18,20 by photoetching process, and then carry out severe P type and mix.
Epitaxial loayer 14, buried horizon 70, and as the words that are fit to also have some buried horizons, produce before the above steps carrying out, particularly when carrying out the BiCMOS method, that is to say when producing bipolar transistor and two kinds of transistors of field-effect transistor in this way.
The method of producing transistor 110 adopts identical step substantially.But, at first be that the otch with the bonding pad only etches into the degree of depth identical with the otch in grid region 136,138, also promptly arrive less than half the degree of depth of the gash depth of groove 134.Produce the thin gate oxide layer then.Have only after this just the otch in drain region 140 to be extended to outside the trench bottom of groove 134, just in time enter buried horizon 170 or just in time enter n type trap 116.
When producing transistor 210, also adopt similar step.But the etching groove of dark insulated trench is to carry out after the etching of shallow insulated trench 248,250 and groove 234 superficial parts.In this process, produce the deep trench zone 302 and 304 of groove 234.In addition, in this step, can produce dark insulated trench in other position of integrated circuit (in the memory cell array as so-called trench capacitor).
In another exemplary embodiments, by same production stage, produce P type DMOS transistor but not n type DMOS transistor, but be to adopt opposite doping.
The drain and gate merging is placed in the insulated trench zone, has reduced the chip area of actual needs.Thereby initial resistivity RON is reduced.In addition, increase than saturation current ISAT.By the degree of depth of change groove or the degree of depth of trench region, can set up the drift path that can be used for big drain voltage easily.
According to above-mentioned each exemplary embodiments, each groove has a slot wedge around it.This slot wedge is a closed line around groove on epitaxial loayer 14 or substrate 14 those surfaces, and the bonding pad, source that is placed in the groove outside also is on this surface.

Claims (10)

1. a field-effect transistor (10), particularly a kind of bilateral diffusion field-effect tranisistor (10) has:
Drift region (16),
Connect the groove (34) of drift region (16), this groove comprises slot wedge, some sidewalls and trench bottom,
The controlled area (36) of field-effect transistor (10), it is positioned in the groove (34),
Two bonding pads (22,40) of field-effect transistor (10),
Form the zone (18) of the inversion channel (86) of field-effect transistor (10), this zone isolates by dielectric and controlled area (36),
Be placed in the bonding pad (22) of groove (34) outside, and be placed in interior another bonding pad (22) of groove (34) or the part of another bonding pad (22).
2. field-effect transistor as claimed in claim 1 (10) is characterized in that: insulating material (142) is positioned between the trench bottom and controlled area (136) under the controlled area (136); The darkest border between controlled area (136) and the insulating material (142) is positioned in the groove the first half that comprises controlled area (136), or comprises on the groove of controlled area (136) in 1/3 part; And the border preferably is parallel to the deep trench bottom.
3. field-effect transistor as claimed in claim 1 or 2 (10) is characterized in that: groove (234) is darker down than the bonding pad (240) that is being placed in the groove (34) down in controlled area (236); Groove (234) cans be compared to dark a times or twice under the bonding pad (240) that is placed in the groove (34) most under controlled area (236); Perhaps below the bonding pad (40) of groove (34) in being placed in groove (34) than dark below controlled area (36).
4. as the described field-effect transistor of above-mentioned each claim, it is characterized in that: this groove does not contain single-crystal semiconductor material, and/or drift region (16) mixes according to first doping type, and preferably the n type mixes; And/or controlled area (36) mixes according to first doping type; And/or bonding pad (22,24) mixes according to first doping type; And/or form inversion channel (86) zone (18) according to a kind of dissimilar doping, preferably the P type mixes; And/or the bonding pad (40) that is placed in the groove (34) mixes heavier than drift region (16); And/or be not placed in bonding pad (22,24) in the groove (34), the zone (18) of drift region (16) and formation inversion channel (86) is positioned in the single-crystal semiconductor material, preferably in the monocrystalline silicon; And/or field-effect transistor (10) is integrated into the integrated circuit (IC) apparatus that comprises a plurality of mutually different elements.
5. as the described field-effect transistor of above-mentioned each claim, it is characterized in that: than drift region (16) more one deck (70) of mixing of severe field-effect transistor (10) and substrate (12) are separated, described substrate (12) is to mix by the doping type different with this severe doped layer.
6. field-effect transistor as claimed in claim 5 (10), it is characterized in that: groove (134) and/or the bonding pad (140) that is placed in the groove (34) just in time extend in the severe doped layer (70), and perhaps groove (34) and/or the bonding pad (40) that is placed in the groove (34) are placed in from severe doped layer (70) a distance.
7. as the described field-effect transistor of above-mentioned each claim (10), it is characterized in that: groove (34) has two groove ends, another preferably is placed in the controlled area (38) in the groove, perhaps groove forms a ring, annular controlled area (36,38) is preferably around the bonding pad (40) that is placed in the groove (34).
8. produce field-effect transistor (10) for one kind, bilateral diffusion field-effect tranisistor (10) particularly, and particularly produce the method as the described field-effect transistor of above-mentioned each claim, comprise following each step, it implements not to be subjected to any restriction of listed order:
Introduce groove (34) in drift region (16) or in the district of arrangement drift region (16), described groove comprises slot wedge, some trench walls and trench bottom,
Fill this groove (34) with insulating material (42,44),
With insulating material (42,44) make figure, the controlled area (36) that is field-effect transistor thus produces otch, and be bonding pad (40) the generation otch of field-effect transistor (10), back a kerf and preceding a kerf are by insulating material (42,44) isolated, this bonding pad is connected with drift region (16)
The material that electric conducting material (36,40) maybe can be transformed into electric conducting material (36,40) is introduced in two otch,
Before or after producing groove (34), form the bonding pad (22) that is placed in groove (34) outside, and the zone (18) that forms the inversion channel district (86) that produces field-effect transistor (10).
9. method as claimed in claim 8 is characterized in that following step:
In at least one regional area (302,304), add deep trench (234), and keep this gash depth, produce trench region with different mutually gash depths at another regional area at least.
10. method as claimed in claim 8 or 9 is characterized in that following step:
Otch one is headed straight for to channel bottom, and insulating material (42,44) is moved at least one trench wall zone of controlled area (36) otch,
Produce thin dielectric layer in the otch of controlled area (36) and in the otch of bonding pad (40),
Before material (36,40) is introduced each otch, the thin dielectric layer in the otch of bonding pad (40) is removed,
Perhaps it is characterized in that following step:
Generation is with a certain distance from the otch of channel bottom, and insulating material (242,244) is moved at least one trench wall zone of otch of controlled area (236),
In the otch of controlled area (236), produce thin dielectric layer,
Deepen the otch of bonding pad (140), be preferably in the generation thin dielectric layer and carry out afterwards.
CN200480016422A 2003-06-12 2004-05-13 Field effect transistor, especially a double diffused field effect transistor, and method for the production thereof Expired - Fee Related CN100583448C (en)

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DE10326523A1 (en) 2005-01-13
EP1631990A2 (en) 2006-03-08
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CN100583448C (en) 2010-01-20

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