JPH06104446A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06104446A
JPH06104446A JP25326692A JP25326692A JPH06104446A JP H06104446 A JPH06104446 A JP H06104446A JP 25326692 A JP25326692 A JP 25326692A JP 25326692 A JP25326692 A JP 25326692A JP H06104446 A JPH06104446 A JP H06104446A
Authority
JP
Japan
Prior art keywords
semiconductor layer
semiconductor
region
layer
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25326692A
Other languages
Japanese (ja)
Inventor
Koji Shirai
浩司 白井
Original Assignee
Toshiba Corp
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP25326692A priority Critical patent/JPH06104446A/en
Publication of JPH06104446A publication Critical patent/JPH06104446A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

PURPOSE:To provide a semiconductor device which has a structure such that the degree of integration can be raised and the area of a source is decreased, according to the development of a fine processing technology. CONSTITUTION:A first group of grooves 152-154, which reach the surface of a substrate 1, are made, along the side faces of isolating regions 21, respectively, and the isolating regions 21 contact with a group of grooves 152, 153, and 155, respecitively, and a takeout region 23 contacts with the groove 153. Furthermore, a second groove 154 is made between the takeout region 23 and a back gate region 39, and the takeout region 23, the back hate region 39, and the source region 45 contact with the groove 154, respectively. A gate electrode 33 is made inside the groove 154, according to the molded part of the back gate region 39, and a channel 63 is made along the side face of the groove 154. According to this constitution, the groove becomes a protective wall against the lateral diffusion of each region, so the increase of the area by the lateral diffusion do not occur. Furthermore, since the channel 63 becomes vertical to the substrate 1, the area of a source region 45 can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention
【0001】[0001]
【産業上の利用分野】この発明は、半導体装置に係わ
り、特に高耐圧型の半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high breakdown voltage type semiconductor device.
【0002】[0002]
【従来の技術】図20は、従来の集積回路用Nチャネル
型高耐圧MOSFET(Double Diffusion MOSFE
T:二重拡散型MOSFET)の断面図である。
2. Description of the Related Art FIG. 20 shows a conventional N-channel high breakdown voltage MOSFET (Double Diffusion MOSFE) for integrated circuits.
(T: Double diffusion type MOSFET).
【0003】P型シリコン基板201表面のうち、選択
された部分の上にはN+ 型埋込層2031 〜2033
形成され、基板201表面上には、N型エピタキシャル
層205が形成されている。エピタキシャル層205内
には、このエピタキシャル層205を複数のN型の島2
071 〜2073 に画定するP+ 型アイソレ−ト領域2
07が形成されている。N型の島2071 〜2073
には、埋込層2031〜2033 それぞれに到達するN+
型ドレイン取り出し領域2111 〜2113が形成され
ている。素子構造は、特に島2072 のみに着目して説
明する。島2072 は素子のドレイン領域として機能す
る。島2072 内には、P型バックゲ−ト層213が形
成されており、このバックゲ−ト層213内にはN+
ソ−ス領域215が形成されている。島2072 上を含
むエピタキシャル層205上には例えばシリコン酸化膜
で成る絶縁膜217が形成されており、特にソ−ス領域
とドレイン領域との間上の絶縁膜はゲ−ト絶縁膜219
として機能する。ゲ−ト絶縁膜219上にはゲ−ト電極
221が形成されている。参照符号223に示される領
域は、P+ 型の電極コンタクト層である。絶縁膜217
内には複数のコンタクト孔が形成されており、これらの
コンタクト孔を介して、ドレイン取り出し領域2111
〜2113 にドレイン配線2251 〜2253 が電気的
に接続され、バックゲ−ト層213およびソ−ス領域2
15にそれぞれ、ソ−ス配線227が電気的に接続され
ている。
On the selected portion of the surface of the P-type silicon substrate 201, N + Type buried layer 203 1-203 3 is formed, on the substrate 201 on the surface, the N-type epitaxial layer 205 is formed. In the epitaxial layer 205, the epitaxial layer 205 is formed into a plurality of N-type islands 2.
P defining 07 1-207 3 + Type isolation region 2
07 are formed. The N-type island 207 1-207 3 of reaching the respective buried layer 203 1 ~203 3 N +
-Type drain extraction region 211 1-211 3 is formed. Device structure will be described focusing only on the particular island 207 2. Island 207 2 serves as a drain region of the device. The island 207 in 2, P-type back gate - coat layer 213 is formed, the back gate - the coat layer in the 213 N + A mold source region 215 is formed. Island 207 on the epitaxial layer 205 including the upper 2 is formed with an insulating film 217 made of silicon oxide film, for example, in particular source - the insulating film on between the source region and the drain region gate - gate insulating film 219
Function as. A gate electrode 221 is formed on the gate insulating film 219. The area indicated by reference numeral 223 is P + Type electrode contact layer. Insulating film 217
A plurality of contact holes are formed in the inside, and the drain extraction region 211 1 is connected through these contact holes.
~211 third drain wiring 225 1-225 3 is electrically connected to, back gate - coat layer 213 and the source - source region 2
A source wiring 227 is electrically connected to each of the terminals 15.
【0004】[0004]
【発明が解決しようとする課題】上記構成のMOSFE
Tにおいて、耐圧を向上させるには、エピタキシャル層
205の膜厚tVGを厚くする。
[Problems to be Solved by the Invention]
At T, in order to improve the breakdown voltage, the thickness t VG of the epitaxial layer 205 is increased.
【0005】しかしながら、膜厚tVGを厚くすると、ア
イソレ−ト領域209、およびコレクタ取り出し領域2
111 〜2113 等を基板201に到達させるのに、長
時間の拡散を行わなければならない。長時間の拡散を行
うと深さ方向のみならず、横方向へも拡散が大きく進行
する。このため、素子面積Sが増加する。素子面積Sの
増加はチップサイズの増加をもたらし、コストアップを
招く。
However, if the film thickness t VG is increased, the isolation region 209 and the collector extraction region 2
11 1-211 3 like for to reach the substrate 201, must be performed for a long time diffusion. When diffusion is carried out for a long time, the diffusion greatly advances not only in the depth direction but also in the lateral direction. Therefore, the element area S increases. An increase in the element area S causes an increase in chip size, which leads to an increase in cost.
【0006】また、二重拡散型MOSFETを形成する
場合、チャネル拡散の拡散距離分、ソ−スの面積が増
え、この拡散距離は、耐圧に対して一意的に決まるた
め、微細化技術をもってしても、ソ−ス面積はある大き
さに収束してゆき、改善できなくなってくる。
Further, when forming a double diffusion type MOSFET, the area of the source is increased by the diffusion distance of the channel diffusion, and this diffusion distance is uniquely determined with respect to the breakdown voltage. However, the source area converges to a certain size and cannot be improved.
【0007】この発明は、上記のような点に鑑み為され
たもので、その目的は、集積度を高めることが可能で、
かつ微細加工技術の発展に応じてソ−ス面積の削減も可
能な構造の素子を持つ半導体装置を提供することにあ
る。
The present invention has been made in view of the above points, and an object thereof is to increase the degree of integration.
Another object of the present invention is to provide a semiconductor device having an element having a structure capable of reducing the source area in accordance with the development of fine processing technology.
【0008】[0008]
【課題を解決するための手段】この発明に係わる半導体
装置は、第1導電型の半導体基板と、この基板の表面の
選択された部分に形成された第2の導電型の第1の半導
体層と、この第1の半導体層を覆って前記基板上に形成
された第2導電型の第2の半導体層と、この第2の半導
体層内に形成され、前記基板に到達して前記第2の半導
体層を第2導電型の島領域に画定する第1導電型の第3
の半導体層と、前記島領域内に形成され、前記第1の半
導体層に到達するとともにこの第1の半導体層の縁に実
質的に沿って設けられる第2導電型の第4の半導体層
と、前記島領域のうち、前記第4の半導体層によって囲
まれる部分にこの第4の半導体層と離間して形成された
第1導電型の第5の半導体層と、この第5の半導体層内
に形成された第2導電型の第6の半導体層と、この第6
の半導体層内に形成され、前記第5の半導体層に通じる
第1導電型の第7の半導体層と、を具備する。そして、
前記第3の半導体層の側面それぞれに沿って前記基板表
面に到達する第1の溝群を形成し、前記第3の半導体層
を第1の溝群にそれぞれ接するようにする。さらに第1
の溝群のうち前記島領域側に形成された溝に前記第4の
半導体層を接するようにする。さらに前記第4の半導体
層と前記第5の半導体層との間に第2の溝を形成し、前
記第4の半導体層、前記第5の半導体層および前記第6
の半導体層をそれぞれこの第2の溝に接するようにす
る。第2の溝内には前記第5の半導体層の形成部に対応
して導電層を形成して、チャネルが第2の溝の側面に沿
って形成することを特徴としている。
A semiconductor device according to the present invention is a semiconductor substrate of a first conductivity type, and a first semiconductor layer of a second conductivity type formed on a selected portion of the surface of the substrate. A second conductive type second semiconductor layer formed on the substrate to cover the first semiconductor layer, and formed in the second semiconductor layer to reach the substrate, Of the first conductivity type defining the second semiconductor layer in the island region of the second conductivity type
A second conductive type fourth semiconductor layer formed in the island region, reaching the first semiconductor layer, and being provided substantially along the edge of the first semiconductor layer. A fifth semiconductor layer of the first conductivity type formed in a portion of the island region surrounded by the fourth semiconductor layer and separated from the fourth semiconductor layer, and in the fifth semiconductor layer. A second conductive type sixth semiconductor layer formed on the
And a seventh semiconductor layer of the first conductivity type which is formed in the semiconductor layer and communicates with the fifth semiconductor layer. And
A first groove group reaching the surface of the substrate is formed along each of the side surfaces of the third semiconductor layer, and the third semiconductor layer is in contact with the first groove group. Furthermore the first
The fourth semiconductor layer is brought into contact with the groove formed on the island region side in the groove group. Further, a second groove is formed between the fourth semiconductor layer and the fifth semiconductor layer, and the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer are formed.
The respective semiconductor layers are in contact with the second groove. A conductive layer is formed in the second groove corresponding to the formation portion of the fifth semiconductor layer, and a channel is formed along the side surface of the second groove.
【0009】[0009]
【作用】上記のような半導体装置によれば、第2の半導
体層内に形成される第3〜第6の半導体層をそれぞれ溝
に接するようにしたので、溝が横方向拡散の防壁として
作用する。このため、第2の半導体層の膜厚を厚くして
も、横方向拡散を考慮しての素子面積の増加をなくせ
る。また、溝によって半導体層間が分離されるため、溝
が空乏層の防壁としても作用するようになり、耐圧を向
上させるために必要な半導体層間の大きい分離距離も取
る必要がなくなる。
According to the semiconductor device as described above, the third to sixth semiconductor layers formed in the second semiconductor layer are in contact with the groove, so that the groove acts as a barrier against lateral diffusion. To do. Therefore, even if the thickness of the second semiconductor layer is increased, it is possible to prevent an increase in the element area in consideration of lateral diffusion. Further, since the semiconductor layers are separated by the groove, the groove also acts as a barrier for the depletion layer, and it is not necessary to provide a large separation distance between the semiconductor layers necessary for improving the breakdown voltage.
【0010】さらに、チャネルが第2の溝の側面に沿っ
て形成されるので、チャネル部を構成する不純物が拡散
する方向が平面方向から深さ方向(垂直方向)に変換さ
れる。このため、拡散により生ずる第6の半導体層の平
面的な面積の制限が無くなり、微細加工技術の進展に伴
って第6の半導体層の面積を縮小させることが可能とな
る。
Further, since the channel is formed along the side surface of the second groove, the diffusion direction of the impurities forming the channel portion is changed from the plane direction to the depth direction (vertical direction). Therefore, there is no limitation on the planar area of the sixth semiconductor layer caused by diffusion, and the area of the sixth semiconductor layer can be reduced with the progress of the fine processing technology.
【0011】[0011]
【実施例】以下、図面を参照してこの発明を一実施例に
より説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.
【0012】図1は、この発明の一実施例に係わる半導
体装置の断面図、図2〜図19はそれぞれ、図1に示す
半導体装置を主要な工程毎に示した断面図である。この
発明の一実施例に係わる半導体装置をその製造方法とと
もに説明する。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 19 are sectional views showing the semiconductor device shown in FIG. A semiconductor device according to an embodiment of the present invention will be described together with its manufacturing method.
【0013】まず、図2に示すように、例えばP型のシ
リコン基板1を温度1000℃でスチ−ム酸化し、基板
1の表面上に1μmの膜厚を有するシリコン酸化膜3を
形成する。次いで、酸化膜3にフォトエッチング法を用
いて埋込層形成パタ−ンに対応した開口部51 〜53
形成する。
First, as shown in FIG. 2, for example, a P-type silicon substrate 1 is steam-oxidized at a temperature of 1000 ° C. to form a silicon oxide film 3 having a thickness of 1 μm on the surface of the substrate 1. Next, openings 5 1 to 5 3 corresponding to the buried layer forming pattern are formed in the oxide film 3 by using a photoetching method.
【0014】次に、図3に示すように、開口部51 〜5
3 を介して基板1内にアンチモン(Sb)を温度100
0℃、1時間の条件で拡散させ、基板1の表面領域内に
+ 型埋込層71 〜73 を形成する。
Next, as shown in FIG. 3, the opening 51~ 5
3The temperature of the antimony (Sb) is 100
Diffuse under the condition of 0 ° C for 1 hour, and
N+ Mold embedding layer 71~ 73To form.
【0015】次に、図4に示すように、酸化膜3を除去
した後、エピタキシャル成長法を用いて基板1上に膜厚
VGが10μm程度のN- 型エピタキシャル層9を形成
する。
Next, as shown in FIG. 4, after the oxide film 3 is removed, an epitaxial growth method is used to form N with a film thickness t VG of about 10 μm on the substrate 1. The type epitaxial layer 9 is formed.
【0016】次に、図5に示すように、エピタキシャル
層9を温度1100℃でスチ−ム酸化し、エピタキシャ
ル層9の表面上に膜厚1.5μmを有するシリコン酸化
膜11を形成する。次いで、酸化膜11にフォトエッチ
ング法を用いて溝形成パタ−ンに対応した開口部131
〜136 を形成する。
Next, as shown in FIG. 5, the epitaxial layer 9 is steam-oxidized at a temperature of 1100 ° C. to form a silicon oxide film 11 having a thickness of 1.5 μm on the surface of the epitaxial layer 9. Next, an opening portion 13 1 corresponding to the groove forming pattern is formed on the oxide film 11 by using a photo etching method.
~ 13 6 are formed.
【0017】次に、図6に示すように、酸化膜11をマ
スクに用いてエピタキシャル層9をエッチングする。こ
の時、反応性イオンエッチング法(RIE)を用いるこ
とにより、エッチング形状は横方向に広がりを持たなく
なる。これにより幅w1が2μm、深さdが10μmの
溝151 〜156 が形成される。この後、酸化膜11を
除去する。
Next, as shown in FIG. 6, the epitaxial layer 9 is etched using the oxide film 11 as a mask. At this time, by using the reactive ion etching method (RIE), the etching shape does not have a lateral spread. As a result, grooves 15 1 to 15 6 having a width w1 of 2 μm and a depth d of 10 μm are formed. After that, the oxide film 11 is removed.
【0018】次に、図7に示すように、エピタキシャル
層9を温度1000℃でスチ−ム酸化し、溝151 〜1
6 の側面および底面を含むエピタキシャル層9の表面
上に膜厚1μmを有するシリコン酸化膜17を形成す
る。酸化膜17が形成された後の溝151 〜156 の隙
間の幅w2は、約1μmとなる。
Next, as shown in FIG. 7, the epitaxial layer 9 is steam-oxidized at a temperature of 1000 ° C. to form the grooves 15 1 to 1 1.
A silicon oxide film 17 having a film thickness of 1 μm is formed on the surface of the epitaxial layer 9 including the side surface and the bottom surface of 5 6 . The width w2 of the gap between the trenches 15 1 to 15 6 after the oxide film 17 is formed is about 1 μm.
【0019】次に、図8に示すように、CVD法を用い
て隙間を含み酸化膜17上にポリシリコンを約0.5μ
m堆積させるような条件で堆積させ、酸化膜17上にポ
リシリコン膜19を形成する。これにより、隙間はポリ
シリコンにより完全に埋め込まれる。
Next, as shown in FIG. 8, about 0.5 μ of polysilicon is deposited on the oxide film 17 including the gap by using the CVD method.
Then, the polysilicon film 19 is formed on the oxide film 17 by depositing under the condition that the m film is deposited. As a result, the gap is completely filled with polysilicon.
【0020】次に、図9に示すように、RIE法を用い
てポリシリコン膜19および酸化膜17を、例えばエピ
タキシャル層9の表面が露出するまで順次除去する。こ
れにより、溝151 〜156 の側面および底面上には酸
化膜17が残り、酸化膜17上には埋込部材としてのポ
リシリコン膜19が残る。結果、溝151 〜156
は、酸化膜17とポリシリコン膜19とによって埋め込
まれる。
Next, as shown in FIG. 9, the polysilicon film 19 and the oxide film 17 are sequentially removed by RIE, for example, until the surface of the epitaxial layer 9 is exposed. Thus, the grooves 15 1 to 15 6 of the sides and on the bottom surface remains oxide film 17, the polysilicon film 19 as embedded members remain on the oxide film 17. Result, grooves 15 1 to 15 6 are filled with the oxide film 17 and the polysilicon film 19.
【0021】次に、図10に示すように、アイソレ−ト
領域形成部に対応した窓を持つ図示せぬフォトレジスト
パタ−ンを図9に示す構造の表面上に形成し、このパタ
−ンをマスクに用いて、P型不純物であるボロン(B)
イオンをエピタキシャル層9内に注入する。次いで、上
記パタ−ンを除去した後、新たにドレイン取り出し領域
形成部に対応した窓を持つ図示せぬフォトレジストパタ
−ンを図9に示す構造の表面上に形成し、このパタ−ン
をマスクに用いて、N型不純物であるリン(P)イオン
をエピタキシャル層9内に注入する。次いで、上記パタ
−ンを除去した後、温度1200℃、5時間、窒素ガス
(N2 )雰囲気中で、ボロン、リンをそれぞれエピタキ
シャル層9内に拡散させる。これにより、P+ 型アイソ
レ−ト領域21、N+ 型ドレイン取り出し領域231
233 がそれぞれ形成される。P+ 型アイソレ−ト領域
21は平面から見ると例えばメッシュ状となっており、
アイソレ−ト領域21によって囲まれた領域はそれぞ
れ、島領域1001 〜1003 となる。
Next, as shown in FIG. 10, a photoresist pattern (not shown) having a window corresponding to the isolation region forming portion is formed on the surface of the structure shown in FIG. 9, and this pattern is formed. Is used as a mask, and boron (B) which is a P-type impurity is used.
Ions are implanted into the epitaxial layer 9. Next, after removing the pattern, a photoresist pattern (not shown) having a window corresponding to the drain extraction region forming portion is newly formed on the surface of the structure shown in FIG. 9, and this pattern is formed. Using it as a mask, phosphorus (P) ions, which are N-type impurities, are implanted into the epitaxial layer 9. Then, after removing the pattern, boron and phosphorus are diffused in the epitaxial layer 9 in a nitrogen gas (N 2 ) atmosphere at a temperature of 1200 ° C. for 5 hours. This gives P + Type isolation region 21, N + Mold drain extraction region 23 1 ~
23 3 are formed respectively. P + The mold isolation region 21 has, for example, a mesh shape when viewed from a plane,
Isolator - Each area surrounded by preparative region 21, the island regions 100 1 to 100 3.
【0022】次に、図11に示すように、ゲ−ト電極を
埋め込み形成するための溝形成部に対応した窓271
273 を持つフォトレジストパタ−ン25を図10に示
す構造の表面上に形成する。
Next, as shown in FIG. 11, the windows 27 1 to 27 1 -corresponding to the groove forming portions for burying the gate electrodes are formed.
27 the photoresist pattern having a 3 - a down 25 is formed on the surface of the structure shown in FIG. 10.
【0023】次に、図12に示すように、パタ−ン25
をマスクに用いて酸化膜17を、後に形成されるMOS
FETのチャネル長を考慮して溝151 、154 および
156 の途中、例えば1μmの深さまでエッチングす
る。これにより、ゲ−ト電極を埋め込み形成するための
溝291 〜293 が形成される。
Next, as shown in FIG. 12, a pattern 25
Is used as a mask to form an oxide film 17 and a MOS to be formed later.
In consideration of the channel length of the FET, the trenches 15 1 , 15 4 and 15 6 are etched to a depth of 1 μm, for example. Thus, gate - groove for the gate electrode buried 29 1-29 3 are formed.
【0024】次に、図13に示すように、エピタキシャ
ル層9の表面を温度1000℃でドライ酸化し、溝29
1 〜293 の側面を含むエピタキシャル層9の表面上に
膜厚500オングストロ−ムを有するシリコン酸化膜
(ゲ−ト酸化膜)31を形成する。
Next, as shown in FIG. 13, the surface of the epitaxial layer 9 is dry-oxidized at a temperature of 1000.degree.
1-29 thickness 500 on the surface of the epitaxial layer 9 including the third aspect angstroms - silicon oxide film having a beam - forming a (gate gate oxide film) 31.
【0025】次に、図14に示すように、CVD法を用
いて溝291 〜293 の隙間を含み酸化膜31上にポリ
シリコンを堆積させ、約5000オングストロ−ムの膜
厚を有する導電性のポリシリコン膜33を形成する。こ
れにより、隙間はポリシリコンにより完全に埋め込まれ
る。
Next, as shown in FIG. 14, the polysilicon is deposited on the oxide film 31 includes a clearance groove 29 1-29 3 by CVD, about 5000 angstroms - conductive having a thickness of arm Forming a conductive polysilicon film 33. As a result, the gap is completely filled with polysilicon.
【0026】次に、図15に示すように、ポリシリコン
膜33をゲ−ト電極パタ−ンにパタ−ニングし、ゲ−ト
電極331 〜333 を得る。次いで、バックゲ−ト形成
部に対応した窓371 〜373 を持つフォトレジストパ
タ−ン35をエピタキシャル層9の上方に形成する。
Next, as shown in FIG. 15, gate polysilicon film 33 - gate electrode pattern - pattern on down - and training, gate - get gate electrode 33 to 333. Then, back gate - to form a down 35 above the epitaxial layer 9 - the photoresist pattern having a window 37 1-37 3 correspond to and forming part.
【0027】次に、図16に示すように、パタ−ン35
をマスクに用いて、P型不純物であるボロンをエピタキ
シャル層9内にイオン注入する。パタ−ン35を除去し
た後、温度1000℃、1時間、窒素ガス雰囲気中でボ
ロンをエピタキシャル層9内に拡散させる。これによ
り、P型バックゲ−ト領域391 〜393 が形成され
る。次いで、ソ−ス領域形成部およびドレインコンタク
ト形成部に対応した窓431 〜433 を持つフォトレジ
ストパタ−ン41をエピタキシャル層9の上方に形成す
る。
Next, as shown in FIG.
Is used as a mask to implant boron, which is a P-type impurity, into the epitaxial layer 9. After removing the pattern 35, boron is diffused into the epitaxial layer 9 in a nitrogen gas atmosphere at a temperature of 1000 ° C. for 1 hour. Thus, P-type back gate - DOO region 39 1-39 3 are formed. Then, source - the photoresist with source region forming unit and the drain contact forming portions window 43 1-43 3 corresponding to the pattern - forming a down 41 above the epitaxial layer 9.
【0028】次に、図17に示すように、パタ−ン41
をマスクに用いて、N型不純物であるヒ素をバックゲ−
ト領域391 〜393 およびドレイン取り出し領域23
1 〜233 内にイオン注入する。パタ−ン41を除去し
た後、温度1000℃、1時間、ドライ雰囲気中で酸化
を行う。これにより、N+ 型ソ−ス領域451 〜4
3 、N+ 型ドレインコンタクト領域471 〜473
得られ、また、ゲ−ト電極331 〜333 の表面上等に
シリコン酸化膜49が得られる。次いで、バックゲ−ト
コンタクト形成部に対応した窓531 〜533 を持つフ
ォトレジストパタ−ン51をエピタキシャル層9の上方
に形成する。
Next, as shown in FIG. 17, a pattern 41 is formed.
Backing the arsenic, which is an N-type impurity, by using
DOO region 39 1-39 3 and the drain extraction region 23
Ions are implanted into 1 to 23 3 . After removing the pattern 41, oxidation is performed in a dry atmosphere at a temperature of 1000 ° C. for 1 hour. This gives N + Type source area 45 1 to 4
5 3 , N + It is obtained -type drain contact region 47 1 to 47 3, also gate - gate electrode 33 to 333 of the surface Choice silicon oxide film 49 is obtained. Then, back gate - to form a down 51 above the epitaxial layer 9 - the photoresist pattern having a window 53 1-53 3 correspond to and contact forming portion.
【0029】次に、図18に示すように、パタ−ン51
をマスクに用いて、P型不純物であるボロンをバックゲ
−ト領域391 〜393 内にイオン注入する。次いで、
CVD法を用いて、酸化シリコンを酸化膜49上に堆積
し、約1μmの膜厚を有するシリコン酸化膜55を酸化
膜49上に形成する。次いで、温度1000℃、30分
間のアニ−ルを行う。この後、温度1000℃、窒素ガ
ス雰囲気中で30分間のアニ−ルを行う。これにより、
+ 型バックゲ−トコンタクト領域571 〜573 等が
形成される。次に、図19に示すように、フォトエッチ
ング法を用いて、各コンタクト領域上の酸化膜55に開
口部を形成し、コンタクト孔591 〜596 を得る。
Next, as shown in FIG.
Using a mask, boron is a P-type impurity back gate - ions are implanted into the preparative area 39 1-39 3. Then
Using the CVD method, silicon oxide is deposited on the oxide film 49, and a silicon oxide film 55 having a film thickness of about 1 μm is formed on the oxide film 49. Then, annealing is performed at a temperature of 1000 ° C. for 30 minutes. After that, annealing is performed at a temperature of 1000 ° C. for 30 minutes in a nitrogen gas atmosphere. This allows
P + Type back gate - DOO contact regions 57 1 to 57 3 and the like are formed. Next, as shown in FIG. 19, by using a photo-etching method, an opening is formed in the oxide film 55 on each contact region to obtain the contact holes 59 1 to 59 6.
【0030】次に、図1に示すように、アルミニウムを
図19に示す構造の表面上に蒸着し、アルミニウム膜を
得る。次いで、このアルミニウム膜をパタ−ニングし
て、コンタクト孔591 〜596 を介して所定領域に電
気的に接続される配線層611〜61 を得る。この
後、配線層611 〜616 に、温度400℃、30分間
のシンタ処理を施して、この発明の一実施例に係わる半
導体装置が完成する。
Next, as shown in FIG. 1, aluminum is vapor-deposited on the surface of the structure shown in FIG. 19 to obtain an aluminum film. Then, the aluminum film pattern - by training, obtaining a wiring layer 61 1 - 61 6 electrically connected to the predetermined region via the contact hole 59 1-59 6. Thereafter, the wiring layers 61 1 to 61 6, the temperature 400 ° C., subjected to annealing treatment for 30 minutes, the semiconductor device is completed according to an embodiment of the present invention.
【0031】上記構成の半導体装置によれば、エピタキ
シャル層9内に形成される各拡散領域、即ち、アイソレ
−ト領域21、ドレイン取り出し領域231 〜233
バックゲ−ト領域391 〜393 、ソ−ス領域451
453 等が、溝151 〜156 によって互いに分離され
るようになるため、これらの溝151 〜156 が、各拡
散領域を構成する不純物の横方向拡散の防壁として機能
する。このため、不純物の横方向拡散による素子面積の
増加が無くなり、充分な耐圧を確保するために、エピタ
キシャル層9の膜厚tVGを厚くしたとしても、素子面積
Sは従来の装置と比較して縮小することができる。
According to the semiconductor device having the above structure, each diffusion region formed in the epitaxial layer 9, that is, the isolation region 21, the drain extraction regions 23 1 to 23 3 ,
Back gate areas 39 1 to 39 3 and source areas 45 1 to
Since 45 3 and the like are separated from each other by the grooves 15 1 to 15 6 , these grooves 15 1 to 15 6 function as a barrier against the lateral diffusion of impurities forming each diffusion region. Therefore, the increase in the element area due to the lateral diffusion of impurities is eliminated, and even if the film thickness t VG of the epitaxial layer 9 is increased in order to secure a sufficient breakdown voltage, the element area S is smaller than that in the conventional device. Can be reduced.
【0032】例えば素子構造の条件として、tVG=10
μm、最小加工寸法=2μm、耐圧確保に必要なP−N
間距離=10μm、二重拡散型MOSETのチャネル拡
散=2μm、トレンチの最小幅=2μmと、仮定した場
合、図20に示す従来装置ではその断面における距離
(S)が116μmとなったが、図1に示す装置ではそ
の断面における距離(S)を20μmまで縮小すること
ができた。
For example, as a condition of the element structure, t VG = 10
μm, minimum processing size = 2 μm, P-N required to secure pressure resistance
Assuming that the inter-distance is 10 μm, the channel diffusion of the double diffusion type MOSET is 2 μm, and the minimum width of the trench is 2 μm, the distance (S) in the cross section of the conventional device shown in FIG. 20 is 116 μm. In the device shown in FIG. 1, the distance (S) in the cross section could be reduced to 20 μm.
【0033】さらに、この発明によれば、チャネル63
が、溝151 、154 および156の側面に沿って形成
されるため、チャネルにおける横方向拡散(チャネル拡
散)を基板の平面方向から基板の深さ方向へと転換する
ことができる。このため、チャネル拡散によって一意的
に決まっていたソ−ス領域451 〜453 の平面的な面
積の制限が無くなり、微細加工技術の進展に伴って更な
る微細化を追及できる構造となる。例えばチャネル長の
制御においては、従来装置では基板の平面方向での制御
であったことが、この発明によれば深さ方向での制御と
なるため、素子の通電能力、耐圧等に合わせてチャネル
長を種々変更したとしても、実質的な素子面積の増加は
無い。
Furthermore, according to the present invention, the channel 63
Are formed along the side surfaces of the grooves 15 1 , 15 4 and 15 6 so that the lateral diffusion in the channel (channel diffusion) can be converted from the plane direction of the substrate to the depth direction of the substrate. Therefore, there is no limitation on the planar area of the source regions 45 1 to 45 3 which is uniquely determined by the channel diffusion, and the structure can be further miniaturized with the progress of the fine processing technology. For example, in controlling the channel length, in the conventional device, the control was performed in the plane direction of the substrate. However, according to the present invention, the control is performed in the depth direction. Even if the length is variously changed, the element area is not substantially increased.
【0034】[0034]
【発明の効果】以上説明したように、この発明によれ
ば、集積度を高めることが可能で、かつ微細加工技術の
発展に応じてソ−ス面積の削減も可能な構造の素子を持
つ半導体装置を提供できる。
As described above, according to the present invention, a semiconductor having an element having a structure capable of increasing the degree of integration and reducing the source area in accordance with the development of fine processing technology. A device can be provided.
【図面の簡単な説明】[Brief description of drawings]
【図1】図1はこの発明の一実施例に係わる半導体装置
の断面図。
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図2】図2はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 2 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図3】図3はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 3 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図4】図4はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 4 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図5】図5はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 5 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図6】図6はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 6 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図7】図7はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 7 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図8】図8はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 8 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図9】図9はこの発明の一実施例に係わる半導体装置
の主要な製造工程を示す断面図。
FIG. 9 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図10】図10はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 10 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図11】図11はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 11 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図12】図12はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 12 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図13】図13はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 13 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図14】図14はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 14 is a cross-sectional view showing main manufacturing steps of a semiconductor device according to an embodiment of the present invention.
【図15】図15はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 15 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図16】図16はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 16 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図17】図17はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 17 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図18】図18はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 18 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図19】図19はこの発明の一実施例に係わる半導体
装置の主要な製造工程を示す断面図。
FIG. 19 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.
【図20】図20は従来の半導体装置の断面図。FIG. 20 is a cross-sectional view of a conventional semiconductor device.
【符号の説明】[Explanation of symbols]
1…P型シリコン基板、71 〜73 …N+ 型埋込層、9
…N- 型エピタキシャル層、151 〜156 …溝、17
…シリコン酸化膜、19…ポリシリコン膜、21…P+
型アイソレ−ト領域、231 〜233 …N+ 型ドレイン
取り出し領域、291 〜293 …溝、31…シリコン酸
化膜(ゲ−ト酸化膜)、331 〜333…ゲ−ト電極、
391 〜393 …P型バックゲ−ト領域、451 〜45
3 …ソ−ス領域、471 〜473 …N+ 型ドレインコン
タクト領域、49…シリコン酸化膜、571 〜573
+ 型バックゲ−トコンタクト領域、611 〜616
配線層、63…チャネル、1001 〜1003 …N型島
領域。
1 ... P-type silicon substrate, 7 1 ~7 3 ... N + Mold embedding layer, 9
... N - Type epitaxial layer, 15 1 to 15 6 ... Groove, 17
… Silicon oxide film, 19… Polysilicon film, 21… P +
Type isolation region, 23 1 to 23 3 ... N + Type drain take-out region, 29 1 to 29 3 ... Groove, 31 ... Silicon oxide film (gate oxide film), 33 1 to 33 3 ... Gate electrode,
39 1 ~39 3 ... P-type back gate - DOO region 45 1-45
3 ... Source region, 47 1 to 47 3 ... N + -Type drain contact region, 49 ... silicon oxide film, 57 1-57 3 ...
P + Back gate contact region, 61 1 to 61 6 ...
Wiring layer, 63 ... channel, 100 1 to 100 3 ... N-type island region.

Claims (3)

    【特許請求の範囲】[Claims]
  1. 【請求項1】 第1導電型の半導体基板と、 前記基板の表面の選択された部分に形成された第2の導
    電型の第1の半導体層と、 前記第1の半導体層を覆って前記基板上に形成された第
    2導電型の第2の半導体層と、 前記第2の半導体層内に形成され、前記基板に到達して
    前記第2の半導体層を第2導電型の島領域に画定する第
    1導電型の第3の半導体層と、 前記島領域内に形成され、前記第1の半導体層の周縁部
    に実質的に到達する第2導電型の第4の半導体層と、 前記島領域のうち、前記第4の半導体層によって囲まれ
    る部分にこの第4の半導体層と離間して形成された第1
    導電型の第5の半導体層と、 前記第5の半導体層内に形成された第2導電型の第6の
    半導体層と、 前記第6の半導体層内に形成され、前記第5の半導体層
    に通じる第1導電型の第7の半導体層と、を具備し、 前記第3の半導体層の側面にそれぞれ沿って前記基板表
    面に到達する第1の溝群が形成され、前記第3の半導体
    層がこの第1の溝群にそれぞれ接し、第1の溝群のうち
    前記島領域側に形成された溝に前記第4の半導体層が接
    し、前記第4の半導体層と前記第5の半導体層との間に
    第2の溝が形成され、前記第4の半導体層、前記第5の
    半導体層および前記第6の半導体層がそれぞれこの第2
    の溝に接し、この第2の溝内に前記第5の半導体層の形
    成部に対応して導電層が形成され、チャネルがこの第2
    の溝の側面に沿って形成されることを特徴とする半導体
    装置。
    1. A semiconductor substrate of a first conductivity type, a first semiconductor layer of a second conductivity type formed on a selected portion of the surface of the substrate, and a substrate covering the first semiconductor layer. A second conductive type second semiconductor layer formed on a substrate; and a second conductive type island region formed in the second semiconductor layer and reaching the substrate. Defining a third semiconductor layer of a first conductivity type; a fourth semiconductor layer of a second conductivity type formed in the island region and substantially reaching a peripheral portion of the first semiconductor layer; In the island region, the first semiconductor layer is formed in a portion surrounded by the fourth semiconductor layer and spaced apart from the fourth semiconductor layer.
    A conductive type fifth semiconductor layer, a second conductive type sixth semiconductor layer formed in the fifth semiconductor layer, and a fifth semiconductor layer formed in the sixth semiconductor layer A seventh semiconductor layer of a first conductivity type communicating with the third semiconductor layer, and a first groove group reaching the surface of the substrate along each side surface of the third semiconductor layer is formed, and the third semiconductor layer is formed. A layer is in contact with each of the first groove groups, and the fourth semiconductor layer is in contact with a groove formed on the island region side of the first groove group, and the fourth semiconductor layer and the fifth semiconductor layer are in contact with each other. A second groove is formed between the second semiconductor layer and the second semiconductor layer, and the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer are respectively formed in the second groove.
    Of the second semiconductor layer, a conductive layer is formed in the second groove corresponding to the formation portion of the fifth semiconductor layer, and a channel is formed in the second groove.
    A semiconductor device, which is formed along the side surface of the groove.
  2. 【請求項2】 前記第1の半導体層は埋込層であり、前
    記第2の半導体層はエピタキシャル層であり、前記第3
    の半導体層はアイソレ−ト領域であり、前記第4の半導
    体層はドレイン取り出し領域であり、前記第5の半導体
    層はナックゲ−ト層であり、前記第6の半導体層はソ−
    ス領域であり、前記第7の半導体層は電極コンタクト領
    域であり、前記導電層はゲ−ト電極であることを特徴と
    する請求項1に記載の半導体装置。
    2. The first semiconductor layer is a buried layer, the second semiconductor layer is an epitaxial layer, and the third semiconductor layer is an epitaxial layer.
    Semiconductor layer is an isolation region, the fourth semiconductor layer is a drain extraction region, the fifth semiconductor layer is a nuck gate layer, and the sixth semiconductor layer is a source region.
    2. The semiconductor device according to claim 1, wherein the semiconductor layer is a gate region, the seventh semiconductor layer is an electrode contact region, and the conductive layer is a gate electrode.
  3. 【請求項3】 前記第3の半導体層により画定される前
    記島領域が複数設けられ、前記第1、第2、第4、第
    5、第6および第7の半導体層で成る素子が同一基板上
    に複数集積されていることを特徴とする請求項1もしく
    は2いずれかに記載の半導体装置。
    3. A substrate in which a plurality of the island regions defined by the third semiconductor layer are provided and the elements composed of the first, second, fourth, fifth, sixth and seventh semiconductor layers are the same substrate. The semiconductor device according to claim 1 or 2, wherein a plurality of semiconductor devices are integrated on the semiconductor device.
JP25326692A 1992-09-22 1992-09-22 Semiconductor device Pending JPH06104446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25326692A JPH06104446A (en) 1992-09-22 1992-09-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25326692A JPH06104446A (en) 1992-09-22 1992-09-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06104446A true JPH06104446A (en) 1994-04-15

Family

ID=17248893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25326692A Pending JPH06104446A (en) 1992-09-22 1992-09-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06104446A (en)

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