JPH06104446A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which has a structure such that the degree of integration can be raised and the area of a source is decreased, according to the development of a fine processing technology. CONSTITUTION:A first group of grooves 152-154, which reach the surface of a substrate 1, are made, along the side faces of isolating regions 21, respectively, and the isolating regions 21 contact with a group of grooves 152, 153, and 155, respecitively, and a takeout region 23 contacts with the groove 153. Furthermore, a second groove 154 is made between the takeout region 23 and a back gate region 39, and the takeout region 23, the back hate region 39, and the source region 45 contact with the groove 154, respectively. A gate electrode 33 is made inside the groove 154, according to the molded part of the back gate region 39, and a channel 63 is made along the side face of the groove 154. According to this constitution, the groove becomes a protective wall against the lateral diffusion of each region, so the increase of the area by the lateral diffusion do not occur. Furthermore, since the channel 63 becomes vertical to the substrate 1, the area of a source region 45 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high breakdown voltage type semiconductor device.

[0002]

2. Description of the Related Art FIG. 20 shows a conventional N-channel high breakdown voltage MOSFET (Double Diffusion MOSFE) for integrated circuits.
(T: Double diffusion type MOSFET).

On the selected portion of the surface of the P-type silicon substrate 201, N ⁺ Type buried layer 203 _{1-203 3} is formed, on the substrate 201 on the surface, the N-type epitaxial layer 205 is formed. In the epitaxial layer 205, the epitaxial layer 205 is formed into a plurality of N-type islands 2.
P defining 07 _{1-207 3} ⁺ Type isolation region 2
07 are formed. The N-type island 207 _{1-207 3} of reaching the respective buried layer 203 ₁ ~203 ₃ N ⁺
-Type drain extraction region 211 _{1-211 3} is formed. Device structure will be described focusing only on the particular island 207 _2. Island 207 ₂ serves as a drain region of the device. The island 207 in _2, P-type back gate - coat layer 213 is formed, the back gate - the coat layer in the 213 N ⁺ A mold source region 215 is formed. Island 207 on the epitaxial layer 205 including the upper ₂ is formed with an insulating film 217 made of silicon oxide film, for example, in particular source - the insulating film on between the source region and the drain region gate - gate insulating film 219
Function as. A gate electrode 221 is formed on the gate insulating film 219. The area indicated by reference numeral 223 is P ⁺ Type electrode contact layer. Insulating film 217
A plurality of contact holes are formed in the inside, and the drain extraction region 211 ₁ is connected through these contact holes.
～211 _third drain wiring 225 _{1-225 3} is electrically connected to, back gate - coat layer 213 and the source - source region 2
A source wiring 227 is electrically connected to each of the terminals 15.

[0004]

[Problems to be Solved by the Invention]
At T, in order to improve the breakdown voltage, the thickness t _VG of the epitaxial layer 205 is increased.

However, if the film thickness t _VG is increased, the isolation region 209 and the collector extraction region 2
11 _{1-211 3} like for to reach the substrate 201, must be performed for a long time diffusion. When diffusion is carried out for a long time, the diffusion greatly advances not only in the depth direction but also in the lateral direction. Therefore, the element area S increases. An increase in the element area S causes an increase in chip size, which leads to an increase in cost.

Further, when forming a double diffusion type MOSFET, the area of the source is increased by the diffusion distance of the channel diffusion, and this diffusion distance is uniquely determined with respect to the breakdown voltage. However, the source area converges to a certain size and cannot be improved.

The present invention has been made in view of the above points, and an object thereof is to increase the degree of integration.
Another object of the present invention is to provide a semiconductor device having an element having a structure capable of reducing the source area in accordance with the development of fine processing technology.

[0008]

A semiconductor device according to the present invention is a semiconductor substrate of a first conductivity type, and a first semiconductor layer of a second conductivity type formed on a selected portion of the surface of the substrate. A second conductive type second semiconductor layer formed on the substrate to cover the first semiconductor layer, and formed in the second semiconductor layer to reach the substrate, Of the first conductivity type defining the second semiconductor layer in the island region of the second conductivity type
A second conductive type fourth semiconductor layer formed in the island region, reaching the first semiconductor layer, and being provided substantially along the edge of the first semiconductor layer. A fifth semiconductor layer of the first conductivity type formed in a portion of the island region surrounded by the fourth semiconductor layer and separated from the fourth semiconductor layer, and in the fifth semiconductor layer. A second conductive type sixth semiconductor layer formed on the
And a seventh semiconductor layer of the first conductivity type which is formed in the semiconductor layer and communicates with the fifth semiconductor layer. And
A first groove group reaching the surface of the substrate is formed along each of the side surfaces of the third semiconductor layer, and the third semiconductor layer is in contact with the first groove group. Furthermore the first
The fourth semiconductor layer is brought into contact with the groove formed on the island region side in the groove group. Further, a second groove is formed between the fourth semiconductor layer and the fifth semiconductor layer, and the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer are formed.
The respective semiconductor layers are in contact with the second groove. A conductive layer is formed in the second groove corresponding to the formation portion of the fifth semiconductor layer, and a channel is formed along the side surface of the second groove.

[0009]

According to the semiconductor device as described above, the third to sixth semiconductor layers formed in the second semiconductor layer are in contact with the groove, so that the groove acts as a barrier against lateral diffusion. To do. Therefore, even if the thickness of the second semiconductor layer is increased, it is possible to prevent an increase in the element area in consideration of lateral diffusion. Further, since the semiconductor layers are separated by the groove, the groove also acts as a barrier for the depletion layer, and it is not necessary to provide a large separation distance between the semiconductor layers necessary for improving the breakdown voltage.

Further, since the channel is formed along the side surface of the second groove, the diffusion direction of the impurities forming the channel portion is changed from the plane direction to the depth direction (vertical direction). Therefore, there is no limitation on the planar area of the sixth semiconductor layer caused by diffusion, and the area of the sixth semiconductor layer can be reduced with the progress of the fine processing technology.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIGS. 2 to 19 are sectional views showing the semiconductor device shown in FIG. A semiconductor device according to an embodiment of the present invention will be described together with its manufacturing method.

First, as shown in FIG. 2, for example, a P-type silicon substrate 1 is steam-oxidized at a temperature of 1000 ° C. to form a silicon oxide film 3 having a thickness of 1 μm on the surface of the substrate 1. Next, openings 5 _{1 to} 5 ₃ corresponding to the buried layer forming pattern are formed in the oxide film 3 by using a photoetching method.

Next, as shown in FIG. 3, the opening 5₁~ 5
₃The temperature of the antimony (Sb) is 100
Diffuse under the condition of 0 ° C for 1 hour, and
N⁺ Mold embedding layer 7₁~ 7₃To form.

Next, as shown in FIG. 4, after the oxide film 3 is removed, an epitaxial growth method is used to form N ⁻ with a film thickness t _VG of about 10 μm on the substrate 1. The type epitaxial layer 9 is formed.

Next, as shown in FIG. 5, the epitaxial layer 9 is steam-oxidized at a temperature of 1100 ° C. to form a silicon oxide film 11 having a thickness of 1.5 μm on the surface of the epitaxial layer 9. Next, an opening portion 13 ₁ corresponding to the groove forming pattern is formed on the oxide film 11 by using a photo etching method.
~ 13 ₆ are formed.

Next, as shown in FIG. 6, the epitaxial layer 9 is etched using the oxide film 11 as a mask. At this time, by using the reactive ion etching method (RIE), the etching shape does not have a lateral spread. As a result, grooves 15 ₁ to 15 ₆ having a width w1 of 2 μm and a depth d of 10 μm are formed. After that, the oxide film 11 is removed.

Next, as shown in FIG. 7, the epitaxial layer 9 is steam-oxidized at a temperature of 1000 ° C. to form the grooves 15 ₁ to ₁ 1.
A silicon oxide film 17 having a film thickness of 1 μm is formed on the surface of the epitaxial layer 9 including the side surface and the bottom surface of 5 ₆ . The width w2 of the gap between the trenches 15 ₁ to 15 ₆ after the oxide film 17 is formed is about 1 μm.

Next, as shown in FIG. 8, about 0.5 μ of polysilicon is deposited on the oxide film 17 including the gap by using the CVD method.
Then, the polysilicon film 19 is formed on the oxide film 17 by depositing under the condition that the m film is deposited. As a result, the gap is completely filled with polysilicon.

Next, as shown in FIG. 9, the polysilicon film 19 and the oxide film 17 are sequentially removed by RIE, for example, until the surface of the epitaxial layer 9 is exposed. Thus, the grooves 15 ₁ to 15 ₆ of the sides and on the bottom surface remains oxide film 17, the polysilicon film 19 as embedded members remain on the oxide film 17. Result, grooves 15 ₁ to 15 ₆ are filled with the oxide film 17 and the polysilicon film 19.

Next, as shown in FIG. 10, a photoresist pattern (not shown) having a window corresponding to the isolation region forming portion is formed on the surface of the structure shown in FIG. 9, and this pattern is formed. Is used as a mask, and boron (B) which is a P-type impurity is used.
Ions are implanted into the epitaxial layer 9. Next, after removing the pattern, a photoresist pattern (not shown) having a window corresponding to the drain extraction region forming portion is newly formed on the surface of the structure shown in FIG. 9, and this pattern is formed. Using it as a mask, phosphorus (P) ions, which are N-type impurities, are implanted into the epitaxial layer 9. Then, after removing the pattern, boron and phosphorus are diffused in the epitaxial layer 9 in a nitrogen gas (N ₂ ) atmosphere at a temperature of 1200 ° C. for 5 hours. This gives P ⁺ Type isolation region 21, N ⁺ Mold drain extraction region 23 ₁ ~
23 ₃ are formed respectively. P ⁺ The mold isolation region 21 has, for example, a mesh shape when viewed from a plane,
Isolator - Each area surrounded by preparative region 21, the island regions 100 ₁ to 100 _3.

Next, as shown in FIG. 11, the windows 27 ₁ to 27 ₁ -corresponding to the groove forming portions for burying the gate electrodes are formed.
27 the photoresist pattern having a ₃ - a down 25 is formed on the surface of the structure shown in FIG. 10.

Next, as shown in FIG. 12, a pattern 25
Is used as a mask to form an oxide film 17 and a MOS to be formed later.
In consideration of the channel length of the FET, the trenches 15 ₁ , 15 ₄ and 15 ₆ are etched to a depth of 1 μm, for example. Thus, gate - groove for the gate electrode buried 29 _{1-29 3} are formed.

Next, as shown in FIG. 13, the surface of the epitaxial layer 9 is dry-oxidized at a temperature of 1000.degree.
_1-29 thickness 500 on the surface of the epitaxial layer 9 including the _third aspect angstroms - silicon oxide film having a beam - forming a (gate gate oxide film) 31.

Next, as shown in FIG. 14, the polysilicon is deposited on the oxide film 31 includes a clearance groove 29 _{1-29 3} by CVD, about 5000 angstroms - conductive having a thickness of arm Forming a conductive polysilicon film 33. As a result, the gap is completely filled with polysilicon.

Next, as shown in FIG. 15, gate polysilicon film 33 - gate electrode pattern - pattern on down - and training, gate - get gate electrode 33 _to 333. Then, back gate - to form a down 35 above the epitaxial layer 9 - the photoresist pattern having a window 37 _{1-37 3} correspond to and forming part.

Next, as shown in FIG.
Is used as a mask to implant boron, which is a P-type impurity, into the epitaxial layer 9. After removing the pattern 35, boron is diffused into the epitaxial layer 9 in a nitrogen gas atmosphere at a temperature of 1000 ° C. for 1 hour. Thus, P-type back gate - DOO region 39 _{1-39 3} are formed. Then, source - the photoresist with source region forming unit and the drain contact forming portions window 43 _{1-43 3} corresponding to the pattern - forming a down 41 above the epitaxial layer 9.

Next, as shown in FIG. 17, a pattern 41 is formed.
Backing the arsenic, which is an N-type impurity, by using
DOO region 39 _{1-39 3} and the drain extraction region 23
Ions are implanted into ₁ to 23 ₃ . After removing the pattern 41, oxidation is performed in a dry atmosphere at a temperature of 1000 ° C. for 1 hour. This gives N ⁺ Type source area 45 ₁ to 4
5 ₃ , N ⁺ It is obtained -type drain contact region 47 ₁ to 47 _3, also gate - gate electrode 33 _to 333 of the surface Choice silicon oxide film 49 is obtained. Then, back gate - to form a down 51 above the epitaxial layer 9 - the photoresist pattern having a window 53 _{1-53 3} correspond to and contact forming portion.

Next, as shown in FIG.
Using a mask, boron is a P-type impurity back gate - ions are implanted into the preparative area 39 _{1-39 3.} Then
Using the CVD method, silicon oxide is deposited on the oxide film 49, and a silicon oxide film 55 having a film thickness of about 1 μm is formed on the oxide film 49. Then, annealing is performed at a temperature of 1000 ° C. for 30 minutes. After that, annealing is performed at a temperature of 1000 ° C. for 30 minutes in a nitrogen gas atmosphere. This allows
P ⁺ Type back gate - DOO contact regions 57 ₁ to 57 ₃ and the like are formed. Next, as shown in FIG. 19, by using a photo-etching method, an opening is formed in the oxide film 55 on each contact region to obtain the contact holes 59 ₁ to 59 _6.

Next, as shown in FIG. 1, aluminum is vapor-deposited on the surface of the structure shown in FIG. 19 to obtain an aluminum film. Then, the aluminum film pattern - by training, obtaining a wiring layer _{61 1 - 61 6} electrically connected to the predetermined region via the contact hole 59 _{1-59 6.} Thereafter, the wiring layers 61 ₁ to 61 _6, the temperature 400 ° C., subjected to annealing treatment for 30 minutes, the semiconductor device is completed according to an embodiment of the present invention.

According to the semiconductor device having the above structure, each diffusion region formed in the epitaxial layer 9, that is, the isolation region 21, the drain extraction regions 23 ₁ to 23 ₃ ,
Back gate areas 39 _{1 to} 39 ₃ and source areas 45 ₁ to
Since 45 _{3 and the} like are separated from each other by the grooves 15 ₁ to 15 ₆ , these grooves 15 ₁ to 15 ₆ function as a barrier against the lateral diffusion of impurities forming each diffusion region. Therefore, the increase in the element area due to the lateral diffusion of impurities is eliminated, and even if the film thickness t _VG of the epitaxial layer 9 is increased in order to secure a sufficient breakdown voltage, the element area S is smaller than that in the conventional device. Can be reduced.

For example, as a condition of the element structure, t _VG = 10
μm, minimum processing size = 2 μm, P-N required to secure pressure resistance
Assuming that the inter-distance is 10 μm, the channel diffusion of the double diffusion type MOSET is 2 μm, and the minimum width of the trench is 2 μm, the distance (S) in the cross section of the conventional device shown in FIG. 20 is 116 μm. In the device shown in FIG. 1, the distance (S) in the cross section could be reduced to 20 μm.

Furthermore, according to the present invention, the channel 63
Are formed along the side surfaces of the grooves 15 ₁ , 15 ₄ and 15 ₆ so that the lateral diffusion in the channel (channel diffusion) can be converted from the plane direction of the substrate to the depth direction of the substrate. Therefore, there is no limitation on the planar area of the source regions 45 _{1 to} 45 ₃ which is uniquely determined by the channel diffusion, and the structure can be further miniaturized with the progress of the fine processing technology. For example, in controlling the channel length, in the conventional device, the control was performed in the plane direction of the substrate. However, according to the present invention, the control is performed in the depth direction. Even if the length is variously changed, the element area is not substantially increased.

[0034]

As described above, according to the present invention, a semiconductor having an element having a structure capable of increasing the degree of integration and reducing the source area in accordance with the development of fine processing technology. A device can be provided.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 4 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 5 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 6 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 7 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 8 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 9 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 10 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 11 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 12 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 13 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 14 is a cross-sectional view showing main manufacturing steps of a semiconductor device according to an embodiment of the present invention.

FIG. 15 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 16 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 17 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 18 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 19 is a sectional view showing a main manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 20 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 ... P-type silicon substrate, 7 ₁ ~7 ₃ ... N ⁺ Mold embedding layer, 9
... N ^- Type epitaxial layer, 15 ₁ to 15 ₆ ... Groove, 17
… Silicon oxide film, 19… Polysilicon film, 21… P ⁺
Type isolation region, 23 ₁ to 23 ₃ ... N ⁺ Type drain take-out region, 29 _{1 to} 29 ₃ ... Groove, 31 ... Silicon oxide film (gate oxide film), 33 _{1 to} 33 ₃ ... Gate electrode,
39 ₁ ~39 ₃ ... P-type back gate - DOO region 45 _1-45
3 ... Source region, 47 _{1 to} 47 ₃ ... N ⁺ -Type drain contact region, 49 ... silicon oxide film, 57 _{1-57 3} ...
P ⁺ Back gate contact region, 61 _{1 to} 61 ₆ ...
Wiring layer, 63 ... channel, 100 ₁ to 100 ₃ ... N-type island region.

Claims (3)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor layer of a second conductivity type formed on a selected portion of the surface of the substrate, and a substrate covering the first semiconductor layer. A second conductive type second semiconductor layer formed on a substrate; and a second conductive type island region formed in the second semiconductor layer and reaching the substrate. Defining a third semiconductor layer of a first conductivity type; a fourth semiconductor layer of a second conductivity type formed in the island region and substantially reaching a peripheral portion of the first semiconductor layer; In the island region, the first semiconductor layer is formed in a portion surrounded by the fourth semiconductor layer and spaced apart from the fourth semiconductor layer.
A conductive type fifth semiconductor layer, a second conductive type sixth semiconductor layer formed in the fifth semiconductor layer, and a fifth semiconductor layer formed in the sixth semiconductor layer A seventh semiconductor layer of a first conductivity type communicating with the third semiconductor layer, and a first groove group reaching the surface of the substrate along each side surface of the third semiconductor layer is formed, and the third semiconductor layer is formed. A layer is in contact with each of the first groove groups, and the fourth semiconductor layer is in contact with a groove formed on the island region side of the first groove group, and the fourth semiconductor layer and the fifth semiconductor layer are in contact with each other. A second groove is formed between the second semiconductor layer and the second semiconductor layer, and the fourth semiconductor layer, the fifth semiconductor layer and the sixth semiconductor layer are respectively formed in the second groove.
Of the second semiconductor layer, a conductive layer is formed in the second groove corresponding to the formation portion of the fifth semiconductor layer, and a channel is formed in the second groove.
A semiconductor device, which is formed along the side surface of the groove. 2. The first semiconductor layer is a buried layer, the second semiconductor layer is an epitaxial layer, and the third semiconductor layer is an epitaxial layer.
Semiconductor layer is an isolation region, the fourth semiconductor layer is a drain extraction region, the fifth semiconductor layer is a nuck gate layer, and the sixth semiconductor layer is a source region.
2. The semiconductor device according to claim 1, wherein the semiconductor layer is a gate region, the seventh semiconductor layer is an electrode contact region, and the conductive layer is a gate electrode. 3. A substrate in which a plurality of the island regions defined by the third semiconductor layer are provided and the elements composed of the first, second, fourth, fifth, sixth and seventh semiconductor layers are the same substrate. The semiconductor device according to claim 1 or 2, wherein a plurality of semiconductor devices are integrated on the semiconductor device.