CN1783471A - Semiconductor packaging and semiconductor module - Google Patents

Semiconductor packaging and semiconductor module Download PDF

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Publication number
CN1783471A
CN1783471A CNA2005101285536A CN200510128553A CN1783471A CN 1783471 A CN1783471 A CN 1783471A CN A2005101285536 A CNA2005101285536 A CN A2005101285536A CN 200510128553 A CN200510128553 A CN 200510128553A CN 1783471 A CN1783471 A CN 1783471A
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mentioned
battery lead
lead plate
semiconductor packages
semiconductor
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CN100418216C (en
Inventor
吉冈心平
池谷之宏
渡边尚威
田多伸光
新留正和
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Die Bonding (AREA)

Abstract

To provide a semiconductor package which can be miniaturized by connecting to a semiconductor element without wire bonding; and also to provide a semiconductor module equipped with the semiconductor package. The package comprises: an IGBT element 20 which has an emitter electrode 22, a gate electrode 23 and an emitter sense electrode on a front surface 21a and has a collector electrode 26 on a rear surface 21b; a first electrode plate 30 which is provided while facing the front surface 21a of the IGBT element 20 and has a protruding part connected to the emitter electrode 22 by solder bonding; a second electrode plate 40 which is provided while facing the rear surface 21b of the IGBT element 20 and has a facing surface 41a connected to the collector electrode 26 by solder bonding; and an insulating substrate 50 which is provided between the first electrode plate 30 and the IGBT element 20 and has a connection pad connected to the gate electrode 23 and the emitter sense electrode by solder bonding.

Description

Semiconductor packages and semiconductor module
Technical field
The present invention relates to semiconductor packages and semiconductor module, particularly have the power semiconductor element, will construct converter (inverter), the semiconductor packages of converter electric control appliances such as (converter) and a plurality of modular semiconductor modules of this semiconductor packages.
Background technology
As the power semiconductor element, use IGBT element (switch element), IEGT, MOS-FET etc. mostly.These power semiconductor elements all possess face side power terminal and control terminal from the teeth outwards, have the rear side power terminal overleaf.In addition, be under the situation of IGBT element at the power semiconductor element, the face side power terminal is the radio utmost point, and the rear side power terminal is a collector electrode, and control terminal is a gate electrode.
When being installed to this power semiconductor element on the substrate and encapsulating, the rear side power terminal of semiconductor element is connected on the electrode of package-side by soldered joint, and the face side power terminal of semiconductor element and control terminal use aluminum steel to be connected to by terminal conjunction method on the electrode of package-side (for example with reference to Japanese Patent Laid document 1 and Patent Document 2).
But there is following technical task in terminal conjunction method: so owing to be that line is engaged engaging time one by one is longer; So line length is elongated in the form of a ring, the wiring inductance change is big owing to line; It is relatively poor to bear vibration ability, and fracture or adjacent 's short circuit etc. takes place easily.
Therefore, has on the face side power terminal that is employed in semiconductor element the method that replaces line and engage aluminium sheet and soldered joint is dull and stereotyped or lead-in wire and the trend of the method for drawing as electrode.Particularly, but select the material of soldered joint to the face side power terminal of semiconductor element, be the technology that receives publicity recently with method dull and stereotyped or that lead-in wire is connected on the face side power terminal by soldered joint.Wherein, from the lead-out wiring of control terminal, use the line that engages by terminal conjunction method.
As shown in figure 19, this semiconductor packages 1 has tabular IGBT element (semiconductor element) 2 and with the 1st battery lead plate 3 and the 2nd battery lead plate 4 of stacked this IGBT element 2 of state clamping.
In the face side of IGBT element 2, be provided with the radio utmost point (power terminal) 2a, gate electrode (control terminal) 2b and penetrate sense electrode (エ ミ Star セ Application ス Electricity Very) (control terminal) 2c.In addition, the rear side at IGBT element 2 is provided with collector electrode (power terminal) 2d.Radio utmost point 2a is connected on the 1st battery lead plate 3 by soldered joint, and collector electrode 2d also is connected on the 2nd battery lead plate 4 by soldered joint.
Near IGBT element 2, be equipped with insulated substrate 5.Insulated substrate 5 uses the connection pads of being located on its back side (not shown), engages with the 2nd battery lead plate 4 by soldered joint.As this soldering, the scolding tin of use the scolding tin thin slice cut into preliminary dimension, sticking with paste, generate by coating process by the scolding tin of print process printing or the scolding tin by the vapour deposition method film forming etc.Wiring of the 2nd battery lead plate 4 double as collector electrode sides and radiator are fixed on the conductive components (not shown) such as metallic cover type ceramic substrate or busbar.In addition, the radio utmost point side wiring of extending from the 1st electrode 3 forms by aluminium strip 8.
Closing line 6b electrical connection by being formed by aluminium between gate electrode 2b and the connection pads 5b is penetrated between sense electrode 2c and the connection pads 5a and is electrically connected by the closing line 6a that is formed by aluminium.And then, on connection pads 5a, welding control wiring 7a, on connection pads 5b, welding control wiring 7b.
[Patent Document 1] Japan Patent spy opens the 2003-110064 communique
[Patent Document 2] Japan Patent spy opens the 2002-164485 communique
In semiconductor packages 1,, the gate electrode 2b of IGBT element 2 and connection pads 5a and the connection pads 5b that penetrates on sense electrode 2c, the insulated substrate 5 need be arranged at grade in order to carry out wire-bonded with said structure.In addition, need guarantee engaging space, guarantee to be used for preventing the spacing distance of short circuit between adjacent closing line 6a, 6b, guarantee to be used for to prevent the spacing distance of short circuit between closing line 6a, 6b and control wiring 7a, the 7b etc.Therefore, the planar dimension of the 2nd battery lead plate 4 increases, and semiconductor packages 1 becomes large-scale.In addition, the wire-bonded operation being retained in the manufacture process of semiconductor packages 1, is being disadvantageous aspect equipment investment and the engineering management.
Summary of the invention
The present invention is with solving above-mentioned problem, the purpose of this invention is to provide a kind of by not using wire-bonded to carry out the connection of semiconductor element and can realize the semiconductor packages of miniaturization and the semiconductor module with this semiconductor packages.
The 1st feature of embodiments of the present invention is in semiconductor packages, to have: tabular semiconductor element, on interarea, have the 1st power terminal and control terminal, with the opposed back side of interarea on have the 2nd power terminal; The 1st battery lead plate with the interarea opposite disposed of semiconductor element, has the 1st electric power electrode that is connected with the 1st power terminal by soldered joint; The 2nd battery lead plate with the back side opposite disposed of semiconductor element, has the 2nd electric power electrode that is connected with the 2nd power terminal by soldered joint; Insulated substrate is located between semiconductor element and the 1st battery lead plate, has the control electrode that is connected with control terminal by soldered joint.
The 2nd feature of embodiments of the present invention is in semiconductor module, to have: the semiconductor packages of above-mentioned the 1st feature; The 1st conductive component and the 2nd conductive component, it has conductivity, clamping semiconductor packages respectively and being provided with.
The invention effect
According to the present invention, thereby can provide a kind of by not using wire-bonded to carry out to realize the semiconductor packages of miniaturization and semiconductor module with this semiconductor packages to the connection of semiconductor element.
Description of drawings
Fig. 1 is the stereogram of the semiconductor packages of expression the 1st execution mode of the present invention.
Fig. 2 is the exploded perspective view of expression semiconductor packages shown in Figure 1.
Fig. 3 is the expression insulated substrate that semiconductor packages had shown in Figure 1 and the exploded perspective view of IGBT element.
Fig. 4 is the expression insulated substrate that semiconductor packages had shown in Figure 1 and the exploded perspective view of the 1st battery lead plate.
Fig. 5 is the expression insulated substrate that semiconductor packages had shown in Figure 1 and the stereogram of the 1st battery lead plate.
Fig. 6 is the A-A line cutaway view of expression semiconductor packages shown in Figure 1.
Fig. 7 is the A-A line cutaway view of the semiconductor packages of expression the 2nd execution mode of the present invention.
Fig. 8 is the 1st an operation cutaway view of the manufacturing process of explanation semiconductor packages shown in Figure 7.
Fig. 9 is the 2nd operation cutaway view.
Figure 10 is the A-A line cutaway view of the semiconductor packages of expression the 3rd execution mode of the present invention.
Figure 11 is the A-A line cutaway view of the semiconductor packages of expression the 4th execution mode of the present invention.
Figure 12 is the A-A line cutaway view of the semiconductor packages of expression the 5th execution mode of the present invention.
Figure 13 is the A-A line cutaway view of the semiconductor packages of expression the 6th execution mode of the present invention.
Figure 14 is the end view of the semiconductor module of expression the 7th execution mode of the present invention.
Figure 15 is the vertical view of expression semiconductor module shown in Figure 14.
Figure 16 is the 1st operation end view of manufacturing process of the semiconductor module of explanation the 8th execution mode of the present invention.
Figure 17 is the 2nd operation end view.
Figure 18 is the end view of the semiconductor module of expression the 9th execution mode of the present invention.
Figure 19 is the stereogram of an example of the semiconductor packages of expression prior art of the present invention.
Embodiment
(the 1st execution mode)
Referring to figs. 1 through Fig. 6 the 1st execution mode of the present invention is described.
As depicted in figs. 1 and 2, semiconductor packages 10 constitutes with lower member by stacked: as the IGBT element (semiconductor element) 20 of power semiconductor element; Be configured in the 1st battery lead plate 30 of surface (interarea) the 21a side of this IGBT element 20; Be configured in the 2nd battery lead plate 40 with the surperficial opposed back side 21b side of IGBT element 20; Be configured in the insulated substrate 50 between the 1st battery lead plate 30 and the IGBT element 20.The outer peripheral edges of IGBT element 20 are located at than each outer peripheral edges of the 1st battery lead plate the 30, the 2nd battery lead plate 40 and insulated substrate 50 in the inner part.
IGBT element 20 is that IGBT is loaded on the so-called semiconductor chip 21 of tabular small pieces as shown in Figures 2 and 3.On the surperficial 21a of semiconductor chip 21, be provided with the radio utmost point (the 1st power terminal) 22, gate electrode (control terminal) 23 and penetrate sense electrode (control terminal) 24.At gate electrode 23 with penetrate around the sense electrode 24, be formed with the soldering-resistance layer 25 that is used for preventing the short circuit that causes because of scolding tin stream by printing.In addition, on the 21b of the back side of semiconductor chip 21, be provided with collector electrode (the 2nd power terminal) 26.In addition, the opening shape of soldering-resistance layer 25 decides according to the kind (shape of the shape of brazed ball or scolding tin thin slice) of soldering tin amount that uses soldered joint and soldering.When brazed ball was used for soldered joint, opening shape was set at for example circular.
The 1st battery lead plate 30 is as Fig. 2 and shown in Figure 4, has by conductive materials such as for example copper materials to form tabular base main body 31.Copper material better is used because of the aspect from price, conductivity, thermal conductivity, but is not limited to this (narrating in the back about other conductive materials in addition).On the opposed faces 31a of the IGBT of base main body 31 element 20 sides, be formed with to IGBT element 20 lateral processes, be used for jut (the 1st electric power electrode) 32 (with reference to Fig. 4) of contacting and be electrically connected with the radio utmost point 22 of IGBT element 20.
The 2nd battery lead plate 40 has by conductive materials such as for example copper materials and forms tabular base main body 41 as shown in Figure 2.The opposed faces of IGBT element 20 sides of this base main body 41 (the 2nd electric power electrode) 41a contacts with the collector electrode 26 of IGBT element 20, and the 2nd battery lead plate 40 is electrically connected with collector electrode 26.In addition, the material of base main body 41 both can for base main body 31 identical materials, also can be different materials.
Insulated substrate 50 is as Fig. 2, Fig. 3 and shown in Figure 4, has by glass epoxy resin or polyimide resin etc. to form tabular base main body 51.On base main body 51, the jut 32 that is provided with the 1st battery lead plate 30 passes, form the flat shape identical with jut 32 and the peristome (pass through openings) 52 of similar shape more greatly.The jut 32 of the 1st battery lead plate 30 is entrenched in the peristome 52.In addition, on base main body 51, be formed with from outstanding laterally lead division (protuberance) 51a (with reference to Fig. 3 and Fig. 4) of each outer peripheral edges of IGBT element the 20, the 1st battery lead plate 30 and the 2nd battery lead plate 40.And then, on the surface of the 2nd battery lead plate 40 sides (IGBT element 20 sides) of base main body 51, be provided with connection pads 51b (with reference to Fig. 4).In addition, on the surface of the 1st battery lead plate 30 sides of base main body 51, be provided with the anchor pad 51c (with reference to Fig. 2 and Fig. 3) that is used for fixing the 1st battery lead plate 30.This anchor pad 51c is positioned in the outer peripheral edges position in the outer part than IGBT element 20.
On base main body 51, as shown in Figure 3 and Figure 4, connection pads (control electrode) 53,54 is respectively with the gate electrode 23 of IGBT element 20 with penetrate sense electrode 24 opposite disposed.And then, on base main body 51, be provided with the wiring 55,56 that is connected with each connection pads 53,54 respectively, be arranged on the lead division 51a with these wiring 55,56 external connection terminals that are connected 57,58 location respectively.
In addition, except the connecting portion of connection pads 53,54 and external connection terminals 57,58, be used to all prevent that the soldering-resistance layer (not shown) of scolding tin stream from covering.The material and the kind of diaphragm have no particular limits.The opening shape of soldering-resistance layer determines according to the soldering tin amount that uses in soldered joint and the kind (shape of brazed ball or the shape of thin slice) of soldering.When brazed ball was used for soldered joint, opening shape was set at for example circular.
Then, these IGBT element the 20, the 1st battery lead plate the 30, the 2nd battery lead plates 40 and insulated substrate 50 mutual electric connection structure and connected structures are described.
As shown in Figure 3 and Figure 4, the radio utmost point 22 of IGBT element 20 and the jut of the 1st battery lead plate 30 32 engage by soldered joint, as shown in Figure 6, are formed with soldering-tin layer 70 between IGBT element 20 and jut 32.Thus, the radio utmost point 22 is electrically connected with the jut 32 of the 1st battery lead plate 30.
In addition, as shown in Figure 3, the gate electrode 23 of IGBT element 20 engages by the soldered joint of being undertaken by brazed ball 60 with connection pads 54 on the insulated substrate 50, is formed with soldering-tin layer between IGBT element 20 and insulated substrate 50.Thus, gate electrode 23 is electrically connected with connection pads 54.Equally, as shown in Figure 3, the sense electrode 24 of penetrating of IGBT element 20 engages by the soldered joint of being undertaken by brazed ball 60 with connection pads 53 on the insulated substrate 50, as shown in Figure 6, is formed with soldering-tin layer 71 between IGBT element 20 and insulated substrate 50.Thus, penetrating sense electrode 24 is electrically connected with connection pads 53.
And then as shown in Figure 2, the collector electrode 26 of IGBT element 20 engages by soldered joint with the opposed faces 41a of the 2nd battery lead plate 40, as shown in Figure 6, is formed with soldering-tin layer 72 between IGBT element 20 and the 2nd battery lead plate 40.Thus, collector electrode 26 is electrically connected with the 2nd battery lead plate 40.
As shown in Figure 5, the 2nd battery lead plate 40 engages by the soldered joint by scolding tin coated ball (liner) 61 with the connection pads 51b of insulated substrate 50.Scolding tin coated ball 61 has the function that keeps certain space between the 2nd battery lead plate 40 and the insulated substrate 50 as making.Scolding tin coated ball 61 is configured on the connection pads 51b, by its melt surface being carried out the soldered joint of the 2nd battery lead plate 40 and insulated substrate 50.In addition, scolding tin coated ball 61 is by following formation: metal material for coating on the core surface of nonmetallic materials such as the surface of metal core or plastics applies scolding tin on the surface of the parts of making like this.
As shown in Figure 2, the 1st battery lead plate 30 engages by soldered joint with the anchor pad 51c of insulated substrate 50, and the 1st battery lead plate 30 is fixed on the insulated substrate 50.In addition, the 1st battery lead plate 30 and the 2nd battery lead plate 40 are by insulated substrate 50 electric insulations.In addition, but anchor pad 51c by and soldering between lubricant nature preferably material form, in order not increase the manufacture process of insulated substrate 50, by in same manufacturing process, making with connection pads 51b identical materials.
Like this, semiconductor packages 10 according to the 1st execution mode, by with the gate electrode 23 of IGBT element 20 and penetrate sense electrode 24, be arranged on the opposed locations, can they be connected by soldered joint, and not need to engage by wire-bonded with each connection pads 53,54 of insulated substrate 50.Thus, do not need to guarantee to be used for carrying out the engaging space of wire-bonded, also do not need to guarantee to be used for to prevent the spacing distance of the short circuit that causes because of closing line, so can realize the miniaturization of semiconductor packages 10.Thereby, can not use wire-bonded and carry out connection IGBT element 20, can make semiconductor packages 10 miniaturizations thus.In addition, owing to do not need to be used for carrying out the patching machine equipment of wire-bonded, can cut down the space of manufacturing equipment investment and production equipment.
And then, insulated substrate 50 has from the outstanding laterally lead division 51a of each outer peripheral edges of IGBT element the 20, the 1st battery lead plate 30 and the 2nd battery lead plate 40, on this lead division 51a, possesses the external connection terminals 57,58 that is connected with connection pads 53,54, so, and the control wiring can be drawn out to outside the encapsulation without wire-bonded.
In addition, the 1st battery lead plate 30 possesses as the 1st electric power electrode and to the jut 32 of IGBT element 20 lateral processes, insulated substrate 50 possesses the peristome 52 that jut 32 passes, so can easily carry out being connected of the radio utmost point 22 of the 1st battery lead plate 30 and IGBT element 20.
In addition, insulated substrate 50 with the 1st battery lead plate 30 opposed surfaces on have anchor pad 51c, the 1st battery lead plate 30 engages by soldered joint with anchor pad 51c, so can be with high strength that insulated substrate 50 and the 1st battery lead plate 30 is fixing.
In addition, each outer peripheral edges of the 2nd battery lead plate 40 and insulated substrate 50 are set in than the outer peripheral edges of IGBT element 20 in the outer part, has for example scolding tin coated ball 61, it is positioned between the 2nd battery lead plate 40 and the insulated substrate 50 than the outer peripheral edges of IGBT element 20 in the outer part, as the spacing distance between the 2nd battery lead plate 40 and the insulated substrate 50 is remained certain liner, thus will remain between the 2nd battery lead plate 40 and the insulated substrate 50 certain, so can prevent the damage of the IGBT element 20 that causes from the impact of outside etc.As a result, can improve the part reliability of semiconductor packages 10.
And then, liner has metal material at least from the teeth outwards, it for example is scolding tin coated ball 61, be bonded on by soldered joint on the one at least of the 2nd battery lead plate 40 and insulated substrate 50, so liner can be bonded on the one at least of the 2nd battery lead plate 40 and insulated substrate 50 by the device that carries out soldered joint, because in do not need to be provided for the new device that liner engages, so can cut down the space of manufacturing equipment investment and production equipment.
In addition, as liner,, can use commercially available ceramic seal or resin-sealed electric passive component making scolding tin coated ball 61 than under the situation of difficult.For example, can utilize chip parts such as resistance, electric capacity or inductance as liner.Chip part is because the parts of equal height are standardized, collected easily to its size, so can carry out the applying of the 2nd battery lead plate 40 and insulated substrate 50 with the higher depth of parallelism.In addition, the chip part of adorning this electric passive component in has the electrode part of soldering coating at both ends.Owing to can use this electrode part to carry out welding, so assembling easily to substrate.At this moment, do not need to be used as the part of circuit of the semiconductor device of present embodiment as the chip part that in the liner electric passive component is housed.
In addition, the present invention is not limited to above-mentioned execution mode.For example, in the above-described embodiment, the material of the 1st battery lead plate 30 and the 2nd battery lead plate 40 is a copper material, but be not limited to this, so long as conductive material just can, from viewpoints such as formability, proportion and coefficient of thermal expansions, also can be aluminium, molybdenum, copper molybdenum alloy and copper-tungsten etc.And then the material of the 1st battery lead plate 30 and the 2nd battery lead plate 40 also can be the clad material (clad) of various materials, but for the lubricant nature that improves soldered joint also can be with other materials with overlay coating.
In addition, be processed to form the jut 32 of the 1st battery lead plate 30 by pressure impression, but be not limited to this, for example using agglomerated material as the material of the 1st battery lead plate 30, when being the material of jut 32, also can form by sintering.
In addition, the soldering tin material that uses in soldered joint also can be various soldering tin materials such as common Sn-Pb SnPb63, Pb-free solder, rich Pb high temperature scolding tin.In addition, as supply between collector electrode 26 and the 2nd battery lead plate 40 and the soldering between the radio utmost point 22 and the 1st battery lead plate 30, can use the scolding tin thin slice that cuts into preliminary dimension, by the scolding tin of print process printing stick with paste, scolding tin by coating or evaporation film-forming etc.And then, as supply to gate electrode 23 and penetrate sense electrode 24 and each connection pads 53,54 between scolding tin, though can use solder ball, by the scolding tin of print process printing stick with paste, by allotting the scolding tin paste supplied with etc., the use of solder ball is the easiest, is preferred.
In addition, as insulated substrate 50, undertaken by soldered joint with the 1st battery lead plate 30 fixedly the time use two panels, and only by bonding or mechanical fixation carry out with the 1st battery lead plate 30 fixedly the time can use single sided board.And then, as insulated substrate 50, can use flexible base, board or flexible substrate etc., especially when requiring thermal endurance, can use BT resin acid imide (BT レ ジ Application. イ ミ De) substrate etc.
In addition, on insulated substrate 50, be provided with the peristome 52 that jut 32 passes, but be not limited to this, for example also the notch that jut 32 passes can be set.
(the 2nd execution mode)
With reference to Fig. 7 to Fig. 9 the 2nd execution mode of the present invention is described.
The 2nd execution mode of the present invention is identical with the 1st execution mode basically, in the 2nd execution mode, the part different with the 1st execution mode is described.In addition, in the 2nd execution mode, the part identical with the part that is illustrated by the 1st execution mode represented with identical label, omits its explanation (other execution modes too).
The difference of the 2nd execution mode and the 1st execution mode is, as shown in Figure 7, the opposed faces of IGBT element 20 sides of the 1st battery lead plate 30 (the 1st electric power electrode) 31a becomes the plane, and the soldered joint of IGBT element 20 and the 1st battery lead plate 30, IGBT element 20 are diffusion bond with the soldered joint of insulated substrate 50 and the soldered joint of IGBT element 20 and the 2nd battery lead plate 40.
Here, diffusion bond is that material is heated to each other smaller or equal to the temperature of fusing point and the joint method that makes it to pressurize and connect airtight, engage with the state of solid phase by the phase counterdiffusion of mutual atom.In addition, because the opposed faces 31a of IGBT element 20 sides of the 1st battery lead plate 30 is the plane, so the 1st battery lead plate 30 does not have the structure of above-mentioned jut 32 shown in Figure 4.
The radio utmost point 22 on the IGBT element 20 is (with reference to the Fig. 2) that engage by the diffusion bond with soldering with the opposed faces 31a of the 1st battery lead plate 30, as shown in Figure 7, is formed with soldering-tin layer 70 between IGBT element 20 and the 2nd battery lead plate 40.Thus, the radio utmost point 22 is electrically connected with the 1st battery lead plate 30.
In addition, the gate electrode 23 on the IGBT element 20 is (with reference to the Fig. 3) that engage by the diffusion bond with soldering with connection pads 54 on the insulated substrate 50, is formed with soldering-tin layer between IGBT element 20 and insulated substrate 50.Thus, gate electrode 23 is electrically connected with connection pads 54.Equally, the sense electrode 24 of penetrating on the IGBT element 20 is (with reference to the Fig. 3) that engage by the diffusion bond with soldering with connection pads 53 on the insulated substrate 50, as shown in Figure 7, is formed with soldering-tin layer 71 between IGBT element 20 and insulated substrate 50.Thus, will penetrate sense electrode 24 is electrically connected with connection pads 53.
And then the collector electrode 26 of IGBT element 20 is (with reference to the Fig. 2) that engage by the diffusion bond with soldering with the opposed faces 41a of the 2nd battery lead plate 40, as shown in Figure 7, is formed with soldering-tin layer 72 between IGBT element 20 and the 2nd battery lead plate 40.Thus, collector electrode 26 is electrically connected with the 2nd battery lead plate 40.
The assembling process of semiconductor packages 10 then, is described.
At first, as shown in Figure 8, scolding tin thin slice 72a is positioned on the 2nd battery lead plate 40, IGBT element 20 is positioned on this scolding tin thin slice 72a.In addition, scolding tin thin slice 72a is formed by the scolding tin of Sn class, on the opposed faces 41a of the 2nd battery lead plate 40 and on the collector electrode 26 (with reference to Fig. 2) of the back side 21b of IGBT element 20, but implements Ni/Au coating with the lubricant nature of scolding tin in order to improve.The 2nd battery lead plate 40 after stacked and IGBT element 20 are arranged in the decompression extruder, in predetermined condition (for example squeeze pressure is that 4MPa, temperature are 210 ℃, reduce pressure smaller or equal to the 10Torr) extruding of reducing pressure.This condition is set according to scolding tin composition of employed scolding tin thin slice 72a etc.In addition, in the 2nd execution mode, for example being set at, squeeze pressure is in the scope smaller or equal to 50Torr in scope, the temperature of 0.5MPa～10MPa 150 ℃～300 ℃ scope, decompression.By the decompression extruding, the opposed faces 41a of the 2nd battery lead plate 40 goes up the Au diffusion on the collector electrode 26 that reaches IGBT element 20, and Ni and Sn diffusion reaction.Thus, the opposed faces 41a of the 2nd battery lead plate 40 engages (with reference to Fig. 2) with the collector electrode 26 of IGBT element 20.
Then, as shown in Figure 9, insulated substrate 50 is positioned on the 1st battery lead plate 30, scolding tin thin slice 70a is embedded in the peristome 52 of insulated substrate 50, and will be positioned on the connection pads 53 (with reference to Fig. 3) of insulated substrate 50 with the unidimensional scutellate scolding tin thin slice 71a of the gate electrode 23 (with reference to Fig. 3) of IGBT element 20, will be positioned on the connection pads 53 (with reference to Fig. 3) of insulated substrate 50 with the unidimensional scutellate scolding tin thin slice 71a of sense electrode 24 (with reference to Fig. 3) that penetrates of IGBT element 20.In addition, scolding tin thin slice 70a is the thin slice thicker than the thickness of insulated substrate 50, and scolding tin thin slice 71a is the thin slice with scolding tin thin slice 70a thickness identical with the difference of the thickness of insulated substrate 50.In addition, scolding tin thin slice 70a, 71a are that the scolding tin by the Sn class forms, on the opposed faces 31a of the 1st battery lead plate 30 and then at the radio utmost point 22, the gate electrode 23 of the surperficial 21a of IGBT element 20 and penetrate on each electrode of sense electrode 24, but implement Ni/Au coating with the lubricant nature of scolding tin in order to improve.
Then,, IGBT element 20 and the 2nd battery lead plate 40 after engaging are positioned on insulated substrate 50, make IGBT element 20 and insulated substrate 50 opposed via scolding tin thin slice 70a and scolding tin thin slice 71a.At this moment, position,, make the gate electrode 23 of scolding tin thin slice 71a and IGBT element 20 and penetrate sense electrode 24 opposed (with reference to Fig. 3) so that the radio utmost point 22 of scolding tin thin slice 70a and IGBT element 20 is opposed.IGBT element after stacked the 20, the 1st battery lead plate the 30, the 2nd battery lead plate 40 and insulated substrate 50 are arranged in the decompression extruder extruding of reducing pressure under the condition identical with above-mentioned condition.By decompression extruding, the opposed faces 31a of the 1st battery lead plate 30 go up and each electrode of IGBT element 20 on the Au diffusion, and Ni and Sn diffusion reaction.Thus, the opposed faces 31a of the 1st battery lead plate 30 engages with the radio utmost point 22 of IGBT element 20, and each connection pads 53,54 of insulated substrate 50 is respectively with the gate electrode 23 of IGBT element 20 and penetrate sense electrode 24 and engage (with reference to Fig. 3).Like this, just finished semiconductor packages 10 as shown in Figure 7.
Like this, semiconductor packages 10 according to the 2nd execution mode, by making each interelectrode soldered joint of connection is diffusion bond, can prevent the fusion of scolding tin, can control the thickness of soldering- tin layer 70,71,72, so can keep the 1st battery lead plate 30 that semiconductor packages 10 had and the depth of parallelism of the 2nd battery lead plate 40, the thickness that can also make semiconductor packages 10 is for certain.As its result, with a plurality of semiconductor packages 10 combinations and modularization the time, also can not produce the interdependent undesirable condition such as in uneven thickness of inhomogeneous and each semiconductor packages 10 of the depth of parallelism of the 1st battery lead plate 30 that had with each semiconductor packages 10 and the 2nd battery lead plate 40, thereby make semiconductor module.
(the 3rd execution mode)
With reference to Figure 10 the 3rd execution mode of the present invention is described.
The 3rd execution mode of the present invention is identical with the 2nd execution mode basically, and parts different with the 2nd execution mode in the 3rd execution mode is illustrated.
The difference of the 3rd execution mode and the 2nd execution mode is, as shown in figure 10, in semiconductor packages 10, has resin portion 80 between the 1st battery lead plate 30 and the 2nd battery lead plate 40, and it surrounds IGBT element 20.
By resin being filled in the space between the 1st battery lead plate 30 and the 2nd battery lead plate 40, with resin portion 80 be located at IGBT element 20 around.Thus, the 1st battery lead plate 30 and the 2nd battery lead plate 40 is affixed, will cover around the IGBT element 20 by resin portion 80.
Like this, semiconductor packages 10 according to the 3rd execution mode, by in the space between the 1st battery lead plate 30 and the 2nd battery lead plate 40 resin portion 80 being set, improved the mechanical strength of semiconductor packages 10, so can prevent damage because of the IGBT element 20 that causes from impact of outside etc.Its result can improve the part reliability of semiconductor packages 10.
(the 4th execution mode)
With reference to Figure 11 the 4th execution mode of the present invention is described.
The 4th execution mode of the present invention is identical with the 1st execution mode basically, and parts different with the 1st execution mode in the 4th execution mode is described.
The difference of the 4th execution mode and the 1st execution mode is, as shown in figure 11, between IGBT element 20 and the 1st battery lead plate 30, possess stress relaxation layer 85, the 2 battery lead plates 40 and possess stress relaxation layer 86 with stress relaxation properties and conductivity with stress relaxation properties and conductivity.
Stress relaxation layer 85 is located on the base main body 31 as the jut 32 on the base main body 31 of the 1st battery lead plate 30, is clamped by jut main body 32a, 32b as the intermediate layer of jut main body 32a, 32b.Jut main body 32a joins on the base main body 31 by soldered joint.Thus, between jut main body 32a and base main body 31, be formed with soldering-tin layer 73.In addition, stress relaxation layer 86 is arranged in the base main body 41 of the 2nd battery lead plate 40 as the intermediate layer.
Stress relaxation layer 85,86 is formed by the conductive material that copper etc. has conductivity.In addition, stress relaxation layer 85,86 forms the section shape of a mesh by wire rod being arranged to mesh-shape, but is not limited to this.This stress relaxation layer 85,86 mildly (flexibly) relaxes stress.
Like this,,, can relax stress, so can prevent the damage of the IGBT element 20 that stress causes by stress relaxation layer 85,86 is set according to the semiconductor packages 10 of the 4th execution mode.Its result can improve the part reliability of semiconductor packages 10.
In addition, in the manufacturing process of semiconductor packages 10, as Fig. 8 and shown in Figure 9, even, also can prevent to cause the damage of IGBT element 20 because of this external force having applied under the situations such as external force.Its result, the reduction of the rate of finished products in the manufacturing in the time of can suppressing to make semiconductor packages 10.
And then, and during modularization with 10 combinations of a plurality of semiconductor packages, also can prevent the damage of the semiconductor packages 10 that in the manufacturing process of this semiconductor module, causes, particularly can prevent the damage of IGBT element 20 because of the external force that imposes on semiconductor packages 10.Its result, the reduction of the rate of finished products in the manufacturing in the time of can suppressing to make semiconductor module.
In addition, because stress relaxation layer 85,86 forms the section mesh-shape, so can mildly relax stress with simple structure.
(the 5th execution mode)
With reference to Figure 12 the 5th execution mode of the present invention is described.
The 5th execution mode of the present invention is identical with the 1st execution mode basically, and parts different with the 1st execution mode in the 5th execution mode is described.
The difference of the 5th execution mode and the 1st execution mode is that as shown in figure 12, the 1st battery lead plate 30 possesses stress relaxation layer 85, the 2 battery lead plates 40 with stress relaxation properties and conductivity and possesses the stress relaxation layer 86 with stress relaxation properties and conductivity.
Stress relaxation layer 85 is arranged in the base main body 31 of the 1st battery lead plate 30 as the intermediate layer, plays the function as the jut on the base main body 31 32.In addition, stress relaxation layer 86 is arranged in the base main body 41 of the 2nd battery lead plate 40 as the intermediate layer.
Stress relaxation layer 85,86 is formed by the conductive material that copper etc. has conductivity.In addition, stress relaxation layer 85,86 forms the section shape of a mesh by wire rod being arranged to mesh-shape, but is not limited to this.This stress relaxation layer 85,86 mildly (flexibly) relaxes stress.
Like this,,, can relax stress, so can prevent the damage of the IGBT element 20 that stress causes by stress relaxation layer 85,86 is set according to the semiconductor packages 10 of the 5th execution mode.Its result can improve the part reliability of semiconductor packages 10.
In addition, in the manufacturing process of semiconductor packages 10, as Fig. 8 and shown in Figure 9, even, also can prevent to cause the damage of IGBT element 20 because of this external force having applied under the situations such as external force.The reduction of the rate of finished products in the manufacturing in the time of as a result, can suppressing to make semiconductor packages 10.
And then, and during modularization, can prevent the damage of the semiconductor packages 10 that in the manufacturing process of this semiconductor module, causes because of the external force that imposes on semiconductor packages 10 with 10 combinations of a plurality of semiconductor packages, particularly can prevent the damage of IGBT element 20.Its result, the reduction of the rate of finished products in the manufacturing in the time of can suppressing to make semiconductor module.
(the 6th execution mode)
With reference to Figure 13 the 6th execution mode of the present invention is described.
The 6th execution mode of the present invention is identical with the 1st execution mode basically, and parts different with the 1st execution mode in the 6th execution mode is described.
The difference of the 6th execution mode and the 1st execution mode is, as shown in figure 13, between IGBT element 20 and the 1st battery lead plate 30, possess stress relaxation layer 87, between IGBT element 20 and the 2nd battery lead plate 40, possess stress relaxation layer 88 with stress relaxation properties and conductivity with stress relaxation properties and conductivity.
Stress relaxation layer 87 is located on the base main body 31 as the jut 32 on the base main body 31 of the 1st battery lead plate 30, is clamped by jut main body 32a, 32b as the intermediate layer of jut main body 32a, 32b.Jut main body 32a joins on the base main body 31 by soldered joint.Thus, between jut main body 32a and base main body 31, be formed with soldering-tin layer 73.
In addition, stress relaxation layer 88 is arranged among the stress mitigation electrode 41b as the intermediate layer.Stress relaxes electrode 41b and is bonded between IGBT element 20 and the 2nd battery lead plate 40 by soldered joint.Thus, between IGBT element 20 and stress mitigation electrode 41b, be formed with soldering-tin layer 72, between the 2nd battery lead plate 40 and stress mitigation electrode 41b, be formed with soldering-tin layer 74.
Stress relaxation layer 87,88 is formed by the conductive material that copper etc. has conductivity.In addition, stress relaxation layer 87,88 forms the fine copper wire band by fine copper wire is woven as cloth, but is not limited to this.This stress relaxation layer 87,88 mildly (flexibly) relaxes stress, particularly relaxes because of IGBT element the 20, the 1st battery lead plate 30, and the stress that produces of the thermal expansion of the 2nd battery lead plate 40.
Like this,,, can relax stress, so can prevent the damage of the IGBT element 20 that stress causes by stress relaxation layer 87,88 is set according to the semiconductor packages 10 of the 6th execution mode.Its result can improve the part reliability of semiconductor packages 10.
In addition, in the manufacturing process of semiconductor packages 10, as Fig. 8 and shown in Figure 9, even, also can prevent to cause the damage of IGBT element 20 because of this external force having applied under the situations such as external force.Its result, the reduction of the rate of finished products in the manufacturing in the time of can suppressing to make semiconductor packages 10.
And then, and during modularization, can prevent the damage of the semiconductor packages 10 that in the manufacturing process of this semiconductor module, causes because of the external force that imposes on semiconductor packages 10 with 10 combinations of a plurality of semiconductor packages, particularly can prevent the damage of IGBT element 20.Its result, the reduction of the rate of finished products in the manufacturing in the time of can suppressing to make semiconductor module.
(the 7th execution mode)
With reference to Figure 14 and Figure 15 the 7th execution mode of the present invention is described.In addition, in the 7th execution mode, an example of the semiconductor module 11 of the semiconductor packages 10 with any execution mode in the above-mentioned the 1st to the 6th is described.
As Figure 14 and shown in Figure 15, the semiconductor module 11 of the 7th execution mode has: the semiconductor packages 10 of any execution mode in the 1st to the 6th; A plurality of FRD elements (using rectifier cell at a high speed) 12; The 1st conductive component 91 and the 2nd conductive component 92 have conductivity, are set to each semiconductor packages 10 of clamping and each FRD element 12; Heating panel 94, the 1 conductive components 91 and the 2nd conductive component 92 are set up via insulators such as heat insulating lamella or insulation board 93.
Semiconductor packages 10 and conductive component 91,92 engage by soldered joint, and semiconductor packages 10 is electrically connected with conductive component 91,92.In addition, FRD element 12 and conductive component 91,92 engage by soldered joint, and FRD element 12 is electrically connected with conductive component 91,92.Thus, between semiconductor packages 10 and conductive component 91,92, be formed with soldering-tin layer 75, between FRID element 12 and conductive component 91,92, also be formed with soldering-tin layer 75.Here, soldered joint is that fusion engages.
Conductive component 91,92 has conductivity, plays the function as the common electrod assembly of each semiconductor packages 10 and each FRD element 12, also has heat conductivity, plays the function as thermal component.Here, the 1st conductive component 91 is connected with the 1st battery lead plate 30 (with reference to Fig. 1) of semiconductor packages 10, plays the effect as the radio polar region.In addition, the 2nd conductive component 92 is connected with the 2nd battery lead plate 40 (with reference to Fig. 1) of semiconductor packages 10, plays the effect as collector area.
Like this, according to the semiconductor module 11 of the 7th execution mode, can access the identical effect of effect that obtains with semiconductor packages 10 by the 1st to the 6th any execution mode.
(the 8th execution mode)
With reference to Figure 16 and Figure 17 the 8th execution mode of the present invention is described.
The 8th execution mode of the present invention is identical with the 7th execution mode basically, in the 8th execution mode, the part different with the 7th execution mode is described.
The difference of the 8th execution mode and the 7th execution mode is that in semiconductor module 11, the soldered joint that forms soldering-tin layer 75 is a diffusion bond.
The assembling process of semiconductor module 11 is described here.
At first, as shown in figure 16, a plurality of semiconductor packages 10 and a plurality of FRD element 12 are positioned on the 2nd conductive component 92, via scolding tin thin slice 75a the 1st conductive component 91 are positioned on each semiconductor packages 10 and each FRD element 12 again via scolding tin thin slice 75a.The 1st conductive component 91, semiconductor packages 10, FRD element 12 and the 2nd conductive component 92 with this after stacked is arranged in the decompression extruder, the extruding of reducing pressure under predetermined condition (for example squeeze pressure is that 4MPa, temperature are that 210 ℃, decompression are smaller or equal to 10Torr).This condition is set according to scolding tin composition of employed scolding tin thin slice 75a etc.In addition, in the 6th execution mode, for example squeeze pressure the scope of 0.5MPa～10MPa, temperature 150 ℃～300 ℃ scope, be pressurised in the scope smaller or equal to 50Torr and set.Diffusion bond by being undertaken by the decompression extruding joins each semiconductor packages 10 and each FRD element 12 on the conductive component 91,92 to.
Then, as shown in figure 17, via insulator 93, each conductive component 91,92 of clamping semiconductor packages 10 and FRD element 12 is positioned on the heating panel 94.The heating panel 94 of this stacked state is arranged on adds in the heat extruder, under predetermined condition, add hot extrusion.By by adding the fusion of hot extrusion, each conductive component 91,92 is engaged with heating panel 94 insulator 93.Thus, Figure 14 and semiconductor module 11 have as shown in Figure 15 been finished.
Like this, according to the semiconductor module 11 of the 8th execution mode, can access the identical effect of effect that obtains with semiconductor packages 10 by the 1st to the 6th any execution mode.And then, by diffusion bond semiconductor packages 10 is engaged with conductive component 91,92 by soldering, thereby can prevent the fusion of scolding tin, can prevent from when semiconductor packages 10 being engaged with conductive component 91,92, to cause the damage of semiconductor packages 10, particularly can prevent the damage of IGBT element 20 because of the solidification shrinkage of scolding tin by the fusion soldered joint.Its result can be suppressed at the reduction of the rate of finished products in the manufacturing when making semiconductor module 11.
(the 9th execution mode)
With reference to Figure 18 the 9th execution mode of the present invention is described.
The 9th execution mode of the present invention is identical with the 7th or the 8th execution mode basically, in the 9th execution mode, illustrates and the different part of the 7th or the 8th execution mode.
The difference of the 9th execution mode and the 7th or the 8th execution mode is as shown in figure 18, in semiconductor module 11, to have the resin portion 81 of surrounding semiconductor module 11 and being provided with between the 1st conductive component 91 and the 2nd conductive component 92.
Resin portion 81 is by being filled into resin in the space between the 1st conductive component 91 and the 2nd conductive component 92, be arranged on each semiconductor packages 10 and each FRD element 12 (with reference to Figure 15) around.Thus, the 1st conductive component 91 and the 2nd conductive component 92 is affixed, covered by resin portion 81 around each semiconductor packages 10 and each the FRD element 12.In addition, resin carry out the engaging of semiconductor packages 10 and each conductive component 91,92 (with reference to Figure 16) afterwards, add hot extrusion (with reference to Figure 17) before, be filled in the space between the 1st conductive component 91 and the 2nd conductive component 92.
Like this, semiconductor module 11 according to the 9th execution mode, by in the space between the 1st conductive component 91 and the 2nd conductive component 92 resin portion 81 being set, improved the mechanical strength of semiconductor module 11, so can prevent from particularly can prevent the damage of IGBT element 20 because of cause the damage of semiconductor packages 10 from impact of outside etc.As its result, can improve the part reliability of semiconductor module 11.
Particularly, semiconductor packages 10 after will engaging and each conductive component 91,92 are arranged on the heating panel 94 and before heating extruding, resin portion 81 is set in the space between the 1st conductive component 91 and the 2nd conductive component 92, so, can prevent from particularly can prevent the damage of IGBT element 20 because of adding the damage that hot extrusion causes semiconductor packages 10.。Its result can be suppressed at the reduction of the rate of finished products in the manufacturing when making semiconductor module 11.
At last, the present invention is not limited to above-mentioned execution mode, and is self-evident, can make various changes in the scope that does not break away from its purport.In addition, by a plurality of structural elements shown in the above-mentioned execution mode are carried out suitable combination, can form various inventions.For example, also can from all structural elements shown in the above-mentioned execution mode, remove certain several structural element.And then, also the structural element of different execution modes suitably can be made up.

Claims (16)

1, a kind of semiconductor packages is characterized in that, has:
Tabular semiconductor element has the 1st power terminal and control terminal on interarea, with the opposed back side of above-mentioned interarea on have the 2nd power terminal;
The 1st battery lead plate with the above-mentioned interarea opposite disposed of above-mentioned semiconductor element, has the 1st electric power electrode that is connected with above-mentioned the 1st power terminal by soldered joint;
The 2nd battery lead plate with the above-mentioned back side opposite disposed of above-mentioned semiconductor element, has the 2nd electric power electrode that is connected with above-mentioned the 2nd power terminal by soldered joint; And
Insulated substrate is located between above-mentioned semiconductor element and above-mentioned the 1st battery lead plate, has the control electrode that is connected with above-mentioned control terminal by soldered joint.
2, semiconductor packages as claimed in claim 1, it is characterized in that, above-mentioned insulated substrate has from the outstanding laterally protuberance of each outer peripheral edges of above-mentioned semiconductor element, above-mentioned the 1st battery lead plate and the 2nd battery lead plate, possesses the external connection terminals that is connected with above-mentioned control terminal on this protuberance.
3, semiconductor packages as claimed in claim 1 is characterized in that,
Above-mentioned the 1st electric power electrode is the jut to above-mentioned semiconductor element side projection;
Above-mentioned insulated substrate possesses peristome or the notch that above-mentioned jut passes.
4, semiconductor packages as claimed in claim 1 is characterized in that,
Above-mentioned insulated substrate with the opposed surface of above-mentioned the 1st battery lead plate on have anchor pad,
Above-mentioned the 1st battery lead plate engages by soldered joint with the said fixing pad.
5, semiconductor packages as claimed in claim 1 is characterized in that, each outer peripheral edges of above-mentioned the 2nd battery lead plate and above-mentioned insulated substrate are located at than the outer peripheral edges of above-mentioned semiconductor element in the outer part; Have liner between above-mentioned the 2nd battery lead plate and above-mentioned insulated substrate, this liner location is arranged on than each outer peripheral edges of above-mentioned semiconductor element in the outer part, and the spacing distance between above-mentioned the 2nd battery lead plate and the above-mentioned insulated substrate is remained necessarily.
6, semiconductor packages as claimed in claim 5 is characterized in that, above-mentioned liner has metal material from the teeth outwards, engages with in above-mentioned the 2nd battery lead plate and the above-mentioned insulated substrate at least one by soldered joint.
7, semiconductor packages as claimed in claim 5 is characterized in that, above-mentioned liner is equipped with the chip part of electric electric passive component in being.
8, semiconductor packages as claimed in claim 1 is characterized in that, above-mentioned soldered joint is a diffusion bond.
9, semiconductor packages as claimed in claim 1 is characterized in that, also has the resin portion of surrounding above-mentioned semiconductor element and being provided with between above-mentioned the 1st battery lead plate and above-mentioned the 2nd battery lead plate.
10, semiconductor packages as claimed in claim 1 is characterized in that, also possesses the stress relaxation layer with stress relaxation properties and conductivity.
11, semiconductor packages as claimed in claim 1 is characterized in that, above-mentioned the 1st battery lead plate possesses the stress relaxation layer with stress relaxation properties and conductivity.
12, semiconductor packages as claimed in claim 1 is characterized in that, above-mentioned the 2nd battery lead plate possesses the stress relaxation layer with stress relaxation properties and conductivity.
13, as each described semiconductor packages in the claim 10 to 12, it is characterized in that above-mentioned stress relaxation layer forms the section mesh-shape.
14, a kind of semiconductor module is characterized in that, has:
Each described semiconductor packages in the claim 1 to 12; And
The 1st conductive component and the 2nd conductive component have conductivity, respectively the above-mentioned semiconductor packages of clamping and being provided with.
15, as claim 14 semiconductor module, it is characterized in that,
Above-mentioned semiconductor packages is connected by soldered joint with above-mentioned the 1st conductive component;
Above-mentioned semiconductor packages is connected by soldered joint with above-mentioned the 2nd conductive component;
Above-mentioned soldered joint is a diffusion bond.
16, as claim 14 semiconductor module, it is characterized in that between above-mentioned the 1st conductive component and above-mentioned the 2nd conductive component, also having the resin portion of surrounding above-mentioned semiconductor packages and being provided with.
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US9018832B2 (en) 2010-09-30 2015-04-28 Sharp Kabushiki Kaisha Light-emitting device and lighting device provided with the same
US9188321B2 (en) 2010-09-30 2015-11-17 Sharp Kabushiki Kaisha Light-emitting device and lighting device provided with the same
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