CN1773727A - Semiconductor, semiconductor chip and producing method thereof - Google Patents
Semiconductor, semiconductor chip and producing method thereof Download PDFInfo
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- CN1773727A CN1773727A CN 200510089249 CN200510089249A CN1773727A CN 1773727 A CN1773727 A CN 1773727A CN 200510089249 CN200510089249 CN 200510089249 CN 200510089249 A CN200510089249 A CN 200510089249A CN 1773727 A CN1773727 A CN 1773727A
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Abstract
The present invention provides a semiconductor device, semiconductor wafer and manufacturing method thereof, concretely relates to a semiconductor-on-insulator device containing silicon covering on an insulating layer.
Description
Technical field
The invention relates to semiconductor integrated circuit, particularly about have＜cover semiconductor (semiconductor-on-insulator on 100〉orientation transistors the insulating barrier; SOI) wafer.
Background technology
At the length direction stress application, that is can improve the electronics in NMOS and the PMOS transistor and the mobility (mobility) in hole respectively at the sense of current stress application.By using the megasoma silicon base of traditional tool (001) planar orientation (orientation), and form the transistor of source electrode to being oriented to of drain electrode＜110〉direction, the stress that is applied to length direction can cause different effects to electronics and hole, not to increase electron mobility and reduce hole mobility, reduce electron mobility exactly and increase hole mobility.
Summary of the invention
In view of this, the present invention provides a kind of integrated circuit for overcoming defective of the prior art, comprises: the semiconductor substrate, have＜100 orientation; At least one field-effect transistor is in above-mentioned substrate, and above-mentioned transistor has at least one grid; And at least two electrical contact points of intraconnections contact above-mentioned transistor.
The present invention is and a kind of semiconductor device is provided, comprises: a silicon active region on an insulating barrier, above-mentioned silicon active region have (001) orientation upper surface and＜100 crystallization direction; And one substrate under above-mentioned insulating barrier, above-mentioned substrate has＜110 crystallization direction; Wherein above-mentioned silicon active region＜100〉direction be parallel in fact above-mentioned substrate＜110〉direction.
The present invention is and a kind of semiconductor device is provided, comprises: an insulating barrier; One silicon active region is in first side of above-mentioned insulating barrier, and wherein above-mentioned silicon active region has first crystallization direction; One substrate is in second side of above-mentioned insulating barrier, and wherein above-mentioned substrate has second crystallization direction.
Semiconductor device of the present invention, this first crystallization direction are＜100〉direction, this second crystallization direction is＜110〉direction, and this second crystallization direction is parallel to this first crystallization direction in fact.
Semiconductor device of the present invention, this silicon active region and this substrate have the upper surface of (001) orientation.
Semiconductor device of the present invention, this silicon active region has elongation strain.
Semiconductor device of the present invention, this active region has elongation strain, this elongation strain in fact along this silicon active region＜100〉direction.
Semiconductor device of the present invention, the first transistor that more comprises the first conduction form is formed on this silicon active region, and this first transistor has a strained channel region.
Semiconductor device of the present invention, this strained channel region are to have elongation strain in source electrode to the direction that drains.
Semiconductor device of the present invention more comprises a stress film on this first transistor, and the stress value of this stress film is 200MPa～2GPa.
Semiconductor device of the present invention, the thickness of this silicon active region are 20～2000 .
Semiconductor device of the present invention, the corner of this silicon active region has skill facet or fillet.
The present invention is and a kind of semiconductor wafer is provided, comprises: first active region and second active region on an insulating barrier, above-mentioned first active region and above-mentioned second active region have (001) orientation upper surface and＜100 crystallization direction; And one substrate under above-mentioned insulating barrier, above-mentioned substrate has＜110 crystallization direction; Wherein above-mentioned first active region and above-mentioned second active region＜100〉crystallization direction be parallel in fact above-mentioned substrate＜110〉crystallization direction.
Semiconductor wafer of the present invention more comprises a N type channel region transistor and is formed on this first active region, is formed on this second active region with a P type channel region transistor.
Semiconductor wafer of the present invention, a N type channel region transistor AND gate the one P type channel region transistor respectively has a strained channel region.
Semiconductor wafer of the present invention, this substrate have the upper surface of (001) orientation.
Semiconductor wafer of the present invention, the thickness of this first active region and this second active region is 20～300 .
Semiconductor wafer of the present invention, a N type channel region transistor AND gate the one P type channel region transistor is isolated by high platform isolation structure or fleet plough groove isolation structure.
The present invention is and a kind of soi semiconductor device is provided, comprises: a silicon active region on an insulating barrier, above-mentioned silicon active region have (001) orientation upper surface and＜100 crystallization direction; One substrate is under above-mentioned insulating barrier; And the first transistor is formed on the part of above-mentioned silicon active region, and above-mentioned the first transistor has a strained channel region.
The present invention is and a kind of manufacture method of semiconductor device is provided, comprises: semiconductor structure is provided, has a plurality of silicon active regions on an insulating barrier, above-mentioned silicon active region has the upper surface and＜100 of (001) orientation〉crystallization direction; Provide a substrate under above-mentioned insulating barrier, above-mentioned substrate has＜110 crystallization direction, wherein above-mentioned silicon active region＜100〉crystallization direction be parallel in fact above-mentioned substrate＜110〉crystallization direction; Form one and pile up grid structure in above-mentioned silicon active region at least on one of them; Form an one source pole district and a drain region and be adjacent to above-mentioned stacked gate architectures opposition side, to form a transistor, above-mentioned transistor has the direction of one source pole to grid, in fact along above-mentioned silicon active region＜100〉crystallization direction; And to being less than formation one stress film on the above-mentioned transistor.
The manufacture method of semiconductor device of the present invention more comprises: form a protective layer on this stress film; Form contact hole in this diaphragm; And an electric conducting material inserted in this contact hole and form this transistorized contact point.
The manufacture method of semiconductor device of the present invention, the thickness of those active regions are 20～500 .
The manufacture method of semiconductor device of the present invention is isolated by high platform isolation structure or fleet plough groove isolation structure between those active regions.
Description of drawings
Fig. 1 is a decomposing schematic representation, is to be presented on the insulating barrier of substrate top, forms a silicon layer;
Fig. 2 is a schematic perspective view, is that the direction that shows silicon layer and silicon base in the SOI wafer is orientated;
Fig. 3 is the schematic perspective view of the SOI wafer of Fig. 2, is the transistor arrangement that shows one embodiment of the invention;
Fig. 4 a is the profile of Fig. 3, is high platform (mesa) isolation structure that shows active region;
Fig. 4 b is the profile of Fig. 3, is the fleet plough groove isolation structure that shows active region;
Fig. 5 a to Fig. 5 h is a series of profile, is the manufacturing process that shows SOI wafer in one embodiment of the invention.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, one (a bit) cited below particularly preferred embodiment, and cooperate appended diagram, be described in detail below:
Traditionally, the processing procedure of CMOS is to use the megasoma silicon base of tool (001) planar orientation, as the parent material of making NMOS and PNOS element.Be formed at transistorized source electrode in the above-mentioned traditional substrate to the orientation of drain electrode, that is raceway groove (channel) be oriented to＜110〉direction.＜110〉labelling method general reference all＜110 direction family (equivalentdirection), for example comprise [110] direction and [i10] direction.Also use the labelling method that indicates crystallization direction and crystal plane on the crystallography at this.[110] direction is respectively perpendicular to (110) and crystal plane (i10) with [i10] direction.Subsidiary one carries, and (110) of silicon are the crystal planes that splitting (cleave) takes place very easily with (110) face.
Please refer to Fig. 1, a SOI substrate 100 is to be used for one embodiment of the invention.SOI substrate 100 is to comprise a silicon layer 30, (001) face that is oriented on its surface.Silicon layer 30 is as an example in the present embodiment, and for example silicon-germanium layer, laminated film (multi-layer), diamond, gallium and/or arsenic replace silicon layer 30 can also to use other material.Above-mentioned laminated film can comprise for example a silicon-germanium layer and a silicon layer.
Insulating barrier 40 is to be positioned in the substrate 10, and substrate 10 for example is the semiconductor-based end of a silicon base or other material.Please refer to the legend 11,31 with Miller indices (Miller Index) mark, the silicon base 10 of present embodiment is a traditional silicon base, being oriented to of its V-type groove (notch) 14＜110〉one of direction family.Yet, silicon layer 30＜100〉crystallization direction be to point to V-type groove 14.[110] direction of substrate 10 be parallel with [100] direction of silicon layer 30 in fact (or with parallel have positive and negative 10 the degree angles with interior gap).
Be formed at the first transistor 16 on the silicon layer 30, its source electrode is oriented to the crystallization direction of [010] to the direction of drain electrode; Be formed at the transistor 18 in silicon layer 30 another districts, its source electrode is oriented to the crystallization direction of [100] to the direction of drain electrode.Therefore, the source electrode of the first transistor 16 and transistor seconds 18 to the direction orientation of drain electrode is all＜one of 100〉direction families.The first transistor 16 can be all NMOS or PMOS transistor or different types of transistor with transistor seconds 18.When the orientation positions of the first transistor 16 and transistor seconds 18 be＜100〉direction families, the mobility of charge carrier rate that can reduce promoted the phenomenon that forms equivalent decline because of another mobility of charge carrier rate.
Please refer to Fig. 2, through processing procedure the silicon layer 30 of Fig. 1 is become and be used for forming active member or transistorized active region 30a～30d.Silicon active region 30a～30d has the upper surface of (001) orientation.Can use for example mode of plasma etching, cut silicon layer 30 and formation active region 30a～30d.One plane 34 is meant separation or cuts into wafer 12a, 12b part.Because the plane 34 of separating wafer 12a, 12b be parallel to substrate 10 { 110} plane or family of planes (equivalent plane), for example a splitting surface can help cutting apart of substrate.Because active region 30a～30d can not cut in plane 34, its whether be parallel to active region 30a～30d { the 100} family of planes is just inessential.
Please refer to Fig. 3, is grid 16g, the 18g that shows the first transistor 16 and transistor seconds 18, and source electrode 16s, 18s are with drain electrode 16d, 18d.The first transistor 16 is to be formed on the silicon active region 30a, and its source electrode is parallel to [010] direction of silicon layer 30 to the direction silicon of drain electrode; Transistor seconds 18 is to be formed on the silicon active region 30b, and its source electrode is parallel to [100] direction of silicon layer 30 to the direction silicon of drain electrode. Active region 30a, 30b can be subjected to for example mechanical strain.Above-mentioned strain can be the strain of elongation strain or other form.In certain embodiments, some is subjected to strain 18 of the first transistor 16 and transistor secondses, and for example channel region can be subjected to strain.Grid 16g, 18g among Fig. 3 only is used for signal, and only is formed on the active region; And in fact, grid can extend to outside the active region.
The present invention can tell on to the circuit element of many variety classeses and framework.For example in Fig. 4 a, the groove 36 between active region 30a, the 30b was not filled with (for example using high platform isolation structure) before forming the first transistor 16 and transistor seconds 18.Another example is shown in Fig. 4 b, and the groove 36 between active region 30a, the 30b had been filled with groove dielectric medium 60 (for example using groove isolation construction) before forming the first transistor 16 and transistor seconds 18.Groove dielectric medium 60 can be the silica that for example forms with chemical vapour deposition technique, can also be with the formed silica of high-density plasma sedimentation.
Please refer to Fig. 4 a and Fig. 4 b, the thickness t of silicon active region 30a, 30b
SiCan be 20～2000 , be less than 300 in the present embodiment.The profile that please notes Fig. 4 a, Fig. 4 b is only to be used for signal.For example silicon active region 30a, 30b not necessarily have acute angle.The corner of silicon active region 30a, 30b might be that skill facet (faceted) or fillet are arranged, and the radius of curvature of above-mentioned fillet for example is 10～500 .
Next please refer to Fig. 5 a, the line that central authorities by SOI substrate 100 extend to V-type groove 14 shown in Figure 1 can exceed the scope of the page.[010] crystallization direction of silicon layer 30 parallel in fact with [110] crystallization direction of silicon base 10 (or have positive and negative 10 the degree angles difference).The formation of SOI substrate 100 can engage the technology of (wafer bonding) or wafer separate (wafer seperation) by for example wafer.
Please refer to Fig. 5 b, in silicon layer 30, form groove 36,, can be covered on the predetermined zone that forms active region 30a, 30b by forming a patterned mask with definition active region 30a, 30b, however the silicon layer 30 that etching exposes to the open air and form groove 36.Above-mentioned etching can for example be the plasma etching of dry type.When using high platform isolation structure, before forming transistor, groove 36 can not be filled with; Use shallow trench isolation from (shallow trenchisolation; SOI) during structure, can insert groove 36 with trench fill material (component symbol 60 of Fig. 5 c), above-mentioned trench fill material for example be the silicon dioxide with chemical vapour deposition technique formation.Then formed structure is given planarization, and remove above-mentioned pattern mask layer, and the structure of formation shown in Fig. 5 c.
Please refer to Fig. 5 d, one piles up grid structure 17 is formed on the active region 30a.Stacked gate architectures 17 comprises gate dielectric layer 16c and the grid 16e on it.Gate dielectric layer 16c can be by any known or gate dielectric layer formation technology of being used, for example thermal oxidation, nitrogenize, splashes deposition (sputter deposition) or chemical vapour deposition (CVD), is formed on the active region 30a.The actual (real) thickness of gate dielectric layer 16c (physical thickness) can be 5～100 .Gate dielectric layer 16c can use traditional grid dielectric medium for example silica, silicon oxynitride, high dielectric constant material or above-mentioned combination.The dielectric constant of above-mentioned high dielectric constant material can be selected from for example aluminium oxide (Al greater than 8
2O
3), hafnium oxide (HfO
2), nitrogen hafnium oxide (HfON), hafnium silicate (HfSiO
4), zirconia (ZrO
2), nitrogen zirconia (ZrON), zirconium silicate (ZrSiO
4), yittrium oxide (Y
2O
3), lanthana (La
2O
3), cerium oxide (CeO
3), titanium oxide (TiO
2), tantalum oxide (Ta
2O
5) or above-mentioned combination.In one embodiment, above-mentioned high K dielectric matter is hafnium oxide.The equivalent silicon oxide thickness of gate dielectric layer 16c (silicon oxide equivalent thickness; EOT) can be greater than 5 , and be greater than 20 at present embodiment.The actual (real) thickness of gate dielectric layer 16c can be greater than 5 , and are greater than 40 at present embodiment.
The material that is used to deposit grid 16e can be deposited on gate dielectric layer 16c.The material that is used to deposit grid 16e can comprise the metal oxide of traditional polysilicon, polycrystalline silicon germanium, metal, metal silicide, metal nitride or tool conductivity.In one embodiment, grid 16e comprises polysilicon.Molybdenum, tungsten, titanium, tantalum, platinum, can be the part of grid 16e with metal such as hafnium.Metal nitride is including but not limited to following molybdenum nitride, tungsten nitride, titanium nitride, tantalum nitride; Metal silicide is including but not limited to following nickle silicide, cobalt silicide, tungsten silicide, titanium silicide, tantalum silicide, platinum silicide, silication erbium (erbium); The metal oxide of conductivity can be including but not limited to following ruthenium-oxide, tin indium oxide.
The deposition of above-mentioned grid material can be used for example chemical vapour deposition (CVD) of traditional technology.The formation of grid material can also form silicon and metal earlier, is annealed and forms the material of metal silicide as grid material.Technology with deposition and little shadow (photolithography) forms a patterned gate mask layer on above-mentioned grid material then.Above-mentioned gate mask layer can use general mask material such as but not limited to silica, silicon oxynitride and silicon nitride.Next form grid 16e with the above-mentioned grid material of processing procedure etching of plasma etching.The grid material that is not capped usually can be totally etched.
Please refer to Fig. 5 e, carry out the doping step of source electrode and drain electrode extension area.The formation of one clearance wall (spacer) 72 for example is to form a clearance wall dielectric medium (as silicon nitride) earlier, it is formed as anisotropic etching again.Please note that clearance wall 72 can comprise the different dielectric medium of multilayer for example silicon nitride and silica.Thereafter one second step of mixing with the source electrode of deep layer more and drain electrode can continue.
Please refer to Fig. 5 f, source electrode 16s in the transistor 16, drain electrode 16d, can reduce because of form a silicide 76 on source/drain regions with the impedance of grid 16e, the formation of silicide 76 can be used for example self aligned silicidation process or the processing procedure of other metal deposition.Can form a mask earlier before above-mentioned silicidation process, for example oxide covers the part (for example must keep the active region of high impedance value) that substrate need not done silication.For example, with above-mentioned silicidation process grid 16e, source electrode 16s, with drain electrode 16d on when forming silicide, use oxide mask to cover active region.
Please refer to Fig. 5 g, can deposit a high stress films 80, next deposit a protective layer 82.High stress films 80 can be to increase liquefaction with plasma to learn silicon nitride or the silicon oxynitride layer that vapour deposition process forms.In the present embodiment, high stress films 80 is to be deposited on MMOS and the PMOS transistor, and its stress value can be 200MPa～2GPa.When the thinner thickness of active region 30a, the 30b of Fig. 5 b, the stress that acts on the transistor channel region will strengthen.When the contraction in length of grid (for example grid 16g of Fig. 3), the stress of channel region also can increase.
Please refer to Fig. 5 h,, rest on the etching stopping layer and form contact hole protective layer 82 eating throwns.Then an electric conducting material is inserted in the above-mentioned contact hole and formed transistorized contact point 84.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
10: substrate
11: legend
12a: wafer
12b: wafer
14:V type groove
16c: gate dielectric layer
16d: drain electrode
16e: grid
16g: grid
16s: source electrode
17: stacked gate architectures
18d: drain electrode
18g: grid
18s: source electrode
30: silicon layer
30a, 30b, 30c, 30d: active region
31: legend
34: the plane
36: groove
40: insulating barrier
60: the groove dielectric medium
72: clearance wall
76: silicide
80: high stress films
82: protective layer
84: contact point
The 100:SOI substrate
Claims (20)
1, a kind of semiconductor device is characterized in that described semiconductor device comprises:
One insulating barrier;
One silicon active region is in first side of this insulating barrier, and wherein this silicon active region has first crystallization direction;
One substrate is in second side of this insulating barrier, and wherein this substrate has second crystallization direction.
2, semiconductor device according to claim 1 is characterized in that: this first crystallization direction for＜100〉direction, this second crystallization direction is＜110〉direction, this second crystallization direction is parallel to this first crystallization direction in fact.
3, semiconductor device according to claim 1 is characterized in that: this silicon active region and this substrate have the upper surface of (001) orientation.
4, semiconductor device according to claim 1 is characterized in that: this silicon active region has elongation strain.
5, semiconductor device according to claim 2 is characterized in that: this active region has elongation strain, this elongation strain in fact along this silicon active region＜100〉direction.
6, semiconductor device according to claim 1 is characterized in that: the first transistor that more comprises the first conduction form is formed on this silicon active region, and this first transistor has a strained channel region.
7, semiconductor device according to claim 6 is characterized in that: this strained channel region is to have elongation strain in source electrode to the direction that drains.
8, semiconductor device according to claim 4 is characterized in that: more comprise a stress film on this first transistor, the stress value of this stress film is 200MPa～2GPa.
9, semiconductor device according to claim 7 is characterized in that: the thickness of this silicon active region is 20～2000 .
10, semiconductor device according to claim 7 is characterized in that: the corner of this silicon active region has skill facet or fillet.
11, a kind of semiconductor wafer is characterized in that described semiconductor wafer comprises:
First active region and second active region on an insulating barrier, this first active region and this second active region have (001) orientation upper surface and＜100 crystallization direction; And
One substrate under this insulating barrier, this substrate has＜110 crystallization direction;
Wherein this first active region and this second active region＜100〉crystallization direction be parallel in fact this substrate＜110〉crystallization direction.
12, semiconductor wafer according to claim 11 is characterized in that: more comprise a N type channel region transistor and be formed on this first active region, be formed on this second active region with a P type channel region transistor.
13, semiconductor wafer according to claim 12 is characterized in that: a N type channel region transistor AND gate the one P type channel region transistor respectively has a strained channel region.
14, semiconductor wafer according to claim 13 is characterized in that: this substrate has the upper surface of (001) orientation.
15, semiconductor wafer according to claim 11 is characterized in that: the thickness of this first active region and this second active region is 20～300 .
16, semiconductor wafer according to claim 12 is characterized in that: a N type channel region transistor AND gate the one P type channel region transistor is isolated by high platform isolation structure or fleet plough groove isolation structure.
17, a kind of manufacture method of semiconductor device is characterized in that the manufacture method of described semiconductor device comprises:
Semiconductor structure is provided, has a plurality of silicon active regions on an insulating barrier, those silicon active regions have (001) orientation upper surface and＜100 crystallization direction;
Provide a substrate under this insulating barrier, this substrate has＜110 crystallization direction, wherein those silicon active regions＜100〉crystallization direction be parallel in fact this substrate＜110〉crystallization direction;
Form one and pile up grid structure in those silicon active regions at least on one of them;
Form an one source pole district and a drain region and be adjacent to this stacked gate architectures opposition side, to form a transistor, this transistor has the direction of one source pole to grid, in fact along those silicon active regions＜100〉crystallization direction; And
Form a stress film on this transistor to being less than.
18, the manufacture method of semiconductor device according to claim 17 is characterized in that more comprising:
Form a protective layer on this stress film;
Form contact hole in this diaphragm; And
One electric conducting material inserted in this contact hole and form this transistorized contact point.
19, the manufacture method of semiconductor device according to claim 17 is characterized in that: the thickness of those active regions is 20～500 .
20, the manufacture method of semiconductor device according to claim 17 is characterized in that: isolated by high platform isolation structure or fleet plough groove isolation structure between those active regions.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/901,763 US7319258B2 (en) | 2003-10-31 | 2004-07-28 | Semiconductor-on-insulator chip with<100>-oriented transistors |
| US10/901,763 | 2004-07-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1773727A true CN1773727A (en) | 2006-05-17 |
| CN100477277C CN100477277C (en) | 2009-04-08 |
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ID=36028017
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100892495A Active CN100477277C (en) | 2004-07-28 | 2005-07-28 | Semiconductor wafer and producing method of semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2006049895A (en) |
| CN (1) | CN100477277C (en) |
| SG (1) | SG119256A1 (en) |
| TW (1) | TWI303862B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140954B (en) * | 2006-07-03 | 2011-01-26 | 瑞萨电子株式会社 | Semiconductor device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006019835B4 (en) * | 2006-04-28 | 2011-05-12 | Advanced Micro Devices, Inc., Sunnyvale | Transistor having a channel with tensile strain oriented along a crystallographic orientation with increased charge carrier mobility |
| JP2009065118A (en) * | 2007-08-09 | 2009-03-26 | Panasonic Corp | Solid-state imaging device |
| CN110420601B (en) * | 2019-08-02 | 2021-11-26 | 南京宁智高新材料研究院有限公司 | Quantitative treatment process through diamond anvil cell |
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|---|---|---|---|---|
| JPS5139078B1 (en) * | 1969-02-28 | 1976-10-26 | ||
| EP0235819B1 (en) * | 1986-03-07 | 1992-06-10 | Iizuka, Kozo | Process for producing single crystal semiconductor layer |
| JPH07335511A (en) * | 1994-06-13 | 1995-12-22 | Nippon Telegr & Teleph Corp <Ntt> | Bonded wafer |
| JP2002134374A (en) * | 2000-10-25 | 2002-05-10 | Mitsubishi Electric Corp | Semiconductor wafer and its manufacturing method and device |
| JP4597479B2 (en) * | 2000-11-22 | 2010-12-15 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| JP3595786B2 (en) * | 2001-08-27 | 2004-12-02 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
| JP2003209259A (en) * | 2002-01-17 | 2003-07-25 | Fujitsu Ltd | Method for manufacturing semiconductor device and semiconductor chip |
| JP4030383B2 (en) * | 2002-08-26 | 2008-01-09 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| JP4294935B2 (en) * | 2002-10-17 | 2009-07-15 | 株式会社ルネサステクノロジ | Semiconductor device |
-
2004
- 2004-12-21 SG SG200407553A patent/SG119256A1/en unknown
-
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- 2005-07-27 JP JP2005217268A patent/JP2006049895A/en active Pending
- 2005-07-28 TW TW94125614A patent/TWI303862B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140954B (en) * | 2006-07-03 | 2011-01-26 | 瑞萨电子株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| SG119256A1 (en) | 2006-02-28 |
| TWI303862B (en) | 2008-12-01 |
| TW200625539A (en) | 2006-07-16 |
| CN100477277C (en) | 2009-04-08 |
| JP2006049895A (en) | 2006-02-16 |
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