CN1773513A - First-in first-out analog unit and logic verification analog system - Google Patents
First-in first-out analog unit and logic verification analog system Download PDFInfo
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- CN1773513A CN1773513A CN 200410088935 CN200410088935A CN1773513A CN 1773513 A CN1773513 A CN 1773513A CN 200410088935 CN200410088935 CN 200410088935 CN 200410088935 A CN200410088935 A CN 200410088935A CN 1773513 A CN1773513 A CN 1773513A
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Abstract
A first-in and first-out artificial unit consists of artificial buffer storage unit for artificially buffer storing artificial data of first-in and first -out and artificial control unit for controlling and executing preset functional task of first-in and first-out in order to write in or read out artificial data of first-in and first -out from artificial buffer storage unit. In addition, a relevant logic verification artificial system is also disclosed.
Description
Technical field
The present invention relates to the computer simulation technique field, in particular, the present invention relates to a kind of first in first out simulation unit and logic checking analogue system that is applied in the computer logic emulation.
Background technology
Computer Simulation (CS, Computer Simulation) is a technology of utilizing computer software simulation true environment.At present, adopt computer simulation technique to realize that the logic checking analogue system of logic checking mainly comprises: emulation testing use-case unit, first in first out (FIFO, First In First Out) simulation unit, emulation bus functional mode unit and be verified logic, wherein emulation testing use-case unit produces the required data excitation of checking, through FIFO simulation unit buffer memory, send to emulation bus functional mode unit then, send to after adaptive through interface by emulation bus functional mode unit again and be verified logic; Send to emulation bus functional mode unit through being verified the data that logical process crosses, carry out verification through sending to emulation testing use-case unit behind the FIFO simulation unit buffer memory again, whether final to confirm to be verified logic correct.
General, when realizing described FIFO simulation unit, prior art adopts synchronously or asynchronous FIFO usually.Synchronously or asynchronous FIFO according to the read-write clock work, externally use read-write control signal and data line to realize interface with other modules.With reference to figure 1, this figure is the FIFO synoptic diagram in the traditional logic checking analogue system.Described FIFO mainly communicates by letter with extraneous according to control signals such as the write clock signal of emulation, read clock signals, what also comprise emulation between the emulation testing use-case unit in described in addition FIFO and the logic checking analogue system writes enable signal, write data signal, spacing wave and full signal, and also comprise emulation between the emulation bus functional mode unit read enable signal, reading data signal, spacing wave and full signal etc.
Above-mentioned prior art can realize the fifo circuit work of artificial actual, further can realize logic checking emulation, but also has following shortcoming:
At first, the FIFO simulation unit more complicated of above-mentioned existing techniques in realizing, the a large amount of circuit connections and the control signal that need other intermodule interfaces in emulation FIFO simulation unit and the logic checking analogue system, particularly then more complicated for the design of a plurality of FIFO of needs, increased the simulation work amount greatly.
For example, as shown in Figure 2, be example with a synchronization fifo, need the following control signal of emulation: rst: reset signal; Full: full signal; Alfull: almost expire signal; Empty: spacing wave; Alempty: spacing wave almost; Rd_en: read enable signal; Wr_en: write enable signal; Clk: work clock; Data_in: data input signal; Data_out: data output signal; Count: storage space counting; Err: mistake reports signal etc., even better simply realization also needs emulation FIFO simulation unit usually and realizes that with a plurality of control signals of external module interface the state of FIFO self reports and read and write control.When realizing a plurality of FIFO, simulation process will be more complicated.
Secondly, the FIFO simulation unit of existing techniques in realizing is used dumb, can not adapt to higher simulation requirements.Because the FIFO simulation unit just can be finished a read/write operation according to the read-write clock work every a read/write clock period in the prior art, can't adjust the speed that excitation produces flexibly according to the test needs of logic checking, also dumb in the use.
Once more, because prior art needs the physical connection of emulation FIFO simulation unit and other intermodules, therefore, the ease for use of module and reusability all reduce greatly.For example, just need physical connection between this FIFO of design of Simulation and external module for a FIFO, for a plurality of FIFO, then need the physical connection of a plurality of FIFO of design of Simulation and external module, therefore, the ease for use and the reusability of module reduce greatly.
Once more, also there is the lower shortcoming of efficient in prior art by the logic checking analogue system that described FIFO simulation unit realizes.Because the FIFO simulation unit is according to the read-write clock work, the operation of each address space of read/write all will take a read/write clock period.Like this, will inevitably take certain simulation time, reduce simulation efficiency.
Summary of the invention
The technical matters that the present invention solves provide a kind of realizations simply, use first in first out simulation unit flexibly and logic checking analogue system, with further raising simulation efficiency.
For addressing the above problem, first in first out simulation unit of the present invention comprises:
The emulation buffer storage is used for the emulated data of emulation buffer memory first in first out;
In addition, also comprise:
The Simulation Control device is used to control and carries out default first in first out functional task, to write or to read the emulated data of first in first out from described emulation buffer storage.
Wherein, described default first in first out functional task comprises:
Reading task if described first in first out simulation unit is not in reset mode, judges at first whether described first in first out simulation unit is empty, if be not empty, sense data from described first in first out simulation unit current address is read cyclic address change then;
Writing task if described first in first out simulation unit is not in reset mode, judges earlier whether described first in first out simulation unit is full, if not for full, write data in described first in first out simulation unit current address, write address adds one then;
Whether whether inquire about idle task, inquiring about and export described first in first out simulation unit is empty state value;
Whether inquiry expires task, and whether inquire about and export described first in first out simulation unit is full state value;
Almost whether inquiry idle task, and whether inquire about and export described first in first out simulation unit is almost empty state value;
Whether inquiry almost expires task, and whether inquire about and export described first in first out simulation unit is almost full state value;
Described Simulation Control device comprises:
The reading task module is used for control and carries out described reading task;
The writing task module is used for control and carries out described writing task;
Whether inquire about the idle task module, be used for control and carry out whether idle task of described inquiry;
Whether completely whether inquiry expires task module, be used for control and carry out described inquiry task;
Whether almost almost whether inquiry the idle task module, be used for control and carry out described inquiry idle task;
Whether inquiry almost expires task module, is used for the described inquiry of control execution and whether almost expires task.
Wherein, described emulation buffer storage comprises:
The emulated data buffer storage is used for the emulated data of emulation buffer memory first in first out;
The simulation status register is used for the full state of sky that described first in first out simulation unit is stored in emulation.
Correspondingly, logic checking analogue system of the present invention comprises:
Emulated data produces authentication unit, is used to produce the test case that logic checking emulation is used, and treats the test case that verifying logic handled and verify whether be verified logic with affirmation correct;
Emulation bus functional mode unit is used for that emulated data is produced test case data that authentication unit produces and sends to logic to be verified with the specific time sequence that is verified logic and is arranged; Or by receiving the data that are verified after the logical process with the specific time sequence that is verified logic agreement;
In addition, also comprise:
Send the first in first out simulation unit, be used for the test case emulation buffer memory that emulated data produces the authentication unit generation being sent to emulation bus functional mode unit according to default first in first out functional task;
Receive the first in first out simulation unit, be used for emulation bus functional mode unit emulated data buffer memory that receive, after being verified logical process being returned to emulated data generation authentication unit and verify according to default first in first out functional task.
Wherein, described transmission first in first out simulation unit comprises:
Emulation sends buffer storage, is used for the emulated data that the described emulated data of emulation buffer memory produces the first in first out that authentication unit sends;
The emulation transmission control device is used to control and carries out default first in first out functional task, produces the emulated data of the first in first out that authentication unit sends to write or to read described emulated data from described emulation buffer storage.
Wherein, described reception first in first out simulation unit comprises:
Emulation receives buffer storage, is used for the emulated data of the first in first out of sending the described bus functional model of emulation buffer memory unit;
The emulation receiving control device is used to control and carries out default first in first out functional task, to receive the emulated data that buffer storage write or read the first in first out of sending described emulation bus functional mode unit to described emulation.
Wherein, described default first in first out functional task comprises:
Reading task, if described transmission or reception first in first out simulation unit are not in reset mode, whether at first judge described transmission or receive the first in first out simulation unit is empty, if be not empty, sense data from described transmission or reception first in first out simulation unit current address is read cyclic address change then;
Writing task, whether if described transmission or reception first in first out simulation unit are not in reset mode, judging earlier described transmission or receiving the first in first out simulation unit is full, if for expiring, write data in described transmission or reception first in first out simulation unit current address, write address adds one then;
Whether whether inquire about idle task, inquiring about and export described transmission or receiving the first in first out simulation unit is empty state value;
Whether inquiry expires task, inquires about and exports described transmission or receive whether the first in first out simulation unit is full state value;
Almost whether inquiry idle task, and whether inquire about and export described transmission or receive the first in first out simulation unit is almost empty state value;
Whether inquiry almost expires task, inquires about and exports described transmission or receive whether the first in first out simulation unit is almost full state value;
Described emulation transmission control device and described emulation receiving control device include:
The reading task module is used for control and carries out described reading task;
The writing task module is used for control and carries out described writing task;
Whether inquire about the idle task module, be used for control and carry out whether idle task of described inquiry;
Whether completely whether inquiry expires task module, be used for control and carry out described inquiry task;
Whether almost almost whether inquiry the idle task module, be used for control and carry out described inquiry idle task;
Whether inquiry almost expires task module, is used for the described inquiry of control execution and whether almost expires task.
Wherein, described emulation transmission buffer storage comprises:
Emulation sends data buffer storage unit, is used for the described emulated data of emulation buffer memory and produces the test case data of authentication unit first in first out that send, to be sent;
Emulation transmit status register is used for the full state of sky that described transmission first in first out simulation unit is stored in emulation.
Wherein, described emulation reception buffer storage comprises:
Emulation receives data buffer storage unit, is used for the emulated data of first in first out that the described emulation bus functional mode of emulation buffer memory unit is sent, that cross through logical process to be verified;
Emulation accepting state register is used for the full state of sky that described reception first in first out simulation unit is stored in emulation.
Compared with prior art, the present invention has following beneficial effect:
At first, the present invention realizes simpler compared to existing technology, and FIFO simulation unit and peripheral modules need not emulated physics line and control signal, has reduced the simulation work amount greatly.
Secondly, the FIFO simulation unit that the present invention realizes is used more flexible compared to existing technology, the read or write speed of FIFO simulation unit can be set as required easily, and, improved the ease for use and the reusability of FIFO simulation unit greatly owing to need not the external physical connection and the control signal of emulation FIFO simulation unit and external module.
Once more, the FIFO simulation unit writes or sense data need not clock control in the logic checking analogue system that the present invention realizes, the read-write of FIFO simulation unit is not taken simulation time, therefore, can improve the simulation efficiency of logic checking analogue system greatly.
Description of drawings
Fig. 1 is the FIFO synoptic diagram in the prior art logic checking analogue system;
Fig. 2 is the control signal synoptic diagram that a kind of FIFO simulation unit of prior art relates to;
Fig. 3 is a FIFO simulation unit synoptic diagram of the present invention;
Fig. 4 is a kind of composition synoptic diagram of Simulation Control device shown in Figure 3;
Fig. 5 is the composition synoptic diagram of logic checking analogue system of the present invention;
Fig. 6 is the process flow diagram flow chart of writing that writes data in the logic checking analogue system of the present invention to the FIFO simulation unit;
Fig. 7 is from the read procedure process flow diagram of FIFO simulation unit sense data in the logic checking analogue system of the present invention.
Embodiment
In logic checking emulation, need to adopt the middle buffer memory of first in first out simulation unit usually as the emulated data of the unmatched interface circuit processing of speed.Traditional first in first out simulation unit is carried out data read-write operation according to the clock period, extremely inconvenient in practical operation, core of the present invention promptly is the first in first out functional task by default first in first out simulation unit execution, and then carry out the corresponding function that corresponding first in first out functional task can be realized the first in first out unit when needed, can avoid prior art by the relatively poor shortcoming of clock period control read-write operation dirigibility, thereby improve the efficient of logical simulation checking.
With reference to figure 3, this figure is the composition frame chart of first in first out simulation unit of the present invention.First in first out simulation unit of the present invention mainly comprises: emulation buffer storage 11 and Simulation Control device 12; Wherein
Described emulation buffer storage 11, be mainly used in the empty full state of emulated data and described first in first out unit of emulation buffer memory first in first out, the function of its realization is suitable with a static memory function, similar with a cell fifo, its storage mainly be that the store status data of data in buffer (being the emulated data of logic checking among the present invention) and FIFO emulation (also are the status data of FIFO in the middle of needing, expire state etc. as sky), also please refer to Fig. 3, during specific implementation, emulation buffer storage 11 of the present invention can further comprise:
Emulated data buffer storage 111 is used for the emulated data of emulation buffer memory first in first out, also is the required emulated data of cache logic checking;
Simulation status register 112 is used for the full state of sky that described first in first out simulation unit is stored in emulation.
In addition, described Simulation Control device 12 is mainly used in control and carries out default first in first out functional task, to write or to read the emulated data of first in first out from described emulation buffer storage.During concrete enforcement, according to the function of first in first out unit, predeterminable following first in first out functional task:
Reading task if described first in first out simulation unit is not in reset mode, judges at first whether described first in first out simulation unit is empty, if be not empty, sense data from described first in first out simulation unit current address is read cyclic address change then;
Writing task if described first in first out simulation unit is not in reset mode, judges earlier whether described first in first out simulation unit is full, if not for full, write data in described first in first out simulation unit current address, write address adds one then;
Whether whether inquire about idle task, inquiring about and export described first in first out simulation unit is empty state value;
Whether inquiry expires task, and whether inquire about and export described first in first out simulation unit is full state value;
Almost whether inquiry idle task, and whether inquire about and export described first in first out simulation unit is almost empty state value;
Whether inquiry almost expires task, and whether inquire about and export described first in first out simulation unit is almost full state.
The above-mentioned basic function task of only enumerating the first in first out simulation unit, during actual the realization, also predeterminable other first in first out functional task owing to can't be exhaustive, and be a key point of the present invention, no longer carefully states here.
With reference to shown in Figure 4, be that control carries out above-mentioned first in first out functional task, Simulation Control device of the present invention 12 is corresponding to comprise following composition module: reading task module 121, writing task module 122, inquire about whether idle task 123, module inquiry and whether expire task module 124, inquiry almost whether whether idle task module 125, inquiry expire task module 126; Wherein
Described reading task module 121 is used for control and carries out described reading task;
Described writing task module 122 is used for control and carries out described writing task;
Whether described inquiry idle task module 123, is used for control and carries out whether idle task of described inquiry;
Whether completely whether described inquiry expires task module 124, be used for control and carry out described inquiry task;
Whether almost almost whether described inquiry idle task module 125, be used for control and carry out described inquiry idle task;
Whether described inquiry almost expires task module 126, is used for the described inquiry of control execution and whether almost expires task.
Further describe with preferred specific embodiment below.Use the Verilog language to design described FIFO simulation unit in this preferred embodiment, do not use the physical connection and the control signal of emulation, but by calling read/write FIFO task and inquiry fifo status task dispatching FIFO functional task as the interface between external module and the FIFO simulation unit, clock system realizes the FIFO function when not required, can improve simulation efficiency.
Concrete, the key word TASK of defined can be used for default described FIFO functional task among the Verilog language standard, when needs read and write data or inquire about fifo status,, be simply described as follows for basic FIFO functional task by calling the corresponding function that corresponding TASK can realize FIFO:
1, reads the FIFO task:, judge earlier whether the FIFO simulation unit is empty, if not empty, sense data (data are exported by outlet parameter) is read cyclic address change then from FIFO simulation unit current address if the FIFO simulation unit is not in reset mode.
Task read_fifo; The statement of // task
Output[7:0] data_out; // outlet parameter
2, write the FIFO task:, judge earlier whether the FIFO simulation unit is full, if discontented, writes data (data are imported by suction parameter) in FIFO simulation unit current address, and write address adds one then if the FIFO simulation unit is not in reset mode.
Task write_fifo; The statement of // task
Input[7:0] data_in; // suction parameter
3, inquiry FIFO idle task whether: the value of the status register whether the FIFO simulation unit is empty is exported by outlet parameter.
Task empty_status; The statement of // task
Output empty_flag; // outlet parameter
4, whether FIFO expires task: the value of the status register whether the FIFO simulation unit is full is exported by outlet parameter.
Task full_status; The statement of // task
Output full_flag; // outlet parameter
5, FIFO idle task whether almost: with the FIFO simulation unit whether almost the value of empty status register export by outlet parameter.
Task alempty_status; The statement of // task
Output alempty_flag; // outlet parameter
6, whether inquiry FIFO almost expires task: the value of the status register whether the FIFO simulation unit is almost full is exported by outlet parameter.
Task alfull_status; The statement of // task
Output alfull_flag; // outlet parameter.
Can realize the various functions of FIFO simulation unit by calling above-mentioned default first in first out functional task, for example finish the function of the empty full indicator signal of traditional F IFO by the respective queries task of calling the empty full state of inquiry FIFO.Finish function from data to FIFO that read or write by calling the read-write task.
Need to prove that the FIFO simulation unit is not limited to default above-mentioned basic FIFO functional task in this preferred embodiment, also can define other task voluntarily according to user's needs.Present embodiment is described with the first in first out simulation unit of Verilog language design in addition, need to prove, FIFO simulation unit of the present invention also can adopt language such as other language such as VHDL to realize, because it is not key point of the present invention that concrete language is realized, no longer is described in detail here.
In addition, also can insert certain time delay as required between the FIFO functional task calls among the present invention, control FIFO read-write or inquiry velocity are to obtain the highest efficient.
With reference to figure 5, the first in first out simulation unit of the above-mentioned realization of the present invention, can further be applied in the logic checking analogue system, to improve the dirigibility and the simulation efficiency of logic checking analogue system, concrete, the logic checking analogue system that the present invention realizes comprises: emulated data produces authentication unit 21, emulation bus functional mode unit 22, sends first in first out simulation unit 23, receives first in first out simulation unit 24.Wherein
Described emulated data produces authentication unit 21, be used to produce the test case that logic checking emulation is used, and treat the test case that verifying logic handled and verify, to confirm whether logic to be verified is correct, during specific implementation, test case that can be different according to different logic checking Demand Design;
Described emulation bus functional mode unit 22 is used for the specific time sequence that the test case data that described emulated data generation authentication unit 21 produces is arranged with logic to be verified is sent to logic to be verified; Or receive data after the logical process to be verified by specific time sequence with logic to be verified agreement;
Described transmission first in first out simulation unit 23, as the middle buffer memory of the data that transmit between emulated data generation authentication unit 21 and the emulation bus functional mode unit 22, the test case emulation buffer memory that emulated data produces authentication unit 21 generations is sent to emulation bus functional mode unit 22 according to default first in first out functional task;
Described reception first in first out simulation unit 24, as the middle buffer memory of the data that transmit between emulated data generation authentication unit 21 and the emulation bus functional mode unit 22, be used for emulation bus functional mode unit 22 emulated data buffer memorys that receive, after being verified logical process being returned to emulated data generation authentication unit 21 and verify equally according to default first in first out functional task.
According to the invention described above first in first out simulation unit principle, sending first in first out simulation unit 23 described in the logic checking analogue system of the present invention can further comprise: emulation sends buffer storage 231 and emulation transmission control device 232, wherein
Described emulation sends buffer storage 231, is used for the emulated data that the described emulated data of emulation buffer memory produces the first in first out that authentication unit sends, but the empty full state of the described transmission first in first out of buffer memory simulation unit etc. also in addition;
Described emulation transmission control device 232 is used to control and carries out default first in first out functional task, produces the emulated data of the first in first out that authentication unit sends to write or to read described emulated data from described emulation buffer storage.
In addition, described reception first in first out simulation unit 24 can further comprise: emulation receives buffer storage 241 and emulation receiving control device 242, wherein
Described emulation receives buffer storage 241, is used for the emulated data of the first in first out of sending the described bus functional model of emulation buffer memory unit 22, and is the same, but described emulation receives the also full state of sky etc. of the described reception first in first out of buffer memory simulation unit of buffer storage;
Described emulation receiving control device 242 is used to control and carries out default first in first out functional task, to receive the emulated data that buffer storage write or read the first in first out of sending described emulation bus functional mode unit 22 to described emulation.
Same, the above-mentioned first in first out simulation unit design concept according to the present invention, first in first out functional task default described in the logic checking simulation unit of the present invention mainly comprises:
Reading task, if described transmission or reception first in first out simulation unit are not in reset mode, whether at first judge described transmission or receive the first in first out simulation unit is empty, if be not empty, sense data from described transmission or reception first in first out simulation unit current address is read cyclic address change then;
Writing task, whether if described transmission or reception first in first out simulation unit are not in reset mode, judging earlier described transmission or receiving the first in first out simulation unit is full, if for expiring, write data in described transmission or reception first in first out simulation unit current address, write address adds one then;
Whether whether inquire about idle task, inquiring about and export described transmission or receiving the first in first out simulation unit is empty state value;
Whether inquiry expires task, inquires about and exports described transmission or receive whether the first in first out simulation unit is full state value;
Almost whether inquiry idle task, and whether inquire about and export described transmission or receive the first in first out simulation unit is almost empty state value;
Whether inquiry almost expires task, inquires about and exports described transmission or receive whether the first in first out simulation unit is almost full state value;
And described emulation transmission control device 231 and described emulation receiving control device 241 further comprise as lower module:
The reading task module is used for control and carries out described reading task;
The writing task module is used for control and carries out described writing task;
Whether inquire about the idle task module, be used for control and carry out whether idle task of described inquiry;
Whether completely whether inquiry expires task module, be used for control and carry out described inquiry task;
Whether almost almost whether inquiry the idle task module, be used for control and carry out described inquiry idle task;
Whether inquiry almost expires task module, is used for the described inquiry of control execution and whether almost expires task.
Be understood that, also can preset other first in first out functional task according to demand, corresponding also the need is provided with corresponding module at described emulation transmission control device 232 and described emulation receiving control device 242.
Specify described emulation below and send buffer storage 231, sending buffer storage 231 for described emulation among the present invention can further comprise:
Emulation sends data buffer storage unit, and described emulation sends data buffer storage unit and is mainly used in the test case data that the described emulated data of emulation buffer memory produces authentication unit 21 first in first out that send, to be sent;
Emulation transmit status register, described emulation transmit status register are mainly used in the full state of sky that described transmission first in first out simulation unit is stored in emulation.
Same, emulation of the present invention receives buffer storage 241 and can further comprise:
Emulation receives data buffer storage unit, and described emulation receives the emulated data that data buffer storage unit is mainly used in the first in first out 22 that send, that cross through logical process to be verified of the described emulation bus functional mode of emulation buffer memory unit;
Emulation accepting state register, described emulation accepting state register are mainly used in the full state of sky that described reception first in first out simulation unit is stored in emulation.
Above-mentioned concrete composition for transmission first in first out simulation unit and reception first in first out simulation unit can repeat no more here with reference to the narration of aforementioned first in first out simulation unit.
The above-mentioned logic checking analogue system of following simple declaration groundwork principle.
With reference to figure 6, this figure is the process of writing that writes data in the above-mentioned logic checking analogue system to the FIFO simulation unit.Concrete, after emulated data produced authentication unit 21 and produces excited datas, whether calling inquiry FIFO earlier, whether to expire task inquiry FIFO simulation unit full, if full, then wait for the some time after inquiry once more; If discontented, then call writing task data are write the FIFO simulation unit.
With reference to figure 7, this figure is from the read procedure of FIFO simulation unit sense data in the above-mentioned logic checking analogue system.Concrete, when emulation bus functional mode unit need send data, whether whether idle task inquiry FIFO empty to call inquiry FIFO earlier, if empty, then wait for the some time after inquiry once more; If not empty, then call reading task data are read the FIFO simulation unit, send on the bus that is connected with emulation bus functional mode unit.
The present invention need not clock, with task call as with the interface of other module, realize simply, FIFO simulation unit and peripheral modules need not physical connection and control signal, have reduced the simulation work amount greatly; On the other hand, the present invention can be provided with the read or write speed of FIFO simulation unit as required easily, uses flexibly, does not have external physical connection, has improved ease for use and reusability; And,, improved efficient greatly so the present invention's read-write to the FIFO simulation unit in the logic checking analogue system does not take simulation time owing to need not the clock control read-write operation.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (9)
1, a kind of first in first out simulation unit is used for computer logic emulation, comprising:
The emulation buffer storage is used for the emulated data of emulation buffer memory first in first out;
It is characterized in that, also comprise:
The Simulation Control device is used to control and carries out default first in first out functional task, to write or to read the emulated data of first in first out from described emulation buffer storage.
2, first in first out simulation unit according to claim 1 is characterized in that, described default first in first out functional task comprises:
Reading task if described first in first out simulation unit is not in reset mode, judges at first whether described first in first out simulation unit is empty, if be not empty, sense data from described first in first out simulation unit current address is read cyclic address change then;
Writing task if described first in first out simulation unit is not in reset mode, judges earlier whether described first in first out simulation unit is full, if not for full, write data in described first in first out simulation unit current address, write address adds one then;
Whether whether inquire about idle task, inquiring about and export described first in first out simulation unit is empty state value;
Whether inquiry expires task, and whether inquire about and export described first in first out simulation unit is full state value;
Almost whether inquiry idle task, and whether inquire about and export described first in first out simulation unit is almost empty state value;
Whether inquiry almost expires task, and whether inquire about and export described first in first out simulation unit is almost full state value;
Described Simulation Control device comprises:
The reading task module is used for control and carries out described reading task;
The writing task module is used for control and carries out described writing task;
Whether inquire about the idle task module, be used for control and carry out whether idle task of described inquiry;
Whether completely whether inquiry expires task module, be used for control and carry out described inquiry task;
Whether almost almost whether inquiry the idle task module, be used for control and carry out described inquiry idle task;
Whether inquiry almost expires task module, is used for the described inquiry of control execution and whether almost expires task.
3, first in first out simulation unit according to claim 1 and 2 is characterized in that, described emulation buffer storage comprises:
The emulated data buffer storage is used for the emulated data of emulation buffer memory first in first out;
The simulation status register is used for the full state of sky that described first in first out simulation unit is stored in emulation.
4, a kind of logic checking analogue system comprises:
Emulated data produces authentication unit, is used to produce the test case that logic checking emulation is used, and treats the test case that verifying logic handled and verify whether be verified logic with affirmation correct;
Emulation bus functional mode unit is used for that emulated data is produced test case data that authentication unit produces and sends to logic to be verified with the specific time sequence that is verified logic and is arranged; Or by receiving the data that are verified after the logical process with the specific time sequence that is verified logic agreement;
It is characterized in that, also comprise:
Send the first in first out simulation unit, be used for the test case emulation buffer memory that emulated data produces the authentication unit generation being sent to emulation bus functional mode unit according to default first in first out functional task;
Receive the first in first out simulation unit, be used for emulation bus functional mode unit emulated data buffer memory that receive, after being verified logical process being returned to emulated data generation authentication unit and verify according to default first in first out functional task.
5, logic checking analogue system according to claim 4 is characterized in that, described transmission first in first out simulation unit comprises:
Emulation sends buffer storage, is used for the emulated data that the described emulated data of emulation buffer memory produces the first in first out that authentication unit sends;
The emulation transmission control device is used to control and carries out default first in first out functional task, produces the emulated data of the first in first out that authentication unit sends to write or to read described emulated data from described emulation buffer storage.
6, logic checking analogue system according to claim 4 is characterized in that, described reception first in first out simulation unit comprises:
Emulation receives buffer storage, is used for the emulated data of the first in first out of sending the described bus functional model of emulation buffer memory unit;
The emulation receiving control device is used to control and carries out default first in first out functional task, to receive the emulated data that buffer storage write or read the first in first out of sending described emulation bus functional mode unit to described emulation.
According to claim 5 or 6 described logic checking analogue systems, it is characterized in that 7, described default first in first out functional task comprises:
Reading task, if described transmission or reception first in first out simulation unit are not in reset mode, whether at first judge described transmission or receive the first in first out simulation unit is empty, if be not empty, sense data from described transmission or reception first in first out simulation unit current address is read cyclic address change then;
Writing task, whether if described transmission or reception first in first out simulation unit are not in reset mode, judging earlier described transmission or receiving the first in first out simulation unit is full, if for expiring, write data in described transmission or reception first in first out simulation unit current address, write address adds one then;
Whether whether inquire about idle task, inquiring about and export described transmission or receiving the first in first out simulation unit is empty state value;
Whether inquiry expires task, inquires about and exports described transmission or receive whether the first in first out simulation unit is full state value;
Almost whether inquiry idle task, and whether inquire about and export described transmission or receive the first in first out simulation unit is almost empty state value;
Whether inquiry almost expires task, inquires about and exports described transmission or receive whether the first in first out simulation unit is almost full state value;
Described emulation transmission control device and described emulation receiving control device include:
The reading task module is used for control and carries out described reading task;
The writing task module is used for control and carries out described writing task;
Whether inquire about the idle task module, be used for control and carry out whether idle task of described inquiry;
Whether completely whether inquiry expires task module, be used for control and carry out described inquiry task;
Whether almost almost whether inquiry the idle task module, be used for control and carry out described inquiry idle task;
Whether inquiry almost expires task module, is used for the described inquiry of control execution and whether almost expires task.
8, logic checking analogue system according to claim 7 is characterized in that, described emulation sends buffer storage and comprises:
Emulation sends data buffer storage unit, is used for the described emulated data of emulation buffer memory and produces the test case data of authentication unit first in first out that send, to be sent;
Emulation transmit status register is used for the full state of sky that described transmission first in first out simulation unit is stored in emulation.
9, logic checking analogue system according to claim 7 is characterized in that, described emulation receives buffer storage and comprises:
Emulation receives data buffer storage unit, is used for the emulated data of first in first out that the described emulation bus functional mode of emulation buffer memory unit is sent, that cross through logical process to be verified;
Emulation accepting state register is used for the full state of sky that described reception first in first out simulation unit is stored in emulation.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100889356A CN100365639C (en) | 2004-11-09 | 2004-11-09 | First-in first-out analog unit and logic verification analog system |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100889356A CN100365639C (en) | 2004-11-09 | 2004-11-09 | First-in first-out analog unit and logic verification analog system |
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| CN1773513A true CN1773513A (en) | 2006-05-17 |
| CN100365639C CN100365639C (en) | 2008-01-30 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101303709B (en) * | 2008-06-30 | 2010-06-02 | 北京中星微电子有限公司 | Simulation control method and system for programmable logic device |
| CN102096734A (en) * | 2011-01-26 | 2011-06-15 | 北京中星微电子有限公司 | Method and device for verifying out-of-order transfer of bus |
| CN101887758B (en) * | 2009-05-12 | 2013-01-16 | 北京兆易创新科技有限公司 | Emulation verification method of nonvolatile memory |
| CN111209660A (en) * | 2019-12-31 | 2020-05-29 | 深圳市芯天下技术有限公司 | Nor Flash simulation and verification system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5799169A (en) * | 1995-10-02 | 1998-08-25 | Chromatic Research, Inc. | Emulated registers |
| US5953020A (en) * | 1997-06-30 | 1999-09-14 | Ati Technologies, Inc. | Display FIFO memory management system |
| CN1290016C (en) * | 2002-08-22 | 2006-12-13 | 联发科技股份有限公司 | Device used in internal circuit simulator system and its internal storage access method |
-
2004
- 2004-11-09 CN CNB2004100889356A patent/CN100365639C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101303709B (en) * | 2008-06-30 | 2010-06-02 | 北京中星微电子有限公司 | Simulation control method and system for programmable logic device |
| CN101887758B (en) * | 2009-05-12 | 2013-01-16 | 北京兆易创新科技有限公司 | Emulation verification method of nonvolatile memory |
| CN102096734A (en) * | 2011-01-26 | 2011-06-15 | 北京中星微电子有限公司 | Method and device for verifying out-of-order transfer of bus |
| CN111209660A (en) * | 2019-12-31 | 2020-05-29 | 深圳市芯天下技术有限公司 | Nor Flash simulation and verification system |
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| Publication number | Publication date |
|---|---|
| CN100365639C (en) | 2008-01-30 |
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