CN1763727A - Processor memory access method and access apparatus thereof - Google Patents
Processor memory access method and access apparatus thereof Download PDFInfo
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- CN1763727A CN1763727A CN 200410085783 CN200410085783A CN1763727A CN 1763727 A CN1763727 A CN 1763727A CN 200410085783 CN200410085783 CN 200410085783 CN 200410085783 A CN200410085783 A CN 200410085783A CN 1763727 A CN1763727 A CN 1763727A
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Abstract
The invention discloses a processor internal storage access method and device, which comprises the steps: utilizing a switching mechanism to access different storage units of internal processor simultaneously through the disposal unit of processor in direct connection with the processor controller; keeping the disposal unit to access and calculate the data of internal storage, wherein the processor disposal unit connects the access controller directly through a switching circuit coupling the internal storage.
Description
Technical field
The present invention is the internal storage access method and the device thereof of a kind of access method of storage and device thereof, particularly a kind of processor.
Background technology
General processor, especially the flush bonding processor (EmbeddedProcessor) often used of System on Chip/SoC, stand-by period when its execution efficient often is subject to access external memory storage (External Memory), that is processor is when the access external memory storage, and the calculation function of processor can be idle state.
As shown in Figure 1, for improving the execution efficient of processor, processor 8 can built-in cache memory 10 with the expedited data access.As shown in Figure 1, processor 8 comprises a processing unit 40, its data with frequent access are deposited a in cache memory (Cache Memory) 10 in addition, so in the time of need using the data of those frequent accesses as if processing unit 40, just can carry out access to cache memory 10, and because processing unit 40 need be by the data of external bus 34 to external memory storage 20 those frequent accesses of access, relatively relatively only need by internal bus 32 access cache 10, so can save the time of data access, therefore processor 8 bulk treatment speed can be fast a lot, but when the data of desiring speed buffering are lost, when speed buffering loss (cache-miss) promptly takes place, processing unit 40 still needs to carry out access by external bus 34 to external memory storage 20, and wherein internal bus 32 must be undertaken by a bus controller 30 with the coordinate operation of external bus 34.
Please refer to Fig. 2, for solving the problem that above-mentioned speed buffering is lost, the conventional practice is for to be appointed as processor 8 internal storages 12 with a certain section addressing space (Address range), internal storage 12 is called Scratchpad Memory (SPM) or Tightly Coupled Memory (TCM) again), processing unit 40 is in the access of this section addressing space, all be by this internal storage 12 of internal bus 32 accesses, rather than via external bus 34 access external memory storages 20, and because internal storage 12 is similar with cache memory 10, but do not need special processing (this is stored as utilizing the speed buffering algorithm to decide what batch data) just can store bulk data, therefore need not worry the problem that speed buffering is lost.Yet, because processor 8 data processed still need write back external memory storage 20 mostly, and processor 8 still needs to read into new data from external memory storage 20 and handles, so in the time of this section read-write external memory storage 20, processing unit 40 is in idle state, therefore causes the waste of calculation resources.
In view of this, the present invention proposes a kind of processor internal storage access method and device thereof, with effective problem that solves routine.
Summary of the invention
When one of purpose of the present invention is to solve conventional access external memory storage, the problem that the processor calculating function is idle.
One of purpose of the present invention is to utilize direct memory access (DMA) controller access data between inside and external memory storage, makes processor can continue the data of access union internal storage.
One of purpose of the present invention is to utilize exchanging mechanism, makes processor and direct memory access (DMA) controller access simultaneously one internal storage.
According to the present invention, a kind of internal storage access method of processor comprises the following step: an exchanging mechanism is provided, an one direct memory access controller and a processing unit are coupled via this exchanging mechanism and an internal storage respectively, and wherein this internal storage comprises one first internal storage unit and one second internal storage unit; When this exchanging mechanism operates on first state, the direct memory access (DMA) controller moves to an external memory storage with the data of first internal storage unit, and the data of this external memory storage are moved into this first internal storage unit, processing unit reads the data of second internal storage unit and is handled at this moment, and the data of handling are deposited back second internal storage unit; And operate on second state when this exchanging mechanism, the direct memory access (DMA) controller moves to external memory storage with the data of second internal storage unit, and the data of this external memory storage are moved into this second internal storage unit, processing unit reads the data of first internal storage unit and is handled at this moment, and the data of handling are deposited back first internal storage unit.
The present invention also discloses a kind of internal storage access device of processor, this device comprises: a processor, it comprises one first internal storage unit, one second internal storage unit, switches a circuit and a processing unit, and this handles the unit and is coupled respectively to first and second internal storage unit by commutation circuit; An and direct memory access controller, it is coupled to first and second internal storage unit via commutation circuit, when direct memory access (DMA) controller during via commutation circuit access first internal storage unit, processing unit can be via this second internal storage unit of commutation circuit access, and work as the direct memory access (DMA) controller by commutation circuit access second internal storage unit, processing unit can be via commutation circuit access first internal storage unit.
Description of drawings
Fig. 1 is the conventional system construction drawing that carries out data access by cache memory.
Fig. 2 is the conventional system construction drawing that carries out data access by cache memory and internal storage.
Fig. 3 carries out the system construction drawing of data access by the direct memory access (DMA) controller for the present invention.
Fig. 4 is an embodiment synoptic diagram of internal storage of the present invention.
Fig. 5 carries out the synoptic diagram of data access for the present invention utilizes the commissure switch.
Fig. 6 compares synoptic diagram for the data access efficiency of the present invention and routine techniques.
The reference numeral explanation
8 processors
10 cache memories
12 internal storages
14 internal storages
16 processors
20 external memory storages
22 direct memory access (DMA) controllers
30 bus controllers
32 internal buss
34 external buss
40 processing units
50 main ends ' MA '
52 from end ' SB '
54 main ends ' MB '
56 from end ' SA '
58 commissure switches
Embodiment
Please refer to Fig. 3, it is an embodiment synoptic diagram of apparatus of the present invention, as seen from the figure, device of the present invention comprises a processor 16, it includes a processing unit 40, it is coupled to a cache memory 10, an internal storage 14, reaches a bus controller 30 by an internal bus 32, and other has a direct memory access controller 22 to be coupled to this internal storage 14, and is coupled to this bus controller 30 and an external memory storage 20 via an external bus 34.
As shown in Figure 4, it is an embodiment synoptic diagram of the internal storage 14 of Fig. 3, as seen from the figure, internal storage 14 comprises one first internal storage unit M0, one second internal storage unit M1 and one and switches circuit, and wherein commutation circuit can be according to selecting signal sel 0 or 1 to select the circuit turn-on path.
Please refer to Fig. 3 and Fig. 4, this processing unit 40 is via internal bus 32 and commutation circuit, be coupled to first and second internal storage unit M0, M1 respectively, and this direct memory access (DMA) controller 22 also is coupled to first and second internal storage unit M0, M1 respectively by commutation circuit, therefore when selecting signal sel to be 0, direct memory access (DMA) controller 22 can be via the data of this second internal storage unit of commutation circuit access M1, and processing unit 40 is then via the data of this first internal storage unit of commutation circuit access M0; In like manner, when selecting signal sel to be 1, direct memory access (DMA) controller 22 can be via the data of this first internal storage unit of commutation circuit access M0, and processing unit 40 is then via the data of this second internal storage unit of commutation circuit access M1.
From the above, processing unit and direct memory access (DMA) controller can be by the runnings of commutation circuit, the different storage unit of the internal storage of access simultaneously, and the direct memory access (DMA) controller is the data with the first/the second internal storage unit, be sent to this external memory storage by external bus, and the data of external memory storage are sent to the first/the second internal storage unit by external bus, at the same time, processing unit then can read the data of the second/the first internal storage unit, and the data of handling is returned deposit to the second/the first internal storage unit.Therefore, the direct memory access (DMA) controller can be specialized in the transmission of data between external memory storage and internal storage, and the data of the then sustainable processing internal storage of processing unit are to give full play to operation efficiency.
Method of the present invention comprises the following steps: to provide exchange (bank swapping) mechanism, make a processing unit and a direct memory access controller be coupled to an internal storage by this exchanging mechanism respectively, wherein this internal storage comprises one first internal storage unit and one second internal storage unit; When this exchanging mechanism operates on first state, this direct memory access (DMA) controller is sent to an external memory storage with the data of first internal storage unit, and the data of external memory storage are moved into first internal storage unit, at this moment, this processing unit reads the data of second internal storage unit and is handled, and the data of handling are deposited back second internal storage unit; And when this exchanging mechanism operates at second state, this direct memory access (DMA) controller is sent to external memory storage with the data of second internal storage unit, and the data of external memory storage are moved into second internal storage unit, simultaneously, this processing unit reads the data of first internal storage unit and is handled, and the data of handling are deposited back first internal storage unit.
Above-mentioned exchanging mechanism can be realized by a commissure switch (Crossbar Switch Interconnection), the running of commissure switch mainly is when having two main end (MASTER) (as processing unit and direct memory access (DMA) controllers) to need to use bus transfer data simultaneously, as long as this two main end be not act on same from end (SLAVE) (as first or second internal storage unit), then can there be two buses to act on simultaneously, so that parallel processing to be provided by the commissure switch.As shown in Figure 5, when main end ' MA ' 50 corresponds to from end ' SB ' 52, and main end ' MB ' 54 corresponds to from end ' SA ' 56, because of two main end ' MA ' 50 that require to use bus, ' MB ' 54 do not use same from end, so two main end ' MA ' 50, ' MB ' 54 can be simultaneously corresponding with it from end ' SB ' 52, ' SA ' 56 connects, yet, if main end ' MA ' 50 and main end ' MB ' 54 are selected samely to connect from end, then by the higher main end of right of priority be connected from end to transmit data, the main end that right of priority is lower is connected to from end to carry out data transmission after waiting for that then previous main end transmission is finished again.
According to the above, method of the present invention is to utilize the running of exchanging mechanism, make the direct memory access (DMA) controller can specialize in the transmission of data between external memory storage and internal storage, the data of the then sustainable processing internal storage of processing unit are to give full play to operation efficiency.
Please refer to Fig. 6, it is the data access efficiency comparison synoptic diagram of the present invention and routine techniques, suppose to have numbering 0,1,2,3,4... block, do not have in routine under the situation of direct memory access (DMA) controller, no matter have or not cache memory or internal storage, processor all needs to be written into data earlier before handling each block, storage data again after the processing, these are written into, actions such as processing and storage must be carried out in proper order, can't be synchronous, but have in the present invention under the situation of direct memory access (DMA) controller and exchanging mechanism, the direct memory access (DMA) controller be responsible for actual figure refuse to take a passenger into store, exchanging mechanism is then avoided processor and the same internal storage unit of direct memory access (DMA) controller access simultaneously, therefore, the sustainable processing data blocks of processor, as shown in Figure 6, and under ideal state, processor can calculate always and (calculate 0, calculate 1, calculate 2...), need not wait pending data to be written into and to store,, avoid the idle of processor so the present invention can effectively carry out the access of data.
In addition, among the present invention, first and second internal storage unit has identical storage address, therefore for processing unit and direct memory access (DMA) controller, first and second internal storage unit is identical storage unit, so as long as by exchanging mechanism of the present invention, processing unit or direct memory access (DMA) controller need not otherwise designed, can distinguish first and second internal storage unit of access.
The above person only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.
Claims (10)
1. the internal storage access method of a processor, it can be for the processing unit and memory access controller access simultaneously one internal storage of a processor, and wherein this internal storage comprises at least two internal storage units, and this method comprises:
One exchanging mechanism is provided, makes this processing unit and this direct memory access (DMA) controller be coupled to this internal storage by this exchanging mechanism; And
Utilize the running of this exchanging mechanism, make this direct memory access (DMA) controller and different these internal storage units of this processing unit access simultaneously.
2. the method for claim 1, wherein this internal storage is ScratchpadMemiry (SPM) or Tightly Coupled Memory (TCM).
3. the method for claim 1, wherein the pairing storage address of this two internal storage unit is identical.
4. the method for claim 1, wherein this exchanging mechanism is a commissure switch, and this two internal storage unit is respectively one first internal storage unit and one second internal storage unit.
5. method as claimed in claim 4, wherein this commissure switch can switch between one first state and one second state, when this commissure switch is in this first state, this this first internal storage unit of direct memory access (DMA) controller access, this second internal storage unit of this processing unit access this moment, and when this commissure switch is in this second state, this this second internal storage unit of direct memory access (DMA) controller access, this first internal storage unit of this processing unit access this moment.
6. method as claimed in claim 4, wherein utilize the step of the running of this exchanging mechanism further to comprise:
Utilize this commissure switch between one first state and one second state, to switch;
When this commissure switch operated on this first state, this direct memory access (DMA) controller carried out data and transmits between this first internal storage unit and an external memory storage, at this moment the data of this this second internal storage unit of processing unit access; And
When this commissure switch operated on this second state, this direct memory access (DMA) controller carried out data and transmits between this second internal storage unit and this external memory storage, at this moment the data of this this first internal storage unit of processing unit access.
7. the internal storage access device of a processor, this device comprises:
One internal storage, it comprises:
At least one first internal storage unit;
At least one second internal storage unit;
One switches circuit, and it is coupled respectively to this first and second internal storage unit;
One processing unit, it is coupled respectively to this first and second internal storage unit via this commutation circuit; And
One direct memory access controller, it is coupled respectively to this first and second internal storage unit via this commutation circuit, when this this first internal storage unit of direct memory access (DMA) controller access, this second internal storage unit of this processing unit access, when this this second internal storage unit of direct memory access (DMA) controller access, this first internal storage unit of this processing unit access.
8. device as claimed in claim 7, wherein this commutation circuit comprises a commissure switch, this commissure switch can switch between one first state and one second state, when this commissure switch is in this first state, this this first internal storage unit of direct memory access (DMA) controller access, when this commissure switch is in this second state, this this second internal storage unit of direct memory access (DMA) controller access.
9. device as claimed in claim 7, wherein the pairing storage address of this first internal storage unit is identical with the pairing storage address of this second internal storage unit.
10. device as claimed in claim 7, wherein this internal storage is ScratchpadMemory (SPM) or Tightly Coupled Memory (TCM).
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200410085783 CN1763727A (en) | 2004-10-22 | 2004-10-22 | Processor memory access method and access apparatus thereof |
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|---|---|---|---|
| CN 200410085783 CN1763727A (en) | 2004-10-22 | 2004-10-22 | Processor memory access method and access apparatus thereof |
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| CN1763727A true CN1763727A (en) | 2006-04-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017084415A1 (en) * | 2015-11-17 | 2017-05-26 | 深圳市中兴微电子技术有限公司 | Memory switching method, device, and computer storage medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017084415A1 (en) * | 2015-11-17 | 2017-05-26 | 深圳市中兴微电子技术有限公司 | Memory switching method, device, and computer storage medium |
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