CN1756092A - Add-compare-select device and method for computing progressive path metric value - Google Patents
Add-compare-select device and method for computing progressive path metric value Download PDFInfo
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Abstract
The invention discloses an addition-comparison-selection device for calculating the accumulated path metrical values and its relative method. Wherein, inside said addition-comparison-selection device, the encoding limited length of present used convolutional code is decreased with a addition-comparison-selection unit while a register unit is serially connected between each two addition-comparison-selection units; the first serially connected addition-comparison-selection unit calculates the accumulated path metrical values in one time and two conditions selected from grid chart, and the calculated value will be directly transmitted to the nearby next addition-comparison-selection unit while another accumulated path metrical value is stored via each register unit to be transmitted to said near-by next addition-comparison-selection unit; and the near-by next addition-comparison-selection unit will calculate the accumulated path metrical value in next time and two conditions of grid chart according to received two accumulated path metrical values. The invention can markedly improve the executing speed for calculating the accumulated path metrical value of every condition with less consumption of resource, to improve the decoding speed of Viterbi decoder.
Description
Technical field
The present invention relates to the decoding technique in the mobile communication system, particularly relate to a kind of the adding of the path metric value that adds up of in the decode procedure of viterbi decoder, calculating than screening device and method.
Background technology
Convolutional encoding be 3-G (Generation Three mobile communication system) a kind of channel coding method of generally adopting, be applicable to business, such as voice service than low rate.The pairing decoding algorithm of convolutional encoding is a lot, and wherein effective and the most practical decoding algorithm is a maximum-likelihood decoding, i.e. Viterbi decoding algorithm.
Fig. 1 is a kind of grid map that uses in the Viterbi decoding process, and Fig. 2 is the basic flow sheet of Viterbi decoding algorithm.Referring to Fig. 1 and Fig. 2, the basic process of Viterbi decoding algorithm may further comprise the steps:
Step 201: in grid map, (i j), distinguishes calculating path branched measurement value bm (y, b (i, j)) to each branch road b of each state Sj of time t+1 for each state Si from time t.
Here, the data of y for deciphering at time t.
Step 202: to each branch road b (i, j), respectively with add up path metric value and each path branches metric bm (i, j) addition of each state Si survivor path of time t.
Step 203: under each state of each state Sj of time t+1, each branch road of this state-transition of subtend, with obtain in the step 202 and compare, selection provides and is worth the survivor path and the branch road b (i of minimum state Si, j) group is organized the survivor path of path as state Sj with this that select.
Step 204: the path metric value that adds up that calculates the survivor path of Sj.
Here, the path metric value that adds up of Sj survivor path equals: add up path metric value and branch road b (i, path branches metric sum j) of survivor path in step 203 routing path, state Si.
Like this, all only there is a unique paths during as destination node with any one state.
Step 205: under each state of each state Sj of time t+1, resulting corresponding survivor path information stores is got up.
Step 206: to each time, all execution in step 201 is to the process of step 205, until the pairing time of final data that should decipher, pursues the survivor path information of being stored along the time, traces back to the initial time always, obtains decode results.
Along with the fast development of business, the decoding speed of viterbi decoder is had higher requirement.Such as, at TD SDMA (TD-SCDMA, Time Division-SynchronizationCode Division Multiple Access) in the system, because its core technology smart antenna and associated detection technique can bring big gain to system, therefore, convolutional encoding can be applied to this kind business very high to rate requirement, and correspondingly, the interpretation method of viterbi decoder then must have higher decoding speed.
Fig. 3 is the structural representation of viterbi decoder.Referring to Fig. 3, in viterbi decoder, add that (ACS, Add-Compare-Select) module is finished the core procedure of above-mentioned Viterbi decoding algorithm, i.e. the add up process of path metric value of each state the computation grid figure from step 202 to step 204 than choosing.Therefore, a key factor that improves the viterbi decoder decoding speed is to improve to add than the add up execution speed of path metric value of each state among the modeling piece computation grid figure.
For raising adds than the add up execution speed of path metric value of each state among the modeling piece computation grid figure, finally reach the purpose that improves the viterbi decoder decoding speed, prior art is adding than the inner computing structure that adopts parallel pipeline of modeling piece, be about to a plurality of acs unit parallel connections, each acs unit calculates at the different conditions of inscribing the time in the grid map simultaneously.
Such as, when adopting two parallel pipelines, prior art is adding than modeling piece inside, and by the acs unit of two parallel connections is finished twice addition, comparison, selection simultaneously and stored operation result in a clock cycle operation, two butterfly diagram computings in the grid map have been finished in this operation.Like this, finishing a step constraint length is 9 to be that status number is 2
9-1The decoding time of=256 addition, comparison and selection operation, need 66 clock cycle, support at viterbi decoder under the work clock of 20MHz, the decoding speed of viterbi decoder be 1/ (66 * 1/20M)=300Kbps, not ideal enough to the increase rate of the decoding speed of viterbi decoder.
This shows that prior art is this comes the add up method of path metric value of each state among the computation grid figure to have following shortcoming by parallel pipeline:
1, each bar pipeline parallel method work can't be shared the interconnection resource of viterbi decoder inside and the storage resources of special register, thereby cause the waste of resource between the streamline, has increased the cost of system.
Though 2, prior art has adopted parallel pipeline to calculate the pairing path metric value that adds up of various states simultaneously, but this executive mode is also just after the path metric value that adds up of all state correspondences of the moment has all calculated, just begin to calculate the next pairing path metric value that adds up of each state constantly, make this method have bigger time delay when each state adds up path metric value in computation grid figure, thereby reduced the decoding speed of viterbi decoder.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of calculating to add up adding than screening device of path metric value,
Another object of the present invention is to provide a kind of calculating method of path metric value that adds up, under taking the situation of less resource, improve the add up execution speed of path metric value of each state among the computation grid figure greatly.
In order to achieve the above object, technical scheme of the present invention is achieved in that
A kind of calculating adds up adding than screening device of path metric value, and this device comprises that the convolution coding limited length of current use subtracts an acs unit, is connected in series successively by two data lines between adjacent two acs units; Be connected in series two register cells successively on every data lines between per two acs units except that latter two acs unit, register cell of serial connection on the every data lines between latter two acs unit;
The previous acs unit that is connected in series is used for calculating the path metric value that adds up of following two states of grid map synchronization of current use, and the path metric value that adds up that will calculate directly transfers to an adjacent back acs unit, another path metric value that adds up by after the register cell between the back acs unit adjacent with self storage, is transferred to this adjacent back acs unit.
The add up method of path metric value of a kind of calculating, be applied in the Viterbi decoding process, add than screening device at viterbi decoder, the convolution coding limited length of current use is subtracted an acs unit to be connected in series successively, and between per two acs units serial register unit successively, this method is further comprising the steps of:
Two states inscribing when an acs unit of A, serial connection is chosen one from the grid map of current use calculate the pairing path metric value that adds up of these two states;
B, this acs unit are in two path metric values that add up that calculate, one of them path metric value that adds up is directly transferred to an adjacent back acs unit, and after another path metric value that adds up stored by self and the register cell between the adjacent back acs unit, transfer to this adjacent back acs unit;
C, this adjacent back acs unit calculate next pairing path metric value that adds up of two states constantly in the described grid map according to two path metric values that add up that receive;
D, repeated execution of steps A are to step C, the path metric value that adds up of all state correspondences under the last moment in having calculated described grid map.
This method further comprises: put in order for the grid map that uses in the Viterbi decoding process, the first row state value of inscribing in first o'clock is arranged in order, each row state for the follow-up moment, begin with state zero, at first be arranged in order even states from top to bottom, and differ (columns value-1) power of 2 between per two even states, and then with state at the beginning, at first be arranged in order odd states from top to bottom, and differ (columns value-1) power of 2 between per two odd states;
In steps A, the step that described acs unit is chosen two states is: this acs unit is chosen steps A and is inscribed when described and can transfer to next two state of same state constantly in the grid map of current use.
The step of the pairing path metric value that adds up of described computing mode is: the path metric value that adds up that will transfer to the previous state of this state adds the path branches metric of this previous state, with gained and value as the pairing path metric value that adds up of this state.
Described each acs unit is serially connected successively by two data lines;
Described between per two acs units successively the step of serial register unit be: on the every data lines between per two acs units except that latter two acs unit, be connected in series two register cells respectively, in the end be connected in series a register cell respectively on the every data lines between two acs units.
The step that is connected in series two register cells on described every data lines between per two acs units except that latter two acs unit respectively further comprises: between any two the adjacent acs units except that latter two acs unit, with two register cells on the data lines in the past backward as first register cell and second register cell, with two register cells on another data lines in the past backward as the 3rd register cell and the 4th register cell;
Described step B specifically comprises:
B11, described acs unit directly transfer to a described adjacent back acs unit with the path metric value that adds up that calculates in the steps A;
B12, for described acs unit after each register cell of being connected in series, from first register cell to the, the four register cells storage operation that is shifted successively, and exporting the path metric value that adds up that the 4th register cell is shifted out to a described adjacent back acs unit, the path metric value that then another that calculates in the steps A added up is stored in first register cell;
Wherein, a described acs unit and a described adjacent back acs unit are not latter two acs units.
In step B12, describedly comprise from be shifted the successively step of storage operation of first register cell to the, four register cells:
B121, the path metric value of storing in described the 4th register cell that adds up is shifted out;
B122, the path metric value of storing in described the 3rd register cell that adds up transferred in described the 4th register cell store;
B123, the path metric value of storing in described second register cell that adds up transferred in described the 3rd register cell store;
B124, the path metric value of storing in described first register cell that adds up transferred in described second register cell store.
The step that is connected in series a register cell on every data lines between described two acs units in the end respectively further comprises: in the end between two acs units, with the register cell on the data lines as at preceding register cell, with the register cell on another data lines as in the late register unit;
Described step B specifically comprises:
B21, described acs unit directly transfer to a described adjacent back acs unit with the path metric value that adds up that calculates in the steps A;
B22, for described acs unit after each register cell of being connected in series, the path metric value that adds up that will store in the late register unit exports a described adjacent back acs unit to;
B23, the path metric value that adds up that will store in preceding register cell transfer in the late register unit and store;
B24, another that calculates in the steps A path metric value that adds up is stored in preceding register cell;
Wherein, a described acs unit and a described adjacent back acs unit are latter two acs unit.
As seen, apparatus and method of the present invention have the following advantages:
1, add than screening device of the present invention, a plurality of acs units are serially connected, make each acs unit can share the interconnection resource of viterbi decoder inside and the storage resources of register cell, thereby saved the resource of system greatly, reduced the cost of system.
2, in the present invention, the pairing path metric value that adds up of state that the acs unit of a plurality of serial connections is inscribed when different among the computation grid figure simultaneously, promptly acs unit inscribes in computation grid figure that state is pairing to add up during path metric value one the time, other acs unit is next pairing path metric value that adds up of state constantly among the computation grid figure simultaneously, reduced arithmetic time delay, improve among the computation grid figure each state execution speed of path metric value that adds up greatly, thereby improved the decoding speed of viterbi decoder.
Description of drawings
Fig. 1 is a kind of grid map that uses in the Viterbi decoding process.
Fig. 2 is the basic flow sheet of Viterbi decoding algorithm.
Fig. 3 is the structural representation of viterbi decoder.
Fig. 4 is the structural representation that adds in an embodiment of the present invention than screening device.
Fig. 5 is the schematic diagram of the grid map that uses in an embodiment of the present invention.
Fig. 6 is the flow chart of the embodiment of the invention.
Fig. 7 A adds than inner each register cell of screening device in embodiments of the present invention at T2 storage schematic diagram constantly.
Fig. 7 B adds than inner each register cell of screening device in embodiments of the present invention at T3 storage schematic diagram constantly.
Fig. 7 C adds than inner each register cell of screening device in embodiments of the present invention at T4 storage schematic diagram constantly.
Fig. 7 D adds than inner each register cell of screening device in embodiments of the present invention at T5 storage schematic diagram constantly.
Fig. 7 E adds than inner each register cell of screening device in embodiments of the present invention at T6 storage schematic diagram constantly.
Fig. 7 F adds than inner each register cell of screening device in embodiments of the present invention at T7 storage schematic diagram constantly.
Fig. 7 G adds than inner each register cell of screening device in embodiments of the present invention at T8 storage schematic diagram constantly.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with drawings and the specific embodiments.
In order to improve the add up execution speed of path metric value of each state among the computation grid figure, prior art is adding the structure that has adopted parallel pipeline than modeling piece inside, promptly adding than modeling piece inside, and this kind practice can cause the waste of resource a plurality of acs unit parallel connections.Therefore, the present invention proposes brand-new the adding of a kind of structure and compare screening device.Add than screening device of the present invention, use two data lines that a plurality of acs units are connected in series, and on the every data lines between per two acs units except that latter two acs unit two register cells of serial connection, here, two register cells of serial connection are in order to realize the displacement storage on every data lines, and register cell of serial connection on the every transmission line between two acs units in the end, make the acs unit of each serial connection can share the storage resources of interconnection resource and register cell, thereby realize taking the purpose of less resource.
Because employed grid map exists 2 in the Viterbi decoding process
nIndividual state, wherein natural number n equals the limited length-1 of current volume level sign indicating number coding, so as can be known, natural number n has determined the number of state in the grid map.Therefore, for corresponding with the status number that occurs in the decode procedure, in the present invention, with the natural number n of state number in this decision grid map, as in the number that adds the acs unit that should be connected in series than screening device inside.Such as, if comprise 8 states in the grid map that in the Viterbi decoding process, uses, then because 2
3=8, promptly described natural number n=3, so, of the present invention adding than three acs units of the inner serial connection of screening device.If comprise 256 states in the grid map that in the Viterbi decoding process, uses, then because 2
8=256, promptly described natural number n=8, so, of the present invention adding than 8 acs units of the inner serial connection of screening device.
In the prior art, in the grid map each the time inscribe each state all according to from small to large sequence arrangement, in decode procedure, after can only all having calculated at the metric that adds up of all state correspondences of the moment, could begin to calculate the next metric that adds up of each state correspondence constantly, thereby cause decoding delay.In order to address this problem, the present invention at first puts in order the grid map that uses in the decode procedure, with in the grid map each the time inscribe state order rearrange, it is arranged principle and is: at first row under 0 constantly, according to each state of original sequence arrangement; To each row state in the follow-up moment,, be arranged in order even states from top to bottom, and differ (columns value-1) power of 2 between per two even states with state 0 beginning; After the even states arrangement finishes,, be arranged in order odd states from top to bottom, and also differ (columns value-1) power of 2 between per two odd states from top to bottom with state 1 beginning.
Next, according to reflected in the grid map of arrangement back different the time inscribe add up correlation between the path metric value of each state, promptly state can transfer to next the time state inscribed, calculate simultaneously and inscribe the path metric value that adds up of state when different, thereby reduce calculation delay.Here, the said path metric value that adds up that calculates the state of inscribing when different simultaneously is meant, as long as one acs unit calculated inscribes in the pairing path metric value that adds up of state one the time, have that the state of inscribing when can be used for calculating next is pairing to add up during path metric value, other acs unit of serial connection then calculates immediately and inscribes the pairing path metric value that adds up of state this next the time.
Utilize the present invention to add acs unit than inner each serial connection of screening device below in conjunction with the explanation of specific embodiment, the state of inscribing when a plurality of according to the grid map after the arrangement calculates the process of its path metric value that adds up simultaneously.In the present embodiment, the limited length of the convolutional encoding of current use is 9, promptly in the Viterbi decoding process, comprises 8 states in the grid map of use, promptly 2
3Individual state.
Fig. 4 is the structural representation that adds in an embodiment of the present invention than screening device.Referring to Fig. 4, owing to comprise 2 in the grid map
3Individual state, so add than screening device at present embodiment, three acs units are serially connected by two data lines, two register cells of serial connection on every data lines between preceding two acs units, register cell of serial connection on every data lines between latter two acs unit, here need to prove that in Fig. 4, r1 represents a register cell respectively to r6.
Fig. 5 is the schematic diagram of the grid map that uses in an embodiment of the present invention.In Fig. 5,8 states are 0 to 7, each the time sequence of states of inscribing rearrange according to arrangement principle of the present invention, the grid map after arrangement can find the path metric value that adds up of state under its required previous moment of the path metric value that adds up of the state of inscribing when calculating fast.Such as, from the arrangement after grid map as can be seen, calculate the adding up during path metric value of 3 times states 0 constantly, only need use the path metric value that adds up of the moment 2 times states 0 and state 4, and need not constantly the path metric value that adds up of 2 times other states such as state 6 and state 7, according to this rule, the adding up during path metric value of 2 times states 0 and state 4 can calculated constantly, calculate the path metric value that adds up of 3 times states 0 constantly immediately, and need not by the time to have calculated the path metric value that adds up of 2 times all states constantly.
Fig. 6 is the flow chart of the embodiment of the invention.In flow chart shown in Figure 6, for ease of describing, (j i) represents the add up path metric value of state j at moment i, and (k) expression state j is at the path branches metric of moment i corresponding to input k (0/1) for j, i for symbol B to use symbol L.Referring to Fig. 4, Fig. 5 and Fig. 6, utilize of the present invention adding to calculate the add up detailed process of path metric value of the state of inscribing when a plurality of simultaneously than screening device and may further comprise the steps:
Step 601:ACS1 reads in L (0,1), B (0,1 constantly at the T1 of an execution cycle, 0), B (0,1,1) and L (4,1), B (4,1,0), B (4,1,1), calculates, obtain L (0,2) and L (1,2) as a result, then at T2 constantly with L (0,2) and L (1,2) deposit r3 and r1 respectively in as a result.
Here, at T2 constantly, adding can be referring to Fig. 7 A than the storage condition of inner each register cell of screening device.
Step 602:ACS1 reads in L (1,1), B (1,1,0), B (1 constantly at T2,1,1) and L (5,1), B (5,1,0), B (5,1,1), calculate, obtain L (2,2) and L (3,2) as a result, and constantly value L among former r3 and the r1 (0,2) and L (1,2) are stored in r4, r2 respectively at T3, L (2,2) and L (3,2) deposit r3 and r1 respectively in as a result with gained.
Here, at T3 constantly, adding can be referring to Fig. 7 B than the storage condition of inner each register cell of screening device.
Step 603:ACS 1 reads in L (2,1), B (2,1,0), B (2 constantly at T3,1,1) and L (6,1), B (6,1,0), B (6,1,1), calculate, get L (4,2) and L (5,2) as a result, and at T4 constantly, L among the r4 (0,2) is exported to ACS2, deposit the value of r3 in r4, deposit the value of r2 in r3, deposit the value of r1 in r2, with gained as a result L (5,2) deposit r1 in.
Here, at T4 constantly, adding can be referring to Fig. 7 C than the storage condition of inner each register cell of screening device.
Step 604:ACS2 reads among the r4 L (4,2) of ACS1 generation in original L (0,2) that preserves and the step 603 constantly at T4, and reads in B (0,2,0), B (0,2,1) and B (4,2,0), B (4,2,1), calculate, obtain L (0,3) and L (1,3) as a result, and constantly deposit L (0,3) and L (1,3) in r6 and r5 respectively at T5.
Referring to Fig. 5, to carry out here, the path metric value that adds up of the moment 2 times states that present embodiment calculates is L (0,2), L (1,2), L (2,2), L (3,2), L (4,2) and L (5,2), also do not calculate L (6,2) and L (7,2), still, from grid map as can be seen, because the path metric value L (0 that adds up at the moment 3 times states 0 and state 1,3) and L (1,3) only with L (0,2) and L (4,2) relevant, and need not L (6,2) and L (7,2), therefore, in step 604, need not to wait until that the path metric value that adds up of 2 times all states has all calculated constantly, just can directly calculate the path metric value that adds up of 3 times correlation behaviors corresponding constantly with the path metric value that adds up that has calculated for 2 times constantly.
Step 605:ACS1 reads in L (3,1), B (3,1,0), B (3 constantly at T4,1,1) and L (7,1), B (7,1,0), B (7,1,1), calculate, L (6,2) and L (7,2) as a result, and the T5 moment with the L among the r4 (2,2) export to ACS2, deposit the value of r3 in r4, deposit the value of r2 in r3, deposit the value of r1 in r2, with gained as a result L (7,2) deposit r1 in.
Here, at T5 constantly, adding can be referring to Fig. 7 D than the storage condition of inner each register cell of screening device.
Step 606:ACS2 reads in the L (2,2) of original preservation among the r4 and the L (6,2) that ACS1 generates constantly at T5, and B (2,2,0), B (2,2,1) and B (6,2,0), B (6,2,1), calculates, get L (4 as a result, 3) and L (5,3), and at T6 constantly with L (5,3) deposit r5 in, deposit the L among the r5 (1,3) in r6.
Here, at T6 constantly, adding can be referring to Fig. 7 E than the storage condition of inner each register cell of screening device.In Fig. 7 E and subsequent figure, the symbol XXX in the register cell represents not store in this register cell data.
Step 607:ACS2 constantly reads in L (5,2) and L (1,2) among r2 and the r4 and B (1 respectively at T6,2,0), B (1,2,1) and B (5,2,0), B (5,2,1), calculate, get L (2,3) and L (3 as a result, 3), and at T7 constantly with L (2,3) and L (3,3) deposit r6 respectively in, r5 deposits the value among the former r5 in r6 simultaneously.
Step 608:ACS3 constantly reads in L (0,3) and L (4,3) from the result of calculation of r6 and ACS2 respectively at T6, and B (0,3,0), B (0,3,1) and B (4,3,0), B (4,3,1), calculates, obtain L (0,4) and L (1,4) as a result, and export L (0,4) and L (1,4) constantly at T7.
Here, at T7 constantly, adding can be referring to Fig. 7 F than the storage condition of inner each register cell of screening device.
Step 609:ACS2 reads in L (3,2), L (7,2) among r2, the r4 and B (3,2,0), B (3,2 constantly at T7,1) and B (7,2,0), B (7,2,1), calculates, get L (6,3) and L (7,3) as a result, constantly deposit L (7,3) in r5, deposit the value among the former r5 in r6 simultaneously at T8.
Constantly respectively from r6, r5 reads in L (1,3), L (5,3) to step 610:ACS3, and B (1,3,0), B (1,3,1) and B (5,3,0), B (5,3,1), calculates, and exports L (2,4) and L (3,4) constantly at T8 at T7.
Here, at T8 constantly, adding can be referring to Fig. 7 G than the storage condition of inner each register cell of screening device.
Step 611:ACS3 reads in L (2,3) and L (6,3) from r6 and ACS2 output result respectively constantly at T8, and B (2,3,0), B (2,3,1) and B (6,3,0), B (6,3,1), calculates, obtain L (4,4) and L (5,4), and export L (4,4) and L (5,4) constantly at T9.
Step 612:ACS3 constantly reads in L (3,3) and L (7,3) from r6 and r5 respectively at T9, and reads in B (3,3,0), B (3,3,1) and B (7,3,0), B (7,3,1), calculates, and exports L (6,4) and L (7,4) constantly at T10.
By above-mentioned flow process as can be seen, the present invention inscribes simultaneously the pairing path metric value that adds up of state among the computation grid figure when different.Such as, in step 604, ACS2 calculates L (0 constantly at T4,3) and L (1,3), and in step 605, ACS 1 calculates L (6 constantly at T4,2) and L (7,2), promptly at synchronization T4, the present invention has calculated state 6 and the state 7 pairing path metric values that add up under the moment 2 in the grid map simultaneously, and state 0 and the state 1 pairing path metric value that adds up under the moment 3 in the grid map, thereby reduced arithmetic time delay.
According to formula, be input to the time delay between the output below
(individual execution cycle), and the viterbi decoder register cell number that need increase
Wherein n is the limited length of volume level sign indicating number coding, and the decoding speed that viterbi decoder in the present embodiment can reach is described.
In the present embodiment, have 8 states in the grid map, promptly the limited length n of volume level sign indicating number coding is 9, so can get, is input to the time delay between the output
(individual execution cycle) that is to say, calculating 8 next states, to shift the needed time be 101 clock cycle, if decoder uses the work clock of 20MHz, the decoding speed of viterbi decoder equals so
The register cell number that viterbi decoder need increase is
In present employed programming device, can not cause hell and high water and increase by 56 register cells fully.In addition, the decoding speed of viterbi decoder has reached 1.584Mbps, hundreds of Kbps with respect to prior art, the present invention has realized improving greatly the execution speed of path metric value that adds up of each state among the computation grid figure fully under taking the situation of less resource, thereby improves the purpose of viterbi decoder decoding speed.
In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1, a kind of calculating adds up adding than screening device of path metric value, it is characterized in that, this device comprises that the convolution coding limited length of current use subtracts an acs unit, is connected in series successively by two data lines between adjacent two acs units; Be connected in series two register cells successively on every data lines between per two acs units except that latter two acs unit, register cell of serial connection on the every data lines between latter two acs unit;
The previous acs unit that is connected in series is used for calculating the path metric value that adds up of following two states of grid map synchronization of current use, and the path metric value that adds up that will calculate directly transfers to an adjacent back acs unit, another path metric value that adds up by after the register cell between the back acs unit adjacent with self storage, is transferred to this adjacent back acs unit.
2, a kind of calculating method of path metric value that adds up, be applied in the Viterbi decoding process, it is characterized in that, add than screening device at viterbi decoder, the convolution coding limited length of current use is subtracted an acs unit to be connected in series successively, and between per two acs units serial register unit successively, this method is further comprising the steps of:
Two states inscribing when an acs unit of A, serial connection is chosen one from the grid map of current use calculate the pairing path metric value that adds up of these two states;
B, this acs unit are in two path metric values that add up that calculate, one of them path metric value that adds up is directly transferred to an adjacent back acs unit, and after another path metric value that adds up stored by self and the register cell between the adjacent back acs unit, transfer to this adjacent back acs unit;
C, this adjacent back acs unit calculate next pairing path metric value that adds up of two states constantly in the described grid map according to two path metric values that add up that receive;
D, repeated execution of steps A are to step C, the path metric value that adds up of all state correspondences under the last moment in having calculated described grid map.
3, method according to claim 2, it is characterized in that, this method further comprises: put in order for the grid map that uses in the Viterbi decoding process, the first row state value of inscribing in first o'clock is arranged in order, each row state for the follow-up moment, begin with state zero, at first be arranged in order even states from top to bottom, and differ (columns value-1) power of 2 between per two even states, and then at the beginning with state, at first be arranged in order odd states from top to bottom, and differ (columns value-1) power of 2 between per two odd states;
In steps A, the step that described acs unit is chosen two states is: this acs unit is chosen steps A and is inscribed when described and can transfer to next two state of same state constantly in the grid map of current use.
4, method according to claim 2, it is characterized in that, the step of the pairing path metric value that adds up of described computing mode is: the path metric value that adds up that will transfer to the previous state of this state adds the path branches metric of this previous state, with gained and value as the pairing path metric value that adds up of this state.
5, method according to claim 2 is characterized in that, described each acs unit is serially connected successively by two data lines;
Described between per two acs units successively the step of serial register unit be: on the every data lines between per two acs units except that latter two acs unit, be connected in series two register cells respectively, in the end be connected in series a register cell respectively on the every data lines between two acs units.
6, method according to claim 5, it is characterized in that, the step that is connected in series two register cells on described every data lines between per two acs units except that latter two acs unit respectively further comprises: between any two the adjacent acs units except that latter two acs unit, with two register cells on the data lines in the past backward as first register cell and second register cell, with two register cells on another data lines in the past backward as the 3rd register cell and the 4th register cell;
Described step B specifically comprises:
B11, described acs unit directly transfer to a described adjacent back acs unit with the path metric value that adds up that calculates in the steps A;
B12, for described acs unit after each register cell of being connected in series, from first register cell to the, the four register cells storage operation that is shifted successively, and exporting the path metric value that adds up that the 4th register cell is shifted out to a described adjacent back acs unit, the path metric value that then another that calculates in the steps A added up is stored in first register cell;
Wherein, a described acs unit and a described adjacent back acs unit are not latter two acs units.
7, method according to claim 6 is characterized in that, in step B12, describedly comprises from be shifted the successively step of storage operation of first register cell to the, four register cells:
B121, the path metric value of storing in described the 4th register cell that adds up is shifted out;
B122, the path metric value of storing in described the 3rd register cell that adds up transferred in described the 4th register cell store;
B123, the path metric value of storing in described second register cell that adds up transferred in described the 3rd register cell store;
B124, the path metric value of storing in described first register cell that adds up transferred in described second register cell store.
8, method according to claim 5, it is characterized in that, the step that is connected in series a register cell on every data lines between described two acs units in the end respectively further comprises: in the end between two acs units, with the register cell on the data lines as at preceding register cell, with the register cell on another data lines as in the late register unit;
Described step B specifically comprises:
B21, described acs unit directly transfer to a described adjacent back acs unit with the path metric value that adds up that calculates in the steps A;
B22, for described acs unit after each register cell of being connected in series, the path metric value that adds up that will store in the late register unit exports a described adjacent back acs unit to;
B23, the path metric value that adds up that will store in preceding register cell transfer in the late register unit and store;
B24, another that calculates in the steps A path metric value that adds up is stored in preceding register cell;
Wherein, a described acs unit and a described adjacent back acs unit are latter two acs unit.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101494464B (en) * | 2009-03-12 | 2011-10-05 | 华为技术有限公司 | Decoding method, device and electronic equipment |
| CN105589082A (en) * | 2015-12-17 | 2016-05-18 | 湖南中森通信科技有限公司 | Viterbi decoding device and method of Beidou navigation system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5881075A (en) * | 1996-03-18 | 1999-03-09 | Samsung Electronics Co., Ltd. | Viterbi decoder |
| AU5335699A (en) * | 1998-08-04 | 2000-02-28 | Qualcomm Incorporated | Viterbi decoder with reduced size path metric memory |
| CN1159933C (en) * | 2002-05-29 | 2004-07-28 | 信息产业部电信传输研究所 | Universal convolution encoder and viterbi decoder |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101494464B (en) * | 2009-03-12 | 2011-10-05 | 华为技术有限公司 | Decoding method, device and electronic equipment |
| CN105589082A (en) * | 2015-12-17 | 2016-05-18 | 湖南中森通信科技有限公司 | Viterbi decoding device and method of Beidou navigation system |
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