CN1750532A - Embedded general communication board based on signal ML language - Google Patents

Abstract

This invention relates to a communication board for city traffic signal control, which features said communication board is based on extensible marked language to describe signal lamp control information in road cross and adapted to communicate between traffic signal controller and upper position unit of different model, said invention integrating object board and core board and communicating by object board set with CPLD device to control and distribute bus and realize communication between signal apparatus and other bus equipment.

Description

Universal embedded communication board based on the SignalML language

Technical field

Can realize communicating by letter between different manufacturers, dissimilar traffic control signal machine and the host computer based on the universal embedded communication board of SignalML language, and follow a kind of new urban traffic signal control system data exchange standard-SignalML (traffic signals SGML) that is proposed, can be widely used in urban traffic signal control field.

Background technology

Urban traffic signal control system is as an important step of intelligent transportation system, for alleviating urban traffic blocking, ensureing and have a good transport and communication network and safeguard that good traffic order bringing into play very important effect.

Yet, at present the employed communication protocol of urban traffic signal control system of the external comparative maturity of introducing all is specialized protocol, and is externally open, causes carrying out System Expansion and when newly-built, must use the special signal machine of original system, and be not easy to the maintenance of system; Some system communication controlling platform belongs to non-open type simultaneously, secondary system upgrading difficulty.Owing to lack unified data exchange standard, and the agreement barrier of foreign system, not only limited the wide participation of unlike signal machine manufacturer, cause undue dependence to existing equipment manufacturer, can't form a kind of situation of fair competition, and limited fusion between the domestic and international unlike signal control system, be unfavorable for realizing the data sharing between the different control system, improve the integrated level of entire city traffic control system, therefore cause to bring into play the greatest benefit of urban traffic signal control system.

At present, at use the most representative of China and have effective urban traffic signal control system and employed signal controlling machine and communication protocol thereof and mainly contain following several, as follows

Shown in the table 1:

Table 1 traffic signal control system and signal controlling machine, communication protocol summary table

Systematic name	Research institute	Agreement	Lower end equipment
				SCOOT	Britain TRRL	Specialized protocol	Siemens T series of signals machine does not have compatibility to homemade semaphore
SCATS	Australia	Specialized protocol	DELTA series of signals machine does not have compatibility to homemade semaphore
				ITACA	Spain	Specialized protocol	CMY RMY does not have compatibility
Quienet/4	American wheat is agree	California ab3418 is open	170,332 series of signals machines do not have compatibility
				ACTRA	U.S. EAGLE	NTCIP is open	2070

Analysis-by-synthesis, our above as can be seen each traffic control system, center and semaphore all according to system separately specialized protocol carry out the transmission of data and homemade semaphore do not had compatibility, integrate to be difficult for, though the ACTRA system has adopted open NTCIP agreement, but the controlled function of this agreement and system and algorithm are got in touch closely, domestic semaphore is followed its exploitation and is had significant limitation, cost height.In addition, though the manufacturer of domestic semaphore also has much, the semaphore function of producing is few, poor reliability.

Based on above reason, we have designed the universal embedded communication board based on the SignalML language, and it can realize communicating by letter between different manufacturers, dissimilar traffic control signal machine and the host computer.

Here the signal controlling SGML of being mentioned---SignalML language (SignalMarkup Language) be unified describe, packing, storage and the format specification that transmits signal control data, being convenient to different signal controlling machines can carry out the exchange of signal controlling, information easily and share based on this standard.The foundation of SignalML will make signal control data separate with signal controller manufacturer with software platform, make between the dissimilar platforms transfer of data become convenient, in real time.Expandable mark language XML (eXtensible Markup Language) is a kind of DDL standard by the W3C exploitation.The data of describing with XML can be carried out corresponding operation by computer understanding, transmission with according to data content.Such as deal with data, press certain way display message, stored data and to airfield equipment issue control command etc.It allows the user to come own custom-written mark according to different application, as long as defer to identical DTD or SCHEMA between two software systems, just can realize accessible communication.SignalML just is being based on a kind of SGML standard that the XML technology is used for describing signal lamp control crossing control information, provide a kind of method in common to define not only to be convenient to computer interpretation but also made things convenient for " data set " of the signal lamp control crossing that the user understands, be mainly used to describe geometric layout structure, signal controlling type, crossing control, detection, the watch-dog information of crossing, crossing control, detected parameters information, crossing sign, graticule information, the data exchange standard of crossing postitallation evaluation information etc.

Summary of the invention

The objective of the invention is to propose a kind of practicable be specifically designed to can not be compatible traffic signal controlling machine and the universal embedded communication board between the upper computer control system based on the SignalML language, can realize communicating by letter between different manufacturers, dissimilar traffic control signal machine and the host computer, improve the level of integrated system of entire city traffic control system, thus the greatest benefit of performance urban traffic signal control system.

The invention is characterized in: described SignalML is meant the traffic signals SGML, this language is based on a kind of SGML standard that extend markup language is described signal lamp control intersection control information, it makes signal control data separate with signal controller manufacturer with software platform, realize the transfer of data between the different platform, this all purpose communication plate comprises core board and Target Board, and Target Board integrates microprocessor in the core board and the memory that extends out by connector, wherein:

Core board comprises:

ColdFire series microprocessor MCF5272,

The Flash memory, adopt the AM29LV320D chip of 32M position, be operated in the word pattern state, the output enable signal input part of this chip, write enable signal input, address wire, data wire and link to each other with this microprocessor MCF5272 corresponding output end respectively, and the sheet that the input of chip selection signal links to each other with this microprocessor MCF5272 selects the respective end of wire jumper plug-in unit JP2 to link to each other;

The SDRAM memory, adopt the MT48LC4M32B2 chip of 128M position, the clock signal that this chip comprises, clock enable signal, chip selection signal, write enable signal, rank addresses pulse output pin signal, address wire and data wire and link to each other with the respective end of this microprocessor MCF5272 at each interior end;

Bus starting pattern wire jumper connector JP1, link to each other with the corresponding signal end of the formation serial peripheral interface of this microprocessor MCF5272 through eight bus buffer 74LCX541, pattern wire jumper during as bus starting, default configuration are 1,2 to link to each other, and select the 32bits bus transfer;

Clock circuit adopts the outside oscillating circuit chip of OSC 66M, to this microprocessor MCF5272 clock signal;

Reset circuit adopts the MAX708TCSA chip, and when pressing reset button, this chip just provides reset signal to this microprocessor MCF5272;

Target Board comprises:

Embedded TESTMODULE assembly is integrated in microprocessor MCF5272 and the memory that extends out on this module by plug-in unit JP3 and JP4, and be provided with two UART interfaces, Ethernet interface, the BDM interface, the LCD interface, two bus interface, PA interface and functional interface: wherein, the UART interface adopts chip SP3243E, its transmitter input end, the receiver output is connected on respectively on the respective end of UART control unit interface of TESTMODULE assembly, and the output pin of this chip SP3243E, input pin links to each other with the input of RS-232 reflector and the output of receiver respectively, so that microprocessor MCF5272 realizes the communication to semaphore and other external equipment; Ethernet interface adopts chip LXT972ALC, adopt the clock oscillation circuit of 25M, this chip LXT972ALC transmits and receives interface data, clock signal and control signal corresponding end thereof link to each other with the respective end of the Ethernet interface of described TESTMODULE assembly respectively, the inputoutput data line of described chip LXT972ALC is after isolating transformer chip TG110-S050N5 effect, be connected on respectively on each respective pin of Ethernet interface, described chip LXT972ALC management data clock signal and management data input/output signal and enabling signal also are connected on respectively on each respective end of described TESTMODULE assembly, so that host computer is by the visit of this Ethernet interface to microprocessor MCF5272; The BDM interface is a kind of background debugging interface, links to each other with the respective end of the BDM control unit interface of TESTMODULE assembly, for outside Flash memory in the core board, the debugging of SDRAM memory is used;

CPLD, adopt Xilinx CPLD family device XC95288XL-7TQ144C, the test interface of this CPLD is drawn the jtag interface as Target Board, be used for this CPLD is tested, the startup output signal of described TESTMODULE assembly, the input/output signal of timer are linked to each other with described CPLD respective end respectively with pulse-width modulated output signal; Described microprocessor MCF5272 is by embedded TESTMODULE assembly, make the general purpose I/O signal of this microprocessor, chip selection signal, address wire, data wire and each control signal output ends link to each other with each respective input of this CPLD, to make full use of the advantage of programmable logic device, GPBUS1 controls to peripheral bus, this peripheral bus GPBUS1 not only links to each other with each output signal control end of CPLD, and again with the chip selection signal of TESTMODULE assembly, the output enable signal, write enable signal, data-signal, transmit answer signal, data/address bus transmission marking signal, the interruption input signal links to each other, and makes this bus to be configured as required;

The PA interface links to each other with the A port of the universaling I/O port of TESTMODULE assembly, uses as control circuit;

Functional interface FUNC links to each other with the pulse-width modulated output signal of TESTMODULE assembly, the input/output signal of timer and some signal ends of formation serial peripheral interface, uses as control circuit;

The BUS1 bus interface, with the chip selection signal of TESTMODULE assembly, data/address bus transmission marking signal, interrupt input signal, output enable signal, write enable signal, transmit answer signal, data wire, address wire link to each other;

The LCD interface with data wire, the output enable signal of TESTMODULE assembly, write enable signal, chip selection signal, transmission answer signal end and link to each other, is used for the demonstration of some state informations in the middle of program debugging or the program operation process;

The SignalML document is set in the described host computer, and the microprocessor MCF5272 of core board is provided with the SignalML analysis program, SignalML generator and signal lamp bus protocol Transformation Program, core board reads SignalML file with the http protocol form from host computer by the Ethernet interface of Target Board, after the SignalML parsing, generate semaphore information, signal information, timing information, and then by signal lamp bus protocol Transformation Program information that these are concrete in the understandable mode of semaphore, send to semaphore, finish control semaphore; Synchronous signal lamp bus protocol Transformation Program can access some specifying informations of semaphore by the serial ports of Target Board, be converted into the information of SignalML form again by SignalML generator semaphore information, signal information and timing information that these are concrete, store, and these SignalML information are passed to host computer by Ethernet interface by the Web service interface routine, again these information are shown with the form of the page or generate corresponding file at host computer, store.

Evidence: the present invention has realized communicating by letter between different manufacturers, dissimilar traffic control signal machine and the host computer, has improved the integrated level of entire city traffic control system, thereby makes urban traffic signal control system give play to greatest benefit.

Description of drawings

The core board schematic diagram of the universal embedded communication board of Fig. 1;

Be connected plug-in unit figure between the core board of the universal embedded communication board of Fig. 2 and the Target Board;

The Target Board schematic diagram of the universal embedded communication board of Fig. 3;

The Target Board power circuit partial design of the universal embedded communication board of Fig. 4;

The information flow chart of the universal embedded communication board of Fig. 5;

Fig. 6 SignalML structural framing.

Embodiment

Technical scheme of the present invention: this universal embedded communication board based on the SignalML language comprises core board and Target Board two boards, what wherein core board adopted is ColdFire microprocessor 5272, it has variable length RISC (reduced instruction set computer) structure, and integrated high-performance kernel and a large amount of peripheral interfaces with height code density, adopt μ CLinux embedded OS.μ CLinux is based on the linux kernel exploitation, is the embedded OS of making for the microprocessor of no memory administrative unit specially, and it also is the free software of issuing down at the public licence of freeware GNU (GPL).Core board comprises memory expansion part (comprising two parts of Flash and SDRAM memory expansion), reset and clock circuit is provided with part and start-up circuit configuration section.And Target Board mainly comprises embedded TESTMODULE assembly, power circuit part, CPLD part and some peripheral interface circuits: Ethernet interface, two UART interfaces, BDM interface (background debug port), LCD interface, jtag interface, two bus interface and PA interface and a functional interface FUNC.Embedded TESTMODULE assembly is integrated in microprocessor MCF5272 and the memory Flash that extends out and SDRAM on this module by pin JP3 and JP4 (as shown in Figure 2), it can be handled as an element during use.

The core board schematic diagram is as shown in Figure 1: ColdFire series microprocessor MCF5272 has advantages such as high-performance, low price, integrated level height, excellent performance, 32 bit address and data/address bus in the sheet, processor cores and bus frequency are 66MHZ, the instruction Cache that has 4KB SDRAM, 16KB ROM and 1KB in the sheet, and abundant peripheral interface is provided, as: two universal asynchronous/transceiver (UART), ethernet module, USB (USB) module, external memory interface, formation serial peripheral interface (QSPI) etc. synchronously.

Microprocessor MCF5272 memory expansion comprises Flash memory expansion and two parts of SDRAM expansion, the former is mainly used to the user data of depositing program code, constant and needing to preserve as can onlinely carrying out the erasable nonvolatile memory of electricity after system's power down; The latter then has the advantage that memory space is big, access speed is fast, price is low, mainly is used as running space, data and the stack area of program, but must periodic refreshing.Wherein Flash memory employing memory capacity is the AM29LV320D chip of 32M position, the BYTE# of AM29LV320D is connect high level, make AM29LV320D be operated in word pattern, and with the output enable signal OE# of this chip, write enable signal WE# and link to each other with R/ W with the corresponding OE/RD of MCF5272 respectively, so that MCF5272 controls its corresponding output enable and read-write operation, with its address wire A ₀-A ₂₀, data wire DQ ₀-DQ ₁₅Respectively with the A of MCF5272 ₁-A ₂₁, D ₁₆-D ₃₁Link to each other, and its chip selection signal is received on the Flash.CS on the connection pin JP2 on the core board, reset signal RESET# pin is connect high level; And the SDRAM accumulator system adopts is the MT48LC4M32B2 chip of 128M position, because the data-bus width of this chip is 32, so will be with its address wire A ₀-A ₉, A ₁₀And A ₁₁, data wire DQ ₀-DQ ₃₁Corresponding with MCF5272 respectively A ₂-A ₁₁, A10_PRECHG and A ₁₃, D ₀-D ₃₁Link to each other, the clock enable signal CKE of this chip, clock signal clk, chip selection signal CS#, write enable signal WE#, CAS#, RAS#, BA ₀-BA ₁Corresponding with the sdram controller of MCF5272 respectively SDCLKE, SDCLK, SDRAMCS/ CS7, SDWE, CAS0, RAS0, SDBA0-SDBA1 link to each other, with DQM ₀-DQM ₃Link to each other with the BS0-BS3 of sdram controller respectively, MCF5272 just can carry out random read-write operation to SDRAM like this.

Start configuration circuit and comprise that bus starting pattern wire jumper JP1 and Flash sheet select wire jumper JP2, the former is used to select the bus transfer width, and the latter is used for determining the chip selection signal of Flash memory.Wherein JP1 links to each other with the corresponding signal of QSPI (formation serial peripheral interface) module through eight bus buffer 74LCX51, the pattern wire jumper during as bus starting, and default configuration is 1,2 to link to each other, and selects the 32bits bus transfer; JP2 selects wire jumper as the sheet of FLASH, is used to select the chip selection signal of FLASH memory chip, and 1,2 use chip selection signal CS0 when linking to each other, and 2,3 use chip selection signal CS1 when linking to each other.

The clock module of microprocessor MCF5272 is provided by the outside oscillating circuit module of frequency of oscillation for 66MHZ, reseting module provides reset signal by the RST pin of voltage monitoring circuit chip MAX708TCSA, and it is linked to each other with the RESET pin of MCF5272 microprocessor.When pressing reset button S1, the RST pin output low level of MAX708TCSA is carried out reset operation to MCF5272.

The Target Board schematic diagram is as shown in Figure 3: the description that it is detailed the circuit catenation principle figure of Target Board, comprise embedded TESTMODULE assembly, power circuit part, CPLD part, Ethernet interface, two UART interfaces, BDM interface (background debug port), LCD interface, JTAG mouth, two bus interface and PA mouth and a functional interface FUNC altogether.Embedded TESTMODULE assembly is integrated in MCF5272, Flash, SDRAM on the module by pin JP3, JP4, just on embedded TESTMODULE assembly basis, carried out the expansion of corresponding interface circuits then, therefore also we can say and realized the control of core board microprocessor MCF5272 the relevant interface and the device of Target Board by embedded TESTMODULE assembly.

After the alternating current process bridge rectifier of power circuit part (as shown in Figure 4) with 5v, again through forward adjuster LM7805 output 5v direct current, through after the capacitor filtering, stable 5v DC power supply just can be provided, because some device needs the direct voltage of 3.3v, thus also will be through a voltage changer, be the voltage of 3.3v with the voltage transformation of 5v, pass through again at last after the Filtering Processing, just can provide stable 3.3v power supply.

That CPLD partly adopts is Xilinx CPLD family device XC95288XL-7TQ144C, can use Xilinx ISE software to develop design, contain the jtag test interface circuit, have testability, and have online programmable (ISP:In System Programmable) ability.The test interface circuit of CPLD module is drawn, as the jtag interface of Target Board, so that the CPLD module is tested accordingly.And general purpose I/O (GPIO) signal CPU.GPIO.PA[0:15 with the MCF5272 microprocessor] and some chip selection signal CS[2:6], address wire A ₁-A ₂₂, data wire D ₁₆-D ₃₁, control signal CPU.WE, CPU.OE, CPU.RST0 etc. link to each other with CPLD, to make full use of the advantage of programmable logic device, GPBUS1 controls to peripheral bus.Because peripheral bus GPBUS1 not only links to each other with the output of CPLD, and with chip selection signal CS6, enable signal CPU.WE and CPU.OE, the data wire D of embedded TESTMODULE assembly ₁₆-D ₃₁Deng linking to each other, so this bus can have good autgmentability so that be configured as required.

What Ethernet interface adopted is the LXT972A Fast Ethernet transponder chip that can support the full-duplex operation of 10Mbps and 100Mbps, the clock frequency that the ethernet transceiver chip adopts is the clock oscillation circuit of 25MHZ, inputoutput data line TPIP with the LXT972A chip, TPIN, TPFOP, TPFON is after isolating transformer chip TG110-S050N5 effect, be connected on 3 of Ethernet interface respectively, 6,1, on 2 pins, data are accepted in the transmission of LXT972A, clock signal and control signal corresponding TX EN thereof, TX ER, TXD[0:3], TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[0:3], COL, CRS respectively with the ETH.ETXEN of the Ethernet interface of Target Board TESTMODULE assembly, ETH.ETXERR, ETH.ETXD[0:3], ETH.ETXCLK, ETH.ERXCLK, ETH.ERXDV, ETH.ERXERR, ETH.ERXD[0:3], ETH.ETXCOL, ETH.ECRS links to each other, and the management data clock signal MDC of LXT972A and input/output signal MDIO thereof and RESET are connected on the pin ETH.EMDC of embedded TESTMODULE assembly respectively, ETH.EMDIO, on the CPU.RST0, so just can realize host computer by Ethernet to the visit of embedded communication plate.

What the UART interface adopted is the SP3243 chip of the RS-232 transceiver of SIPEX company production, and it is one three driving, five receiver chips.On UART.TXD2, the UART.RTS2 of the UART interface of the reflector of this chip three input T1IN, T2IN, T3IN pin difference TESTMODULE assembly, the UART.TXD1 pin, its receiver output R1OUT, R2OUT, R5OUT are connected on respectively on UART.CTS2, UART.RXD2, the UART.RXD1 pin of UART interface, and output pin T1OUT, the T2OUT of this chip, T3OUT are connected on respectively on 3 pins of 3,7 pins of UART.J2 and UART.J1, as the input of RS-232 reflector; Input pin R1IN, the R2IN of this chip, R5IN are connected on respectively on 2 pins of 8,2 pins of UART.J2 and UART.J1.Such two serial ports just can communicate with external equipment under the control of MCF5272 microprocessor.By the UART interface, can realize configuration on the one hand, as adding user program, adding the transplanting of device drives and application program etc. to μ CLinux; By serial ports, realize visit or control on the other hand to semaphore or other equipment.

The MCF5272 microprocessor adopts background debug mode (BDM, Background DebugMode) debugging, by the BDM interface, can realize SDRAM detection, Flash detection, the programming of Flash file, ram file programming, single-step debug or the like.By the LCD interface, can be implemented in the demonstration of the more central state informations of program debugging or program operation process, can play the visual effect of enhanced system.Other interface can be joined corresponding principle subgraph in the see this drawing, these interfaces provide abundant peripheral interface resource, debugging interface and power interface for universal embedded communication board, for the debugging of systemic-function, expand strong device resource basis is provided.

Be further described in conjunction with 5 figure:

With reference to Fig. 5, based on the information flow block diagram of the universal embedded communication board of SignalML language as shown in Figure 5, host computer links to each other with universal embedded communication board by Ethernet, and semaphore can link to each other with communication board by serial ports, just can finish the interconnection of host computer and semaphore thus, realize inquiry and the control operation of host computer the semaphore state information.At the closure or the diversity of semaphore communication protocol, universal embedded communication board is finished the conversion of the HTTP host-host protocol and the signal lamp bus protocol of SignalML information, realizes nothing barrier communication between the two.When host computer is desired the control signal machine, with relevant information with the SignalML form according to http protocol, get in touch by Ethernet and embedded communication plate, and then the SignalML information decomposition is become other the specifying information such as timing of semaphore by the analysis program of SignalML, and then by signal lamp bus protocol Transformation Program information that these are concrete in the understandable mode of semaphore, send to semaphore, finish control semaphore; When desiring the state of request signal machine, by signal lamp bus protocol Transformation Program, some specifying informations that can the picked up signal machine, and then be converted into the SignalML form by the SignalML generator information that these are concrete and store, at last these information are passed to the server of host computer according to http protocol with the SignalML form, and the information of these SignalML forms shown with page format or generate corresponding file, store.

According to the demand data analysis of traffic control system with consider the practical application of notebook data standard, the defined computer interpretation of both being convenient to, make things convenient for again the signal lamp control crossing that the user understands " data set " initial structure as shown in Figure 6.

Claims (1)

1, based on the universal embedded communication board of SignalML language, it is characterized in that, described SignalML is meant the traffic signals SGML, this language is based on a kind of SGML standard that extend markup language is described signal lamp control intersection control information, it makes signal control data separate with signal controller manufacturer with software platform, realize the transfer of data between the different platform, this all purpose communication plate comprises core board and Target Board, and Target Board integrates microprocessor in the core board and the memory that extends out by connector, wherein:

Core board comprises:

ColdFire series microprocessor MCF5272,

The Flash memory, adopt the AM29LV320D chip of 32M position, be operated in the word pattern state, the output enable signal input part of this chip, write enable signal input, address wire, data wire and link to each other with this microprocessor MCF5272 corresponding output end respectively, and the sheet that the input of chip selection signal links to each other with this microprocessor MCF5272 selects the respective end of wire jumper plug-in unit JP2 to link to each other;

The SDRAM memory, adopt the MT48LC4M32B2 chip of 128M position, the clock signal that this chip comprises, clock enable signal, chip selection signal, write enable signal, rank addresses pulse output pin signal, address wire and data wire and link to each other with the respective end of this microprocessor MCF5272 at each interior end;

Bus starting pattern wire jumper connector JP1, link to each other with the corresponding signal end of the formation serial peripheral interface of this microprocessor MCF5272 through eight bus buffer 74LCX541, pattern wire jumper during as bus starting, default configuration are 1,2 to link to each other, and select the 32bits bus transfer;

Clock circuit adopts the outside oscillating circuit chip of OSC_66M, to this microprocessor MCF5272 clock signal;

Reset circuit adopts the MAX708TCSA chip, and when pressing reset button, this chip just provides reset signal to this microprocessor MCF5272;

Target Board comprises:

Embedded TESTMODULE assembly is integrated in microprocessor MCF5272 and the memory that extends out on this module by plug-in unit JP3 and JP4, and be provided with two UART interfaces, Ethernet interface, the BDM interface, the LCD interface, two bus interface, PA interface and functional interface: wherein, the UART interface adopts chip SP3243E, its transmitter input end, the receiver output is connected on respectively on the respective end of UART control unit interface of TESTMODULE assembly, and the output pin of this chip SP3243E, input pin links to each other with the input of RS-232 reflector and the output of receiver respectively, so that microprocessor MCF5272 realizes the communication to semaphore and other external equipment; Ethernet interface adopts chip LXT972ALC, adopt the clock oscillation circuit of 25M, this chip LXT972ALC transmits and receives interface data, clock signal and control signal corresponding end thereof link to each other with the respective end of the Ethernet interface of described TESTMODULE assembly respectively, the inputoutput data line of described chip LXT972ALC is after isolating transformer chip TG110-S050N5 effect, be connected on respectively on each respective pin of Ethernet interface, described chip LXT972ALC management data clock signal and management data input/output signal and enabling signal also are connected on respectively on each respective end of described TESTMODULE assembly, so that host computer is by the visit of this Ethernet interface to microprocessor MCF5272; The BDM interface is a kind of background debugging interface, links to each other with the respective end of the BDM control unit interface of TESTMODULE membrane module, for outside Flash memory in the core board, the debugging of SDRAM memory is used;

CPLD, adopt Xilinx CPLD family device XC95288XL-7TQ144C, the test interface of this CPLD is drawn the jtag interface as Target Board, be used for this CPLD is tested, the startup output signal of described TESTMODULE assembly, the input/output signal of timer are linked to each other with described CPLD respective end respectively with pulse-width modulated output signal; Described microprocessor MCF5272 is by embedded TESTMODULE assembly, make the general purpose I/O signal of this microprocessor, chip selection signal, address wire, data wire and each control signal output ends link to each other with each respective input of this CPLD, to make full use of the advantage of programmable logic device, GPBUS1 controls to peripheral bus, this peripheral bus GPBUS1 not only links to each other with each output signal control end of CPLD, and again with the chip selection signal of TESTMODULE assembly, the output enable signal, write enable signal, data-signal, transmit answer signal, data/address bus transmission marking signal, the interruption input signal links to each other, and makes this bus to be configured as required;

The PA interface links to each other with the A port of the universaling I/O port of TESTMODULE assembly, uses as control circuit;

Functional interface FUNC links to each other with the pulse-width modulated output signal of TESTMODULE assembly, the input/output signal of timer and some signal ends of formation serial peripheral interface, uses as control circuit;

The BUS1 bus interface, with the chip selection signal of TESTMODULE assembly, data/address bus transmission marking signal, interrupt input signal, output enable signal, write enable signal, transmit answer signal, data wire, address wire link to each other;

The LCD interface with data wire, the output enable signal of TESTMODULE assembly, write enable signal, chip selection signal, transmission answer signal end and link to each other, is used for the demonstration of some state informations in the middle of program debugging or the program operation process;

The SignalML document is set in the described host computer, and the microprocessor MCF5272 of core board is provided with the SignalML analysis program, SignalML generator and signal lamp bus protocol Transformation Program, core board reads SignalML file with the http protocol form from host computer by the Ethernet interface of Target Board, after the SignalML parsing, generate semaphore information, signal information, timing information, and then by signal lamp bus protocol Transformation Program information that these are concrete in the understandable mode of semaphore, send to semaphore, finish control semaphore; Synchronous signal lamp bus protocol Transformation Program can access some specifying informations of semaphore by the serial ports of Target Board, be converted into the information of SignalML form again by SignalML generator semaphore information, signal information and timing information that these are concrete, store, and these SignalML information are passed to host computer by Ethernet interface by the Web service interface routine, again these information are shown with the form of the page or generate corresponding file at host computer, store.

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