CN1741387A - Latch reverse circuit and trigger and double-latch data trigger using the same - Google Patents
Latch reverse circuit and trigger and double-latch data trigger using the same Download PDFInfo
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- CN1741387A CN1741387A CN 200410057911 CN200410057911A CN1741387A CN 1741387 A CN1741387 A CN 1741387A CN 200410057911 CN200410057911 CN 200410057911 CN 200410057911 A CN200410057911 A CN 200410057911A CN 1741387 A CN1741387 A CN 1741387A
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- 230000005540 biological transmission Effects 0.000 description 5
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Abstract
A latch reverse circuit consists of the first PMOS transistor , the second PMOS transistor , the first NMOS transistor , the second NMOS transistor , the first level regulation unit and the second level regulation unit . It features that the first level regulation unit and the second level regulation unit are used to regulate levels of source electrode of the second PMOS transistor and drain electrode of the second NMOS transistor in advance for rising reaction speed of latch reverse circuit .
Description
Technical field
The present invention relates to a kind of negater circuit that latchs, particularly relate to a kind of negater circuit that latchs that promotes reaction speed.
Background technology
Figure 1A shows general twin-lock deposit data trigger (double latch data flip-flop, DDFF) 10.General twin-lock deposit data trigger 10 receives two input signal D1 and D2, and two triggered clock CLK1 and CLK2, and produces an output signal Dout.This twin-lock deposit data trigger 10 is the state of output signal Dout with the state of input signal D1 when triggering the positive edge of clock CLK1, and when triggering the positive edge of clock CLK2, is the state of output signal Dout with the state of input signal D2.Therefore, can utilize this twin-lock deposit data trigger 10 that two parallel datas are merged into serial datum output.
Figure 1B shows the Organization Chart of known twin-lock deposit data trigger 10.This pair door bolt data trigger 10 comprises four and latchs negater circuit 111,112,113,114, a buffer 12 and two latch units (latch) 13,13 '.First latchs negater circuit 111 receives the first data-signal D1 and triggers clock CLK1, and produces one first latch signal DD1, and the first latch signal DD1 changes over the reverse level of the first data-signal D1 when the low level of this triggering clock CLK1.The 3rd latchs negater circuit 113 receives the first latch signal DD1 and triggers clock CLK1, and produces one the 3rd latch signal DD3.And the 3rd latch signal DD3 changes over the reverse level of the first latch signal DD1 when the positive level of this triggering clock CLK1, also is the level of the first data-signal D1.Second latchs the operation that negater circuit 112 and the 4th latchs negater circuit 114, latchs negater circuit 111 and the 3rd to latch negater circuit 113 identical with first, and its difference is that the triggering clock that is received is CLK2.And generally trigger clock in the use is that CLK2 is that the triggering clock is the reverse signal of CLK1.
Change by negative edge that triggers clock CLK1 level and positive edge, twin-lock deposit data trigger 10 can synthesize the first data-signal D1 and the second data-signal D2, and exports an output signal Dout with double frequency.Please refer to Fig. 2, Fig. 2 shows 10 inputs of twin-lock deposit data trigger and the relation of exporting.
Fig. 3 shows these phenomenons that latch negater circuit and take place (this sentence first latch negater circuit 111 be example) when the positive edge of output signal level.Node A is between the source electrode of the drain electrode of the first PMOS transistor P1 and the 2nd PMOS transistor P2 among this figure.Node B is between the drain electrode of the source electrode of the first nmos pass transistor N1 and the 2nd PMOS transistor P2.When the level of Node B is 0, and the level of latch signal DD1 will become at 1 o'clock by 0, and voltage source must charge to level 1 with Node B and latch signal DD1 simultaneously.Therefore the described negater circuit that latchs changes as shown in Fig. 4 dotted line at the level of latch signal DD1.And when the voltage of Node B be 1 and the level of latch signal DD1 will become 1 by 0 time, voltage source only needs latch signal DD1 is charged to level 1.Therefore the described negater circuit that latchs changes as shown in Fig. 4 solid line at the level of latch signal DD1.
Fig. 5 shows the described phenomenon that negater circuit takes place (this sentence first latch negater circuit 111 be example) that latchs when the negative edge of output signal level.Node A is identical with position and Fig. 3 of Node B among this figure.When the level of node A is 1, and the level of latch signal DD1 becomes at 0 o'clock by 1, and the second nmos pass transistor N2 must be discharged to level 0 with node A and output latch signal DD1 simultaneously.Therefore the described negater circuit that latchs changes as shown in Fig. 6 dotted line in the level of latch signal DD1.And when the voltage of node A be 0 and the level of latch signal DD1 will become 0 by 1 time, the second nmos pass transistor N2 only needs latch signal DD1 is discharged to level 0.Therefore the described negater circuit that latchs changes as shown in Fig. 6 solid line in the level of latch signal DD1.
Because the described rate of reversing (slew rate) that latchs the latch signal of negater circuit has difference, to cause the output signal Dout of twin-lock deposit data trigger 10 that the problem of data dithering (data jitter) takes place, thereby cause the transmission quality instability of data.How making the transmission quality of data stable, is a urgent problem.
Summary of the invention
One of purpose of the present invention provides a kind of negater circuit that latchs, and promotes the rate of reversing that this latchs negater circuit.
One of purpose of the present invention provides a kind of twin-lock deposit data trigger, the problem that changes with the rate of reversing that reduces this twin-lock deposit data trigger.
For realizing above-mentioned purpose of the present invention, the invention provides a kind of negater circuit that latchs, this latchs negater circuit and comprises one the one PMOS transistor, one the 2nd PMOS transistor, one first nmos pass transistor, one second nmos pass transistor, one first level adjustment unit and one second level adjustment unit.The transistorized grid of the one PMOS receives a data-signal, and its source electrode is connected in a voltage source.The transistorized grid of the 2nd PMOS receives one first and triggers clock, and its source electrode is connected in a PMOS transistor drain, and its drain electrode output one latch signal.The grid of first nmos pass transistor receives one second and triggers clock, and its drain electrode is connected in the 2nd PMOS transistor drain.The grid of second nmos pass transistor receives data-signal, and its drain electrode is connected in the source electrode of first nmos pass transistor, and its source ground.The first level adjustment unit is connected between a PMOS transistor drain and the transistorized source electrode of the 2nd PMOS (being first node), use in data-signal is the level of 1 o'clock adjustment first node, make first node keep level 0, use promoting the reaction speed that latchs negater circuit.The second level adjustment unit is connected between the drain electrode of first nmos pass transistor and the transistorized source electrode of the 2nd PMOS (being Section Point), use in data-signal is the level of 0 o'clock adjustment Section Point, make Section Point keep level 1, use promoting the reaction speed that latchs negater circuit.
This latchs negater circuit and adjusts the level of first node and Section Point in advance by the level adjustment unit, thereby has promoted the reaction speed that latchs negater circuit, makes to latch negater circuit and become a negater circuit that latchs with high reaction speed.
Moreover, the invention provides a kind of trigger and twin-lock deposit data trigger that latchs negater circuit of the present invention that use, and, make trigger of the present invention and twin-lock deposit data trigger by the transmission quality of the high reaction speed that latchs negater circuit, reach the transmission quality of high reaction speed.
Description of drawings
Figure 1A is the schematic diagram of a known twin-lock deposit data trigger.
Figure 1B is the Organization Chart of a known twin-lock deposit data trigger.
Fig. 2 is that corresponding oscillogram is gone in the output of a known twin-lock deposit data trigger.
Fig. 3 is the known schematic diagram of negater circuit when the positive edge of output latch signal that latch.
Fig. 4 is the known oscillogram of negater circuit when the positive edge of output latch signal that latch.
Fig. 5 is the known schematic diagram of negater circuit when the output latch signal is born edge that latch.
Fig. 6 is the known oscillogram of negater circuit when the output latch signal is born edge that latch.
Fig. 7 is one according to the schematic diagram that latchs negater circuit of the present invention.
Fig. 8 one latchs the schematic diagram of negater circuit one embodiment according to the present invention.
Fig. 9 is the schematic diagram that a use the present invention latchs the trigger of negater circuit.
Figure 10 is the schematic diagram that a use the present invention latchs the twin-lock deposit data trigger of negater circuit.
Detailed description of main elements
10 twin-lock deposit data triggers
111,112,113,114 latch negater circuit
12 buffers
13 latch units
70,80 latch negater circuit
71,72 level adjustment units
81,82 MOS transistor
90 triggers
91,92,93,94 latch negater circuit
100 twin-lock deposit data triggers
CLK1, CLK2 triggering signal
N1, N2 nmos pass transistor
P1, P2 PMOS transistor
Embodiment
Latch negater circuit and use this trigger that latchs negater circuit and twin-lock to deposit trigger below with reference to graphic detailed description the present invention, and identical assembly will be with identical symbology.
Fig. 7 shows a kind of negater circuit that latchs of the present invention, and this latchs negater circuit 70 and comprises one the one PMOS transistor P1, one the 2nd PMOS transistor P2, one first nmos pass transistor N1, one second nmos pass transistor N2, one first level adjustment unit 71 and one second level adjustment unit 72.At present embodiment, the first level adjustment unit 71 is connected between a PMOS transistor P1 and the 2nd PMOS transistor P2 (node A).The second level adjustment unit 72 is connected between the first nmos pass transistor N1 and the second nmos pass transistor N2 (Node B).On the implementation, the second triggering clock CLK2 can be the reverse signal of the first triggering clock CLK1.
Next illustrate that the present invention latchs the annexation and the mode of operation of negater circuit 70, in the present embodiment, second triggers the reverse signal that clock CLK2 is the first triggering clock CLK1.Following state according to data-signal D further specifies.
State one: when data-signal D is H, the then second nmos pass transistor N2 conducting.Level adjustment unit 71 is adjusted to L with the voltage of node A in advance at this moment.Be L and when triggering clock CLK2 and being H when triggering clock CLK1 afterwards, then the 2nd PMOS transistor P2 and the first also conducting of nmos pass transistor N1, so latch signal DD becomes L via the first nmos pass transistor N1 and the second nmos pass transistor N2 ground connection.Because the voltage of node A becomes L in advance, therefore the first nmos pass transistor N1 and the second nmos pass transistor N2 do not need the discharge to node A, make the voltage of latch signal DD reduce to L fast.
State two: when being L as if data-signal D, a then PMOS transistor P1 conducting.Level adjustment unit 72 is adjusted to H with the voltage of Node B in advance at this moment.Be L and when triggering clock CLK2 and being H when triggering clock CLK1 afterwards, then the 2nd PMOS transistor P2 and the first also conducting of nmos pass transistor N1, so latch signal DD receives positive voltage and becomes H via a PMOS transistor P1 and the 2nd PMOS transistor P2.Because the voltage of Node B becomes H in advance, therefore a PMOS transistor P1 and the 2nd PMOS transistor P2 do not need the Node B charging, and the voltage fast lifting that makes latch signal DD is H.
This latchs negater circuit 70 and adjusts the level of node A and Node B in advance by level adjustment unit 71 and 72, thereby has promoted the reaction speed that latchs negater circuit, has solved the problem of output latch signal DD data dithering, has promoted the stability of transmission quality.
Fig. 8 shows the circuit that latchs negater circuit 80 of the present invention.As shown in the drawing, the level adjustment unit that latchs negater circuit 80 is a nmos pass transistor 81, and the level adjustment unit is a PMOS transistor 82, and remaining circuit is all with to latch negater circuit 70 identical.The grid of nmos pass transistor 81 receives data-signal D, and its drain electrode is connected in node A, and its source ground.The grid of PMOS transistor 82 receives data-signal D, and its source electrode is connected in voltage source, and its drain electrode is connected in Node B.It is identical with operation that this latchs negater circuit 80 and the framework that latchs negater circuit 70, no longer repeat specification.
Fig. 9 shows that a kind of use of the present invention latchs the circuit of the trigger of negater circuit.This trigger 90 comprises two and latchs a negater circuit 91,92 and a latch units 13.Latch negater circuit 91 and receive data-signal D1 and trigger clock CLK1, and produce one first latch signal DD1.The first latch signal DD1 changes over the reverse level of the first data-signal D1 when triggering clock CLK1 for L.Latch the reverse signal that negater circuit 92 receives the first latch signal DD1 and triggers clock CLK1, and produce one second latch signal DD2.The second latch signal DD2 changes over the reverse level of the first latch signal DD1 when triggering the H of clock CLK1.Buffer 12 receives the second latch signal DD2, and produces an output signal Dout.Latch units 13 keeps the level of the first latch signal DD1.In this embodiment, because trigger 90 utilizes two to latch negater circuit 91,92 formation secondarys (two stage) connections, and, make trigger 90 reach the transfer of data quality of high reaction speed by the transfer of data quality of the high reaction speed that latchs negater circuit 91,92.Certainly, level use the present invention has the negater circuit that latchs of level adjustment unit after can having only, and prime is used the general negater circuit that latchs.
Figure 10 shows that a kind of use of the present invention latchs the circuit of the twin-lock deposit data trigger of negater circuit.This twin-lock deposit data trigger 100 comprises four and latchs negater circuit 91,92,93,94, a buffer 12 and two latch units 13.The framework of this second embodiment and first embodiment is roughly the same with operation, and difference be that this twin-lock deposit data trigger 100 receives two input signal D1 and D2, and two triggering clock CLK1 and CLK2, and produces an output signal Dout.That is latch negater circuit 91,92 and come output signal according to triggering clock CLK1, come output signal and latch negater circuit 93,94 according to triggering clock CLK2.Triggering clock CLK2 can be the reverse signal that triggers clock CLK1.
This twin-lock deposit data trigger 100 state with input signal D1 when triggering the positive edge of clock CLK1 is the state of output signal Dout, and the state with input signal D2 is the state of output signal Dout when triggering the positive edge of clock CLK2.Therefore, if trigger clock CLK2 can be the reverse signal that triggers clock CLK1, this twin-lock deposit data trigger 100 is merged into the serial data Dout output with double frequency with two parallel data D1 and D2, and, make twin-lock deposit data trigger 100 become a trigger with high reaction speed transfer of data quality by the transfer of data quality of the high reaction speed that latchs negater circuit.Certainly, level use the present invention has the negater circuit that latchs of level adjustment unit after can having only, and prime is used the general negater circuit that latchs.
In sum, of the present inventionly latch negater circuit and use this trigger that latchs negater circuit and twin-lock deposit data trigger, latch the transistor level of negater circuit by the adjustment of level adjustment unit, promoted the reaction speed of the transfer of data that latchs negater circuit.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, those skilled in the art can carry out various distortion or change.
Claims (10)
1. one kind is latched negater circuit, comprises:
One the first transistor, its grid receives a data-signal, and its source electrode is connected in a voltage source;
One transistor seconds, its grid receive one first and trigger clock, and its source electrode is connected in the drain electrode of this first transistor;
One the 3rd transistor, its grid receive one second and trigger clock, and its drain electrode is connected in the drain electrode of this transistor seconds and produces an output signal;
One the 4th transistor, its grid receives this data-signal, and its drain electrode is connected in the 3rd transistorized source electrode, and its source ground;
One first level adjustment unit is connected in the source electrode of this transistor seconds, and using provides the source terminal of one first level to this transistor seconds; And
One second level adjustment unit is connected in the 4th transistor drain, and using provides one second level to the 4th transistor drain end.
2. the negater circuit that latchs as claimed in claim 1, wherein this second triggers the reverse signal that clock be this first triggering clock.
3. the negater circuit that latchs as claimed in claim 1, wherein this first transistor and transistor seconds are the PMOS transistor, this first level adjustment unit is adjusted into L with the voltage of this first level at this data-signal during for H.
4. the negater circuit that latchs as claimed in claim 3, wherein this first level adjustment unit comprises a nmos pass transistor, and the grid of this nmos pass transistor receives this data-signal, and its drain electrode is connected in the source electrode of this transistor seconds, and its source ground.
5. the negater circuit that latchs as claimed in claim 1, wherein the 3rd transistor AND gate the 4th transistor is a nmos pass transistor, this second level adjustment unit is adjusted into H with the voltage of this this second level at this data-signal during for L.
6. the negater circuit that latchs as claimed in claim 5, wherein this second level adjustment unit comprises a PMOS transistor, the transistorized grid of this PMOS receives this data-signal, and its source electrode is connected in a voltage source, and its drain electrode is connected in the 4th transistor drain.
7. trigger comprises:
One first latchs negater circuit, receives a data-signal and and triggers clock, and produce one first latch signal; And
One second latchs negater circuit, receives this first latch signal and this triggering clock, and produces one second latch signal;
Wherein this second latchs negater circuit and comprises:
One the first transistor, its grid receive this first latch signal, and its source electrode is connected in a voltage source;
One transistor seconds, its grid receive this triggering clock, and its source electrode is connected in the drain electrode of this first transistor;
One the 3rd transistor, its grid receives the reverse signal of this triggering clock, and its drain electrode is connected in the drain electrode of this transistor seconds and produces this second latch signal;
One the 4th transistor, its grid receive this first latch signal, and its drain electrode is connected in the 3rd transistorized source electrode, and its source ground;
One first level adjustment unit is in order to provide the source terminal of one first level to this transistor seconds; And
One second level adjustment unit is in order to provide one second level to the 4th transistor drain end.
8. the negater circuit that latchs as claimed in claim 12, wherein this first transistor and transistor seconds are the PMOS transistor, and the 3rd transistor AND gate the 4th transistor is a nmos pass transistor.
9. trigger as claimed in claim 8, wherein this first level adjustment unit comprises a nmos pass transistor, the grid of this nmos pass transistor receives this first latch signal, and its drain electrode is connected in the source terminal of this transistor seconds, and its source ground, this second level adjustment unit comprises a PMOS transistor, and the transistorized grid of this PMOS receives this first latch signal, and its source electrode is connected in a voltage source, and its drain electrode is connected in the 4th transistor drain end.
10. twin-lock deposit data trigger comprises:
One first latchs negater circuit, receives one first data-signal, and produces one first latch signal;
One first level adjustment unit is exported one first level;
One second latchs negater circuit, receives this first latch signal and this first level, and produces one second latch signal, wherein, promotes the reaction speed of this second latch signal by this first level;
One the 3rd latchs negater circuit, receive one second data-signal with and produce one the 3rd latch signal;
One second level adjustment unit is exported one second level;
One the 4th latchs negater circuit, receives the 3rd latch signal and this second triggering clock, and produces one the 4th latch signal, wherein, promotes the reaction speed of the 4th latch signal by this second level; And
One buffer receives the 3rd latch signal and the 4th latch signal, and produces an output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410057911 CN1741387B (en) | 2004-08-26 | 2004-08-26 | Latch reverse circuit and trigger and double-latch data trigger using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410057911 CN1741387B (en) | 2004-08-26 | 2004-08-26 | Latch reverse circuit and trigger and double-latch data trigger using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1741387A true CN1741387A (en) | 2006-03-01 |
| CN1741387B CN1741387B (en) | 2011-11-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410057911 Expired - Lifetime CN1741387B (en) | 2004-08-26 | 2004-08-26 | Latch reverse circuit and trigger and double-latch data trigger using the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1741387B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024012032A1 (en) * | 2022-07-14 | 2024-01-18 | 上海嘉楠捷思信息技术有限公司 | Dynamic d flip-flop, data operation unit, chip, hash board and computing device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI656738B (en) * | 2018-06-11 | 2019-04-11 | 瑞昱半導體股份有限公司 | Flip-flop circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6621318B1 (en) * | 2001-06-01 | 2003-09-16 | Sun Microsystems, Inc. | Low voltage latch with uniform sizing |
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2004
- 2004-08-26 CN CN 200410057911 patent/CN1741387B/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024012032A1 (en) * | 2022-07-14 | 2024-01-18 | 上海嘉楠捷思信息技术有限公司 | Dynamic d flip-flop, data operation unit, chip, hash board and computing device |
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| Publication number | Publication date |
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| CN1741387B (en) | 2011-11-09 |
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