CN1737604A - Personal positioning terminal apparatus based on FPGA technology - Google Patents

Abstract

This invention relates to one personal sticking pad composite positioning terminal based on FGPA, which comprises the process as following: connecting the output end of digital indicator with A/D conversion module input end connected to general control module through A/D conversion control module; GPS module is connected to total control module through series communication module with one end connected to monitor wireless center and with the other end connected to the general control module through series communication module; connecting one end of status display module with general control end and with the other end connected to LED; the timer module and reset switch and clock are connected to the general control module.

Description

A kind of personal positioning terminal apparatus based on the FPGA technology

One, technical field

The invention belongs to individual SMD Combined Positioning Terminal.Relate in particular to a kind of individual SMD Combined Positioning Terminal based on FPGA

Two, background technology

Since the nineties in 20th century, along with high precision, real-time, safe and reliable location survey and the appearance of time service method, GPS (Global Positioning System is called for short GPS) technology is more and more used.

The GPS Position Fixing Navigation System is made up of receiving terminal and Surveillance center.The applied research of China's navigation field is started late, location navigation receiving terminal volume based on GPS is bigger, mainly be confined to the big customer's of specific industry monitoring management, as public security, bank, traffic administration, navigation transportation etc., be difficult for being incorporated in the personal belongings and carry, inconvenient old man, child, amentia crowd and special industry personnel wear, and can't finish from security standpoint these crowds are monitored.At present, domestic portable personal positioning system rests on theoretical research stage or experimental stage, for example: its discussion of " based on the personal location system of GSM network " (2002 12 phases of the Yuan Shu Central China University of Science and Technology Guangdong communication technology) be a kind of positioning system that is applicable to urban mass-transit system, taxi dispatching system, large-scale logistics distribution system, transport vehicle tracker and motor vehicle antitheft system, its receiving terminal volume is big, being inconvenient to be used for the individual and carrying, is not personal location system truly.Receiving terminal products few in number on the market are external equipment, for example: " Personal GPS navigation device " (Inventors:Geelen, Pieter; (Hilversum, NL) United States Patent Application 20040243307), this patent is a kind of personal GPS guider, this device can show its position on map synchronously, show gps signal intensity, mark is carried out with icon in own interested place, and map is carried out convergent-divergent.But it is based on general purpose microprocessor, and volume ratio is bigger, and the single location of GPS is adopted in the location, the positioning performance instability, and precision is limited, and the product life cycle is short, and upgrading is inconvenient, and cost is than higher.

Three, summary of the invention

Purpose of the present invention provides the individual SMD Combined Positioning Terminal that a kind of volume is little, cost is low, position stability is good, bearing accuracy is high, product up-gradation is convenient, the product life cycle is long.

For achieving the above object, the technical solution adopted in the present invention is: the output terminal of digital compass is connected with the input end of A/D modular converter, the A/D modular converter links to each other with total control module by A/D conversion and control module, the GPS module links to each other with total control module by serial communication modular, one end of GPRS module and Surveillance center's wireless connections, the other end links to each other with total control module by serial communication modular, one end of state display module links to each other with total control module, the other end is connected with LED, timer module, reset switch, clock is connected with total control module respectively;

Wherein, A/D conversion and control module, timer module, total control module, state display module, serial communication modular and serial communication modular are programmed with Hardware Description Language VHDL and are integrated among a slice FPGA.

Described total control module is made up of frequency division module, control module; The reset signal input end resertin of control module links to each other with reset switch, and the reset signal output terminal resertout of control module links to each other with the reset signal input end resert of A/D conversion and control module, timer module, state display module and two serial communication modulars respectively; The clk end of frequency division module, ad_clk end link to each other with the clkin end of clock, A/D conversion and control module respectively, and the time_clk end of frequency division module links to each other the uart_clk of frequency division module with the clk_in end of timer module ₁End links to each other the uart_clk of frequency division module with the clkin end of serial communication modular ₂End links to each other with the clkin end of serial communication modular.

Described A/D conversion and control module is made up of fifo cache module and A/D control module; The written allowance signal end wr of A/D control module, read to allow signal end rd, full end and empty end to link to each other with wrreq end, rdreq end, full end and the empty end of fifo cache module respectively; The clkout end of A/D control module, ad_oe end link to each other with clk end, the oe end of A/D modular converter respectively, and the clkin end of A/D control module links to each other with the ad_clk end of frequency division module; The fifoclk end of fifo cache module, data input pin i ₀-i ₇Respectively with the clk of A/D modular converter end, data output end d ₀-d ₇Link to each other the data output end q of fifo cache module ₀-q ₇Data input pin in control module ₀-in ₇Link to each other.

Described serial communication modular is made up of baud rate generation module, receiver module; The baud rate output terminal bd_out of baud rate generation module links to each other with the baud rate input end bd_in of receiver module; The clkin end of baud rate generation module and the uart_clk of frequency division module ₁End links to each other, and the rxd end of receiver module links to each other the data output end dout of receiver module with the txd end of GPS module ₀～dout ₇Respectively with the gps of control module ₀～gps ₇End links to each other.

Described serial communication modular is made up of baud rate generation module, sending module and receiver module; The baud rate output terminal bd_out of baud rate generation module links to each other with the baud rate input end bd_rxd of receiver module and the baud rate input end bd_txd of sending module respectively; The clkin end of baud rate generation module and the uart_clk of frequency division module ₂End links to each other, the rxd end of receiver module, data output end dout ₀～dout ₇Respectively with the txd end of GPRS module, the gprs of control module ₀～gprs ₇End links to each other, the txd end of sending module, data input pin din ₀～din ₇Respectively with the rxd end of GPRS module, the gprs_out of control module ₀～gprs_out ₇End links to each other.

Described timer module is made up of read-write control module and timing module; The dout of read-write control module ₀～dout ₇Din with the timing module ₀～din ₇End links to each other; The data input pin d of read-write control module ₀～d ₇, working mode selection end a ₀, a ₁, read to allow to hold rd, write allow end wr, input end of clock clk_in respectively with the clk_d of control module ₀～clk_d ₇End, ta ₀, ta ₁End, trd, twr end, time_clk hold connection, the output terminal ckout of timing module ₀～ckout ₃Ck with control module ₀～ck ₃Connect.

Described state display module is made up of display module and display control module; The x of display module ₀～x ₃End and display control module x1 ₀～x1 ₃End links to each other; The xc of display control module ₀～xc ₇The xt of end and control module ₀～xt ₇End links to each other, and the write gate signal rw end of display control module links to each other with the xrw end of control module, and the output terminal of display module is connected with LED.

Owing to adopt technique scheme, each module is integrated in the fpga chip, have that volume is little, in light weight, low in energy consumption, cost of development is low, the construction cycle is short, the product life cycle grows, the characteristics easily of upgrading; Adopt digital compass and GPS integrated positioning, make that its position stability is good, bearing accuracy is high.Usable range of the present invention is wide, not only is fit to individual paster and carries, and also can be used for vehicle-mounted.

Four, description of drawings

Fig. 1 is a kind of general structure schematic block diagram of the present invention;

Fig. 2 is the structural representation block diagram of the A/D conversion and control module [2] among Fig. 1;

Fig. 3 is the structural representation of the serial communication modular [9] among Fig. 1;

Fig. 4 is the structural representation of the serial communication modular [7] among Fig. 1;

Fig. 5 is the structural representation of the timer module [3] among Fig. 1;

Fig. 6 is the structural representation of the state display module [5] among Fig. 1;

Fig. 7 is the structural representation of the total control module [4] among Fig. 1.

Five, embodiment

The invention will be further described below in conjunction with embodiment:

[embodiment]

Present embodiment as shown in Figure 1, the output terminal of digital compass [14] is connected with the input end of A/D modular converter [1], A/D modular converter [1] links to each other with total control module [4] by A/D conversion and control module [2], GPS module [10] links to each other with total control module [4] by serial communication modular [9], one end of GPRS module [8] and Surveillance center's wireless connections, the other end links to each other with total control module [4] by serial communication modular [7], one end of state display module [5] links to each other with total control module [4], the other end and LED[6] be connected timer module [3], reset switch [12], clock [11] is connected with total control module [4] respectively;

Wherein, A/D conversion and control module [2], timer module [3], total control module [4], state display module [5], serial communication modular [7] and serial communication modular [9] are programmed with Hardware Description Language VHDL and are integrated into a slice FPGA[13] in.

Total control module [4] is made up of frequency division module [26], control module [27] as shown in Figure 7.The reset signal input end resertin of control module [27] links to each other with reset switch [12], and the reset signal output terminal resertout of control module [27] links to each other with the reset signal input end resert of A/D conversion and control module [2], timer module [3], state display module [5] and serial communication modular [7], [9] respectively.The clk end of frequency division module [26], ad_clk end link to each other with the clkin end of clock [11], A/D conversion and control module [2] respectively, and the time_clk end of frequency division module [26] links to each other the uart_clk of frequency division module [26] with the clk_in end of timer module [3] ₁End links to each other the uart_clk of frequency division module [26] with the clkin end of serial communication modular [9] ₂End links to each other with the clkin end of serial communication modular [7].

A/D conversion and control module [2] is made up of fifo cache module [15] and A/D control module [16] as shown in Figure 2.The written allowance signal end wr of A/D control module [16], read to allow signal end rd, full end and empty end to link to each other with wrreq end, rdreq end, full end and the empty end of fifo cache module [15] respectively.The clkout end of A/D control module [16], ad_oe end link to each other with clk end, the oe end of A/D modular converter [1] respectively, and the clkin end of A/D control module [16] links to each other with the ad_clk end of frequency division module [26].The fifoclk end of fifo cache module [15], data input pin i ₀-i ₇Respectively with the clk of A/D modular converter [1] end, data output end d ₀-d ₇Link to each other the data output end q of fifo cache module [15] ₀-q ₇Data input pin in control module [27] ₀-in ₇Link to each other.

Serial communication modular [9] is made up of baud rate generation module [17], receiver module [18] as shown in Figure 3.The baud rate output terminal bd_out of baud rate generation module [17] links to each other with the baud rate input end bd_in of receiver module [18].The clkin end of baud rate generation module [17] and the uart_clk of frequency division module [26] ₁End links to each other, and the rxd end of receiver module [18] links to each other the data output end dout of receiver module [18] with the txd end of GPS module [10] ₀～dout ₇Respectively with the gps of control module [27] ₀～gps ₇End links to each other.

Serial communication modular [7] is made up of baud rate generation module [19], sending module [20] and receiver module [21] as shown in Figure 4.The baud rate output terminal bd_out of baud rate generation module [19] links to each other with the baud rate input end bd_rxd of receiver module [21] and the baud rate input end bd_txd of sending module [20] respectively.The clkin end of baud rate generation module [19] and the uart_clk of frequency division module [26] ₂End links to each other, the rxd end of receiver module [21], data output end dout ₀～dout ₇Respectively with the txd end of GPRS module [8], the gprs of control module [27] ₀～gprs ₇End links to each other, the txd end of sending module [20], data input pin din ₀～din ₇Respectively with the rxd end of GPRS module [8], the gprs_out of control module [27] ₀～gprs_out ₇End links to each other.

Timer module [3] is made up of read-write control module [22] and timing module [23] as shown in Figure 5.The dout of read-write control module [22] ₀～dout ₇Din with timing module [23] ₀～din ₇End links to each other.The data input pin d of read-write control module [22] ₀～d ₇, working mode selection end a ₀, a ₁, read to allow end rd, write allow end wr, input end of clock clk_in respectively with the clk_d of control module [27] ₀～clk_d ₇End, ta ₀, ta ₁End, trd, twr end, time_clk hold connection, the output terminal ckout of timing module [23] ₀～ckout ₃Ck with control module [27] ₀～ck ₃Connect.

State display module [5] is made up of display module [24] and display control module [25] as shown in Figure 6.The x of display module [24] ₀～x ₃End and display control module [25] x1 ₀～x1 ₃End links to each other.The xc of display control module [25] ₀～xc ₇The xt of end and control module [27] ₀～xt ₇End links to each other, and the write gate signal rw end of display control module [25] links to each other the output terminal and LED[6 of display module [24] with the xrw end of control module [27]] be connected.

Principle of work of the present invention is mainly as follows:

Digital compass [14] signal is through A/D conversion and control module [2], from ₀-in ₇End is input to total control module [4], and the calculation process of process total control module [4] obtains deflection φ, and φ is a clockwise direction, 0≤φ＜360.Total control module [4] is from gps ₀～gps ₇End is gathered the positioning signal (longitude and latitude, speed) of GPS receiver.

Obtain the average velocity of terminal organ:

Get Δ T interval time, think at this section in the period, terminal organ speed is approximate constant, every Δ T to from gps ₀～gps ₇The speed of the gps signal of end input is carried out n sampling, is labeled as v ₁, v ₂V _n, then can try to achieve average velocity and be: $\stackrel{\‾}{v}=\left(\underset{i=1}{\overset{n}{\mathrm{\Σ}}}\mathrm{vi}\right)/n,$ Deposit this average velocity in buffer memory, and bring in constant renewal in to obtain optimum value.

Terminal does not receive gps signal when the GPS blind area.When terminal has just entered blind area previous moment T ₀The time, the longitude in this moment of system log (SYSLOG) is E ₀, latitude W ₀, digital compass angle of deviation φ ₀During the gps signal losing lock, carry out auxiliary positioning with digital compass [14].With Δ t this time period is divided, obtain one by one little time period (T ₀, T ₀+ Δ t), (T ₀+ Δ t, T ₀+ 2 Δ t) ... (T ₀+ (n-1) Δ t, T ₀+ n Δ t), think that digital compass in the Δ t time [14] direction does not change.Simultaneously digital compass [14] was sampled with the Δ t time interval, obtain one group of angle of deviation φ ₁, φ ₂... φ _n, be located at T constantly _RTerminal organ need be known the position at own place, at first obtains T _RBelong to top which time period, suppose at (T ₀+ i Δ t, (T ₀+ i+1) Δ t) in, the angle of deviation of this moment is φ _i, according to iterative algorithm:

E _j＝E _j-1+F(L*sina(φ _j-1))

W _j＝W _j-1+F(L*cos(φ _j-1)) 1≤j≤i；

Calculate T0+i Δ t initial longitude and latitude (E constantly _i, W _i),

TR longitude and latitude (E constantly then _TR, W _TR):

E _TR＝E _i+F(L*sina(φi))

W _TR＝W _i+F(L*cos(φi))

In the formula:

L＝Δt* v

V: the best average velocity of trying to achieve when effective for gps signal, and deposit in total control module [4] buffer memory, after the gps signal losing lock, system stops to find the solution average velocity.

F (): displacement is converted into the longitude and latitude function.

The AT command list leaves among one 20 * 10 the ROM, and the ROM programmed configurations is at FPGA[13] inside, storage AT order sends AT by serial port module [7] and orders GPRS module [8], carries out message exchange with Surveillance center.Present embodiment is integrated in a slice FPGA[13 with the SMD Combined Positioning Terminal of individual] in, digital compass [14] signal is sent into FPGA[13 after changing through A/D], GPS module [10] is sent into FPGA[13 with positioning signal by serial communication modular [9]], through generating final positioning signal after the calculation process of total control module [4].Because individual SMD Combined Positioning Terminal is integrated in a FPGA[13] in, it is very little that volume can be done, and be convenient to old man, children, amentia crowd and wear, and upgrading is convenient, and the product life cycle is long.

Claims (7)

1, a kind of personal positioning terminal apparatus based on the FPGA technology, it is characterized in that the output terminal of digital compass [14] is connected with the input end of A/D modular converter [1], A/D modular converter [1] links to each other with total control module [4] by A/D conversion and control module [2], GPS module [10] links to each other with total control module [4] by serial communication modular [9], one end of GPRS module [8] and Surveillance center's wireless connections, the other end links to each other with total control module [4] by serial communication modular [7], one end of state display module [5] links to each other with total control module [4], the other end and LED[6] be connected timer module [3], reset switch [12], clock [11] is connected with total control module [4] respectively;

Wherein, A/D conversion and control module [2], timer module [3], total control module [4], state display module [5], serial communication modular [7] and serial communication modular [9] are programmed with Hardware Description Language VHDL and are integrated into a slice FPGA[13] in.

2, the personal positioning terminal apparatus based on the FPGA technology according to claim 1 is characterized in that described total control module [4] is made up of frequency division module [26], control module [27]; The reset signal input end resertin of control module [27] links to each other with reset switch [12], and the reset signal output terminal resertout of control module [27] links to each other with the reset signal input end resert of A/D conversion and control module [2], timer module [3], state display module [5] and serial communication modular [7], [9] respectively; The clk end of frequency division module [26], ad_clk end link to each other with the clkin end of clock [11], A/D conversion and control module [2] respectively, and the time_clk end of frequency division module [26] links to each other the uart_clk of frequency division module [26] with the clk_in end of timer module [3] ₁End links to each other the uart_clk of frequency division module [26] with the clkin end of serial communication modular [9] ₂End links to each other with the clkin end of serial communication modular [7].

3, the personal positioning terminal apparatus based on the FPGA technology according to claim 1 is characterized in that described A/D conversion and control module [2] is made up of fifo cache module [15] and A/D control module [16]; The written allowance signal end wr of A/D control module [16], read to allow signal end rd, full end and empty end to link to each other with wrreq end, rdreq end, full end and the empty end of fifo cache module [15] respectively; The clkout end of A/D control module [16], ad_oe end link to each other with clk end, the oe end of A/D modular converter [1] respectively, and the clkin end of A/D control module [16] links to each other with the ad_clk end of frequency division module [26]; The fifoclk end of fifo cache module [15], data input pin i ₀-i ₇Respectively with the clk of A/D modular converter [1] end, data output end d ₀-d ₇Link to each other the data output end q of fifo cache module [15] ₀-q ₇Data input pin in control module [27] ₀-in ₇Link to each other.

4, the personal positioning terminal apparatus based on the FPGA technology according to claim 1 is characterized in that described serial communication modular [9] is made up of baud rate generation module [17], receiver module [18]; The baud rate output terminal bd_out of baud rate generation module [17] links to each other with the baud rate input end bd_in of receiver module [18]; The clkin end of baud rate generation module [17] and the uart_clk of frequency division module [26] ₁End links to each other, and the rxd end of receiver module [18] links to each other the data output end dout of receiver module [18] with the txd end of GPS module [10] ₀～dout ₇Respectively with the gps of control module [27] ₀～gps ₇End links to each other.

5, the personal positioning terminal apparatus based on the FPGA technology according to claim 1 is characterized in that described serial communication modular [7] is made up of baud rate generation module [19], sending module [20] and receiver module [21]; The baud rate output terminal bd_out of baud rate generation module [19] links to each other with the baud rate input end bd_rxd of receiver module [21] and the baud rate input end bd_txd of sending module [20] respectively; The clkin end of baud rate generation module [19] and the uart_clk of frequency division module [26] ₂End links to each other, the rxd end of receiver module [21], data output end dout ₀～dout ₇Respectively with the txd end of GPRS module [8], the gprs of control module [27] ₀～gprs ₇End links to each other, the txd end of sending module [20], data input pin din ₀～din ₇Respectively with the rxd end of GPRS module [8], the gprs_out of control module [27] ₀～gprs_out ₇End links to each other.

6, the personal positioning terminal apparatus based on the FPGA technology according to claim 1 is characterized in that described timer module [3] is made up of read-write control module [22] and timing module [23]; The dout of read-write control module [22] ₀～dout ₇Din with timing module [23] ₀～din ₇End links to each other; The data input pin d of read-write control module [22] ₀～d ₇, working mode selection end a ₀, a ₁, read to allow end rd, write allow end wr, input end of clock clk_in respectively with the clk_d of control module [27] ₀～clk_d ₇End, ta ₀, ta ₁End, trd, twr end, time_clk hold connection, the output terminal ckout of timing module [23] ₀～ckout ₃Ck with control module [27] ₀～ck ₃Connect.

7, the personal positioning terminal apparatus based on the FPGA technology according to claim 1 is characterized in that described state display module [5] is made up of display module [24] and display control module [25]; The x of display module [24] ₀～x ₃End and display control module [25] xl ₀～xl ₃End links to each other; The xc of display control module [25] ₀～xc ₇The xt of end and control module [27] ₀～xt ₇End links to each other, and the write gate signal rw end of display control module [25] links to each other the output terminal and LED[6 of display module [24] with the xrw end of control module [27]] be connected.

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