CN1723611A - Apparatus, methods and articles of manufacture for multiband signal processing - Google Patents

Abstract

Apparatus, methods and articles of manufacture are shown for modifying electromagnetic waves. Through using various wave characteristics such as amplitude to regulate a current source, a current is output that may be used in any number of ways, such as driving an antenna or other load.

Description

Be used for device, method and manufacturing clause that multi-wave signal is handled

Technical field

The present invention relates to power amplifier, more particularly, the present invention relates to the multiband power amplifier.

Background technology

Can be optimized the power amplifier that in transmitter, uses in order in specific pattern and frequency band, to make maximizing efficiency.Such optimization can make amplifier be biased in a certain mode.In addition, usually between the parts in amplifier and between amplifier and adjacent component, need to make impedance matching.

But owing to need some to be placed on communication system on the amplifier, difficulty has increased.For example, in W-CDMA or CDMA2000 transmitter, feed back signal by power amplifier traditionally with non-constant-envelope.But the optimum level that reaches the efficiency of amplitude and the linearity is difficult: design tradeoff way that often need be between the two.Moreover, need the power output of wide region: usually on the 80dB level.

Difficulty may increase along with the multiband transmitter in addition.For example, impedance depends on operating frequency, and therefore, the amplifier with the optimum impedance coupling on a frequency band will not be optimized to be used for the operation on the different frequency wave band.By providing independent amplifier chain (amplifying chain) can solve the problem of relevant impedance matching at the different frequency place.But independent amplification string may be expensive, has increased the volume of transmitter and has increased the transmitter desired power.

It is difficult that Amplifier Design and impedance matching further become, and this is because in present communication system, the expectation amplifier moves on the multi-frequency wave band.For example, transmitter can be used among GSM900 (880-915MHZ) and the DCS1800 (1710-1785MHZ wave band).As another example, transmitter can be used in CDMA800 (824-849MHZ) and CDMA1900 (1850-1910MHZ) frequency band.Usually, two waveband mobile phone transceiver comprises two power amplifiers, and each all operates in the single-frequency bandwidth, and each all needs impedance matching.

Prior art has attempted providing the solution for Amplifier Design and impedance matching difficulty.For example, Fig. 1 show a kind of prior art for two waveband single-stage power amplifier moves under 800MHz or 1900MHz in the trial aspect the impedance matching.A kind of single active equipment has the hindrance network 104 and 106 at input end, in amplifier 102, biasing control 103, voltage source 107, hindrance network 105 and hindrance network 108 and 110 of output, so that the input and output impedance of expectation to be provided.But, the needs of these hindrance networks have been raised the cost of equipment and have been reduced efficient.

Shown another kind of method of in dual band power amplifier, carrying out impedance matching among Fig. 2.Amplifier 214 is matched first match circuit 202.Second match circuit of being made up of two independent impedance networks 206 and 208 204 is tuned on each frequency bandwidth.This method needs two switches 210 and 212.This method has been raised the cost of equipment once more and has been reduced efficient equally.

The method of another kind of prior art is to ignore efficiency factor.For example, can use the inefficient level A operation match circuit that is used for multiband, single-stage power amplifier.In these circuit, the difference between the power gain of 800MHz and 1900MHz is very significant, is typically about 15dB.But if wish consistent power output, such as in 2.5G and 3G communication system, different input powers need be applied on the different amplifiers, and this can produce other difficult design.

Also have the method for another kind of prior art to provide multi-stage power amplifier.When comparing with the single-stage power amplifier, multi-stage power amplifier can be usually as expectation, and they can provide the input impedance of increase, the gain of increase and the power handling capability of increase.But realization up to the present shown in the multistage embodiment of all equipment as seen in Figure 1, has the difficulty of power drain (power drain) and equipment cost.For example, the prior art embodiments shown in Fig. 1 can be used in the multi-stage power amplifier.But, in such method, increased number such as the parts of impedance network and switch, therefore increased cost, size and the inefficiency of system.

Therefore, need a kind ofly can cross a plurality of frequency bands the low cost of appropriate output power, high efficiency multiband amplifier are provided.

Summary of the invention

The invention provides device, the method that is used for the multiband transmitter power and amplifies and make clause (articles of manufacture).In a preferred embodiment, provide at least one multiplying arrangement, this multiplying arrangement has input impedance matching circuit and compensates different input and output signal frequencies.In other embodiments, can provide a plurality of multiplying arrangements with input impedance matching circuit and inter-stage impedance matching circuit and output matching circuit.

Description of drawings

Fig. 1 describes a kind of dual-band device of prior art.

Fig. 2 describes a kind of dual-band device of prior art.

Fig. 3 shows a preferred embodiment.

Fig. 4 shows a preferred embodiment.

Fig. 5 shows a preferred embodiment.

Fig. 6 shows a preferred embodiment.

Fig. 7 shows a preferred embodiment.

Fig. 8 shows a preferred embodiment.

Fig. 9 shows a preferred embodiment.

Figure 10 shows a preferred embodiment.

Figure 11 shows a preferred embodiment.

Figure 12 shows a preferred embodiment.

Figure 13 shows a preferred embodiment.

Figure 14 shows the performance of a preferred embodiment.

Figure 15 shows the performance of a preferred embodiment.

Figure 16 shows the performance of a preferred embodiment.

Embodiment

The invention provides device, the method that is used for the multiband transmitter power and amplifies and make clause.Fig. 3 shows a preferred embodiment.Digital signal processor 10 comprises analog-to-digital converter 11, and it is by using rectangular coordinate or I, and the Q data are with the digitlization of multiband input signal.The right angle receives I then to polarity switch 12, Q data and its conversion (translate) become polar coordinates.For example, signal can adopt the form of R, P (sin) and P (cos), wherein the phase property of the amplitude characteristic of R coordinate representation signal and P (sin) and P (cos) coordinate representation signal.

Via transducer 13 along path a ^mConvert the amplification characteristic of input signal to digit pulse, wherein this digit pulse comprise be quantized into have highest significant position (" MSB ") to least significant bit (" LSB ") the position B ₀To B _N-1Numeric word.Numeric word can be a variable length in various embodiments.Usually, word is long more, and the accuracy of playback input signal is big more.Described numeric word is provided for the command signal or the control that decay and/or amplify in the following mode that will describe.Certainly, just as what further describe below, in other embodiments, with the derivation thing of other type of amplitude or other signal characteristic and/or supply with equally, can use the numeric words of different compositions.

In the embodiments of figure 3, seven control assembly line a have been shown away from transducer 13 ^m1-a ^m7.In a preferred embodiment, the number of these control assembly lines depends on the resolution (resolution) of word.In this preferred embodiment, word has 7 discrimination rates, and in order easily to observe Fig. 3, the control assembly line is merged into the single-pathway a that introduces among the control assembly 22a-g ^mBut, in the present embodiment, as being further described below, the control assembly line is not merged and is introduced into separately on the contrary in the control assembly.For example, if desired, the parts (not shown) also can be used to feed back on the amplitude characteristic by the correction (correction) of transducer 13 (for example look-up table etc.) with any hope.

Phase property is along path a ^pAdvance.Here, utilize digital to analog converter 18 and synthesizer 20 (it is voltage controlled oscillator in certain preferred embodiment) at first phase property to be modulated on the ripple.Synthesizer 20 provides the output wave of being made up of phase information.This output wave has constant envelope, and promptly it does not have changes in amplitude, and it also has the phase property of original incoming wave, and is delivered to driver 24, and is followed successively by drive wire a ^p1-a ^p7.

Time delay equalization circuit 35 provides synchronizing capacity for phase place and amplitude characteristic.Input impedance matching circuit 40 utilizes first multiplying arrangement 36 to mate the impedance of phase characteristic.Further describe the preferred embodiment of input impedance matching circuit 40 below.Any input impedance matching circuit of preferred embodiment should be mated the dynamic range that is used for compensating potential variation (may in the scope of 80dB) and is provided to the impedance that changes together in the signal of multiplying arrangement.

Output from multiplying arrangement 36 is fed back to inter-stage impedance matching circuit 41 then, wherein will recall, and should be output as the phase modulated parts of original input signal from multiplying arrangement 36.Further describe the preferred embodiment of inter-stage impedance matching circuit 41 below, and the preferred embodiment will be advanced among the transistor array 25a-g from the impedance matching of the variation output signal of multiplying arrangement 36.In case by transistor array 25a-g treated this signal, as will be described in further detail below, it is combined in the inlet wire 27, and transmits in the output impedance match circuit 42.Further describe the preferred embodiment of output impedance match circuit 42 below.

Turn back to the embodiment of Fig. 3 now, output impedance match circuit 42 will make in the output of transistor array 25a-g and the coupling of the impedance phase between any load.If load is antenna then can inserts band diplexer (band diplexer) here, so that be provided at the output among the various frequency bands.

Turn back to signal now and enter processing among the transistor array 25a-g, will remember to be that phase component is output from inter-stage impedance matching circuit 41.This signal is then at driver line a ^p1-a ^pCut apart among 7 and be fed among the current source 25a-25g, and will be used for drive current source 25a-25g potentially.

In the present embodiment, transistor can be used as current source 25a-25g.In addition, in other embodiments, suitably one or more transistors of segmentation can be used as current source 25a-25g.

Path a ^m(by aforesaid control assembly line a ^m1-a ^m7 form) terminate among the control assembly 22a-g.In specific preferred embodiment, those are switching transistor, and are preferably current source.Control assembly 22a-g quilt is switched according to the position of the numeric word of exporting from amplitude component and is therefore regulated according to the numeric word of exporting from amplitude component.If a position is " 1 " or " height ", then connect corresponding control assembly, so electric current flows to suitable current source 25a-g from this control assembly along biasing control line 23a-g.Therefore as what have been noted that above, the length of numeric word can change, and the number, control assembly, control assembly line, driver line, biasing control line, current source etc. of position can correspondingly change in various embodiments.Moreover, in various embodiments need be at the one among digital word resolution, parts, line and the current source.

If control assembly is for opening (on) then current source 25a-g from the control assembly received current, and therefore regulate each current source according to those parts.In specific preferred embodiment, suitable control assembly is provided to current source with bias current, and as described further below, and therefore this control assembly can be called as bias control circuit, and a large amount of bias control circuits is then as biasing networks.In certain embodiments, if necessary, can wish by using switching network statically or dynamically one or more bias control circuits to be assigned to one or more current sources.

Each current source is used as potential current source, and can produce electric current, and it is outputed to current source line 26a-g respectively.Each current source can maybe cannot serve as current source, and therefore can maybe cannot produce electric current, and this is because it is regulated by the digital word value of suitable command signal or regulation control part.The activation of any segmentation (segment), and from the generation of the electric current of that segmentation all depends on the value from the suitable position of the numeral of the amplitude component that is used to regulate suitable control assembly.Current source is not a multiplying arrangement or multiplying arrangement, and in a preferred embodiment, but a plurality of current source plays a multiplying arrangement, as described herein.Really, amplify and/or decay can be considered for the function of these embodiment in a preferred embodiment, and therefore multiplying arrangement and/or relaxation equipment can be considered for one and be used to the electronic unit that amplifies and/or decay.

Fig. 4 has shown another preferred embodiment.Here signal is translated into amplitude and phase component (component), as top described with reference to Fig. 3.The parts of identical numbering have been set forth in Fig. 3.The impedance that input impedance matching circuit 40 utilizes first multiplying arrangement 136 to mate phase property.Here, the expectation of first multiplying arrangement 136 is configured to make to have a magnification region, as the fractional value (fractional value) of the magnification region of transistor array 25a-g.First intervalve matching circuit 141 is provided at the impedance matching between first multiplying arrangement and second multiplying arrangement 137.The expectation of second multiplying arrangement 137 is configured to make to have a magnification region, and as the fractional value of the magnification region of transistor array 25a-g, it can be greater than first multiplying arrangement 136.Second intervalve matching circuit 142 is provided at the impedance matching between second multiplying arrangement 137 and the transistor array 25a-g.Second intervalve matching circuit 142 only provides the expectation coupling of half at this one-level place.By being separately positioned on driver line a ^p1-a ^p Intervalve matching circuit 143a-g on 7 provide second half.These circuit wish to be high pass or low pass filter.

After amplification or deamplification, output impedance match circuit 144a-g is provided at the impedance matching on each current source line 26a-g respectively.In other embodiments, can implement output matching circuit such as 144a-g.Output impedance match circuit 145 offers any load with coupling then, for example, and antenna multicoupler and antenna.Further describe the preferred embodiment of output impedance match circuit 145 below.

When the independent transistor in the array opened or closed, output impedance match circuit 144a-g provided a hindrance coupling array to increase the efficient of array.For example, for 1W power output and 3V supply voltage, utilize to equal (3V) with load resistance ²/ (2*1W)=4.5 ohm all crystals pipe of transistor output resistance conducting will be realized maximum efficient.If still, only having power output is the transistor 22g conducting of 7.8mW, then load resistance equals (3V) ²/ (2*7.8mW)=577 ohm.Therefore, if used single output impedance match circuit such as 145 in one embodiment, then it must mate 577 ohm largest transistor output resistance (load resistance is 50 ohm) here.Therefore, as following further described, can wish in this and other embodiment, to use switch output impedance match circuit.

Fig. 5 has shown another preferred embodiment.With frequency is f ₁And/or f ₂Signal be input to switch 324.Between the input signal that will amplify, switch for the switch 324 of high speed transistor in the present embodiment.Can use the control circuit (not shown) to determine bandwidth of operation (operating bandwidth).The effect that a plurality of multiplying arrangements 302,304 and 306 that equipment 300 utilizations are separated with 310 by inter-stage impedance matching circuit 308 have come multi-stage power amplifier.Multiplying arrangement is preferably transistor.Input impedance matching circuit 312 impedances of coupling between first multiplying arrangement 302 and input signal.314 impedances of coupling between last multiplying arrangement 306 and arbitrary load of output impedance match circuit.If load is an antenna, then can insert band diplexer (band diplexer) here, so that among various frequency bands, provide output.Should be noted that equally, in this or other preferred embodiment, can wish to mate simultaneously impedance equally at the different frequency place.

In this preferred embodiment, switch 324 is speed-sensitive switch or band diplexer.Switch 324 will depend on frequency band signal will be transmitted in the impedance matching circuit 312.Should be noted that it is to minimize from the impedance effect on the signal of the remainder of embodiment in order to make that switch is present in the present embodiment.That is to say that under the situation in the path that does not have conducting, " downstream " impedance on entering signal may influence the integrality and the systematic function of signal.But other embodiment can utilize other or not have input switch.

For different frequencies, 308 impedances of coupling between multiplying arrangement 302 and 304 of inter-stage impedance matching circuit.In a preferred embodiment, multiplying arrangement 304 is similar in appearance to multiplying arrangement 302.Similarly, in a preferred embodiment, inter-stage impedance matching circuit 310 and multiplying arrangement 306 are respectively similar in appearance to inter-stage impedance matching circuit 308 and multiplying arrangement 304.The value of impedance certainly,, electric capacity and resistance can be different among parts.

The various levels of embodiment by Fig. 5, and really in all preferred embodiments, some losses are acceptable.That is to say,, the impedance matching less than the best can take place for by input impedance matching circuit 312, multiplying arrangement 302,304 and 306 and the dual band frequencies of inter-stage impedance matching circuit 308 and 310.A plurality of multiplying arrangements by present embodiment compensate any such loss.In can comprising other embodiment of more or less grade, the some of these grades can have standby impedance matching equipment, as known in the prior art.For example, in three standby stage power amplifier embodiment, can be with second impedance matching circuit, for example, the similar circuit of output impedance match circuit to the embodiment of Fig. 7-10 offers intergrade.

The embodiment of Fig. 3 to 5 can be implemented on a semiconductor equipment, expects that here this semiconductor equipment is for such as integrated circuit (IC) or specific to integrated circuit (ASIC) synthetic (composition) of application program; Some examples comprise silicon (Si), germanium silicide (SiGe) or GaAs (GaAs) substrate.The output impedance match circuit 145 of Fig. 4 can be realized separately from IC or ASIC, still, depends on its structure, and various embodiment are further described as following reference.

Forward Fig. 6 to, shown a preferred embodiment of input impedance matching circuit.In the preferred embodiment, this circuit is used as the inter-stage impedance matching circuit equally.This circuit comprises the series connection rlc circuit that is used to be received in the input on the direction a.This circuit be particularly suitable for broadband operation (as preferred embodiment).Certainly, in other embodiments, can use other circuit, such as low pass or high pass ladder filter (ladder filter).

Fig. 7 has shown a kind of embodiment that more high efficiency switch output impedance match circuit can be provided.For example, though the single ON transistor in the array 25a-g of Fig. 3 or 4 can mate 50 ohm load, two ON transistors will have whole output impedance (50 ohm/2=25 ohm), and this is in parallel because of them.Therefore, need different output impedance matching conditions.Similarly, suppose 50 ohm load, therefore then N transistor will have the whole output impedance of 50/N that is, and switch output impedance match circuit should have the impedance matching ability of X/N, and the X output impedance that equals to expect here and N equal the transistorized quantity in the array.Bias voltage V _Bias1And V _Bias2Capacitance is offered variable capacitance diode (varactor) 350 and 351.Capacitor 355,356 and 357 is DC block-condensers; Resistor 360 and 361 expectations are big to stoping RF to leak.Transmission line 365 be one provide inductive impedance less than quatrter-wavelength line.Because the use of the embodiment among parts that these are additional and the above-mentioned non-linear embodiment, these parts need be calibrated at first, for the efficient of maximum, can use switch or p-i-n diode to do these parts.

Fig. 8 has shown the another kind of embodiment that more high efficiency switch output impedance match circuit can be provided.Here, four single switch 380-383 and four capacitor 390-393 mate impedance.Transmission line 395 be one provide inductive impedance less than quatrter-wavelength line.The quantity of noticing the input in this and other embodiment can determine that parts form.For example, if have realization this embodiment (such as top described) within seven transistorized embodiment with reference to Fig. 3, then can wish to use less parts, three capacitors for example, since they will for seven possible outputs (that is, here 50/N=50/1,50/2 ..., 50/7) coupling that needs is provided.Capacitor 390-393 is a matching capacitor.Because the use of the embodiment among parts that these are additional and the above-mentioned non-linear embodiment, these parts can be calibrated at first, for maximal efficiency, can use switch or p-i-n diode to do these parts.

Should be noted that there is no need provides maximal efficiency in output, and therefore accurately coupling impedance in a preferred embodiment, up to the present, the transistor in the array of preferred embodiment is as current source, rather than voltage source.

Turn back to Fig. 9 now, shown another embodiment of output impedance match circuit.Be used for the certain preferred embodiment of wideband transmit, just as what may see in the embodiment of Fig. 3 to 5, the output impedance coupling in this one-level is used the parallel circuit laod network.According to the appropriate value of the remainder of embodiment, with this parallel circuit laod network be tuned to be used for the particular value of impedance, electric capacity and resistance.Laod network is made up of resonant circuit 501, and this resonant circuit 501 comprises that capacitor 501C, resistor 501R (having resistance R) and load 501R2 (have resistance R _L), parallel short circuited transmission 502 and quarter-wave transmission line 503.Parallel short circuited transmission 502 and parallel capacitor 501C with ${\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="A20038010537600241.png,A20038010537600242.png"\; state="\{\{state\}\}">f</figure-callout>}}_0=\sqrt{f_1{f}_2}$ Centre frequency provide inductive impedance, f here ₁Be low bandwidth frequency and f ₂Be the high bandwidth frequency.

Certainly, the inductive impedance of laod network can be different with different frequencies.Usually, determine by following formula:

Z _net1＝R/(1-jtan34.244°)

Here R be required output resistance and $R_L=Z_{01}^2/R$ 。Any impedance on higher order resonances all should be capacitive.

In specific preferred embodiment, can define the optimum load network parameter by following formula:

$\tan \mathrm{\&theta;}=0.732\frac{\mathrm{<figure-callout\; id="0"\; label="R\; Z"\; filenames="A20038010537600241.png,A20038010537600242.png"\; state="\{\{state\}\}">R</figure-callout>}}{Z_{}},C=\frac{0.685}{\mathrm{\&omega;R}},R=1.365\frac{V_{\mathrm{cc}}^2}{P_{\mathrm{ouyt}}}$

Here V _CcBe supply voltage, P _OutBe power output, Z ₀With θ is respectively to walk abreast to lack the characteristic impedance and the electrical length of circuited transmission 502.

Capacitor C be internal unit electric capacity (though some outside output capacitances can exist equally, and correspondingly should multiply each other with the factor express (factor)), known is that it is selected for suitable frequency in this area.For example, if the output impedance match circuit is a bipolar device, then will utilize collector electrode (collector) electric capacity.As another example,, will utilize capacitance of drain so if the output impedance match circuit is the FET transistor.

Quarter-wave transmission line 503 will have impedance Z ₀₁Electrical length with 0=90 °.Quarter-wave transmission line 503 can be counted as the high frequency series resonant circuit and widen whole frequency range effectively.In other embodiments, certainly, other method of the prior art can be used equally, or according to need not.

Shown an alternative example among Figure 10.Here, the quarter-wave transmission line 503 of Fig. 9 is replaced by two electric capacity 602 and 604 and than short transmission line 606.The parameter of parts is defined by following formula:

$Z_{02}=\frac{Z_{01}}{\sin {\mathrm{\&theta;}}_2}$

See another alternative embodiment among Figure 11.By about 5 ohm order, when output impedance hour, this embodiment preferably is used among the embodiment of broadband.Two L section converters 701 and 702 that will have series transmission lines and parallel electric capacity are increased among the embodiment shown in Figure 11.

Certainly, other embodiment can use other output impedance match circuit, for example, and low pass ladder filter.

A preferred embodiment that has shown the band diplexer of forming by high pass and low pass filter among Figure 12.Such an embodiment makes any insertion loss minimum among the switch type embodiment, shown in Fig. 5.High pass filter 1100 comprises inductor 1102 and capacitor 1104 and 1106.Low pass filter 1111 comprises inductor 1108 and 1110 and capacitor 1112.Also in another embodiment, inductor can be substituted and capacitor can be replaced by open electric circuit short-term (open-circuit stub) by the short transmission line with high characteristic impedance.

Perhaps, also in another embodiment, can avoid utilizing quarter-wave or half-wavelength transmission line to form band diplexer, as shown in Figure 13.In the present embodiment, length of transmission line l1 and l2 are the quarter-wave at 800MHz place so that protect high frequency channel to avoid the low frequency signal interference, on the contrary length of transmission line l ₃And l ₅For the quarter-wave at 1900MHz place is disturbed so that the protection low frequency channel is avoided high-frequency signal.In order to reduce or eliminate the coupling of any extra needs, length l ₃Be selected to realize having the parallel equivalent electric circuit of open electric circuit short-term, that is, and whole length l ₂+ l ₃Should be the half-wavelength of 1900MHz, same whole length l ₅+ l ₆Should be the half-wavelength of 800MHz.Series transmission lines preferably has 50 ohm characteristic impedance.

As another embodiment, one or more notch filters can be used within output impedance match circuit or the band diplexer, and any not desired frequency therefore further decays.For example, in the embodiment of CDMA800/CDMA1900, wish the second harmonic at 840MHz bandwidth place is suppressed.This harmonic wave will be in the power amplifier frequency bandwidth, and therefore should be attenuated.Therefore can use notch filter (notch fi1ter).

Figure 14 has shown the multiband that is used for small parameter signal S (2,1), the performance of multi-stage power amplifier apparatus embodiments.820 to 1910MHz frequency range has shown the power gain skew of the approximate 7dB of this characteristic frequency.

Figure 15 and 16 has shown the multiband that is used for large-signal, the performance of multi-stage power amplifier apparatus embodiments.Figure 15 has shown two signal S that are used at 840MHz and 1880MHz (being respectively the midbandwidth frequency of CDMA 800 and CDMA 1900) ₃And S ₄Power output.Figure 16 has shown two signal S that are used at 840MHz and 1880MHz (being respectively the midbandwidth frequency of CDMA 800 and CDMA 1900) ₅And S ₆The efficient that increases of power.Just as can be seen, this embodiment provides the similar power output and the efficient (more than 45%) of power increase.

Can use embodiments of the invention in pairs and with other multiband structure.The example of dual-band topology is GSM900/DCS1800 or CDMA800/CDMA1900.The triband example of structure is GSM900/DCS1800/PCS1900 or CDMA800/CDMA1900/PCS1900.

Various types of system configurations can be used for constructing embodiments of the invention.Those skilled in the art will correspondingly understand, and embodiments of the invention or its various parts and/or feature can wholely be made up of maybe hardware, software can be the combination of software and hardware.Though described the present invention by illustrative embodiment, additional advantage and modification will exist those skilled in the art.Therefore, the present invention is shown in be not limited to here aspect its broad and the specific detail of describing.Under the situation that does not break away from the spirit and scope of the present invention, can make modification.Therefore, be intended that and the invention is not restricted to this specific illustrative embodiment, and can be explained within the spirit and scope completely of claims and their equivalent.

Claims (29)

1. one kind is used to the method for amplifying or decaying, and comprising:

Input signal is provided;

At least one first non-linear current source and at least one second non-linear current source are provided;

When it provides described input signal, come the impedance of described first and second non-linear current source is mated by input impedance matching circuit;

Any electric current that is produced by described first and second non-linear current source is made up, so that produce the linear amplification or the decay of described input signal.

2. method according to claim 1, wherein, described input signal also comprises the phase characteristic of importing waveform.

3. one kind is used to the method for amplifying or decaying, and comprising:

The input signal of first bandwidth is provided;

The input signal of second bandwidth is provided;

Input impedance matching circuit is provided;

First multiplying arrangement is provided;

The inter-stage impedance matching circuit is provided;

Second multiplying arrangement is provided;

Wherein when the described input signal of the described input signal of first bandwidth or second bandwidth is delivered to described input impedance matching circuit, described circuit utilizes described first multiplying arrangement that impedance is mated, and when the described input signal of the described input signal of first bandwidth or second bandwidth was delivered to described second multiplying arrangement, described inter-stage impedance matching circuit utilized described second multiplying arrangement that impedance is mated.

4. method according to claim 3 also comprises: via the output impedance match circuit impedance when from the output of described second multiplying arrangement is mated.

5. method according to claim 3, wherein, described input signal also comprises the phase characteristic of importing waveform.

6. amplification method comprises:

A plurality of multiplying arrangements are provided;

One or more inter-stage impedance matching circuits are provided, and each in these one or more inter-stage impedance matching circuits is all between two in these a plurality of multiplying arrangements;

The output impedance match circuit is provided, and last the signal that comes from these a plurality of multiplying arrangements passes this output impedance match circuit; And

Last that is provided in will these a plurality of multiplying arrangements is connected to the band diplexer of load.

7. method according to claim 6, wherein, at least one in described one or more inter-stage impedance matching circuits also comprises rlc circuit.

8. method according to claim 6, wherein, described output impedance match circuit also comprises the parallel circuit laod network.

9. method according to claim 6, wherein, described output impedance match circuit also comprises switch output impedance match circuit.

10. method according to claim 6, wherein, described at least one at least one in described a plurality of multiplying arrangements is field-effect transistor.

11. method according to claim 6, wherein, described at least one at least one in described a plurality of multiplying arrangements is bipolar transistor.

12. method according to claim 6 also comprises: produce power output.

13. method according to claim 6 also comprises: produce for the substantially the same power output of a plurality of operating frequencies.

14. method according to claim 6 also comprises: simultaneously the impedance at the different frequency place of described input signal is mated.

15. one kind is used to the device that amplifies or decay, comprises:

At least one first non-linear current source and at least one second non-linear current source;

Input impedance matching circuit is used for when when it provides input signal the impedance of described first and second non-linear current source being mated;

Wherein, any electric current that is produced by described first and second non-linear current source is made up, so that produce the linear amplification or the decay of described input signal.

16. device according to claim 15, wherein, described input signal also comprises the phase characteristic of importing waveform.

17. one kind is used to the device that amplifies or decay, comprises:

Be used to provide the device of the input signal of first bandwidth;

Be used to provide the device of the input signal of second bandwidth;

Input impedance matching circuit;

First multiplying arrangement;

The inter-stage impedance matching circuit;

Second multiplying arrangement;

Wherein, when the described input signal of the described input signal of first bandwidth or second bandwidth is delivered to described input impedance matching circuit, described circuit utilizes described first multiplying arrangement that impedance is mated, and when the described input signal of the described input signal of first bandwidth or second bandwidth was delivered to described second multiplying arrangement, described inter-stage impedance matching circuit utilized described second multiplying arrangement that impedance is mated.

18. device according to claim 17 wherein, via the output impedance match circuit, mates impedance when from the output of described second multiplying arrangement.

19. device according to claim 17, wherein, described input signal also comprises the phase characteristic of importing waveform.

20. one kind is used to the device that amplifies or decay, comprises:

A plurality of multiplying arrangements;

One or more inter-stage impedance matching circuits, each in these one or more inter-stage impedance matching circuits is all between two in these a plurality of multiplying arrangements;

The output impedance match circuit, last the signal that comes from these a plurality of multiplying arrangements passes this output impedance match circuit; And

Band diplexer, last that is used for these a plurality of multiplying arrangements is connected to load.

21. device according to claim 20, wherein, at least one in described one or more inter-stage impedance matching circuits also comprises rlc circuit.

22. device according to claim 20, wherein, described output impedance match circuit also comprises the parallel circuit laod network.

23. device according to claim 20, wherein, described output impedance match circuit also comprises switch output impedance match circuit.

24. device according to claim 20, wherein, described at least one at least one in described a plurality of multiplying arrangements is field-effect transistor.

25. device according to claim 20, wherein, described at least one at least one in described a plurality of multiplying arrangements is bipolar transistor.

26. device according to claim 20 also comprises: via in described a plurality of multiplying arrangements described last produce power output so that be input to described band diplexer.

27. device according to claim 20 also comprises: via in described a plurality of multiplying arrangements described last produce for the substantially the same power output of a plurality of operating frequencies, so that be input to described band diplexer.

28. device according to claim 20, wherein, described one or more inter-stage impedance matching circuits each all between two in these a plurality of multiplying arrangements; And described output impedance match circuit carries out impedance matching simultaneously with the different frequency of described input signal.

29. an integrated circuit that is used for Electromagnetic Treatment comprises:

A plurality of multiplying arrangements;

One or more inter-stage impedance matching circuits, each in these one or more inter-stage impedance matching circuits is all between two in these a plurality of multiplying arrangements.

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