CN1722360A - Design method for integration super-current power unit structure of small conduction resistance - Google Patents
Design method for integration super-current power unit structure of small conduction resistance Download PDFInfo
- Publication number
- CN1722360A CN1722360A CN 200410104298 CN200410104298A CN1722360A CN 1722360 A CN1722360 A CN 1722360A CN 200410104298 CN200410104298 CN 200410104298 CN 200410104298 A CN200410104298 A CN 200410104298A CN 1722360 A CN1722360 A CN 1722360A
- Authority
- CN
- China
- Prior art keywords
- cellular
- annular
- resistance value
- plies
- designing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
This invention relates to a method for designing the integrated great current power device structure with small conducting mass resistivity, which comprises the following steps: pressure resistance designing the current operation unit of said device, figuring out the unit 's size, interval and terminal structure; transforming the former unit into annular unit; figuring out the device buried layer and resistance value of unit length; making equivalent circuit of the device and charting it; charting the annular unit layer and correlative curve between the layer and its relative device mass resistivity; figuring out proper power parallel unit size and shape; in parallel linking the power unit and repeating to get structure layout of the said device. Compared with the present designing method, the invention has better design performance, and more economical property.
Description
(1) technical field
The present invention relates to a kind of power device (power transistor) structure Design method that integrated circuit is made that is used for, particularly about a kind of integration super-current power unit (power transistor) structure Design method of small conduction resistance, the structure of such power device (power transistor) is usually used in the smart-power IC manufacturing.The present invention for convenience of description, unification abbreviates " device " as with described " power device (power transistor) " in its application documents.
(2) background technology
In the big electric current compatible integrated circuit of high-low pressure is made, usually need one or more power transistors, it is power device, and these power devices are usually integrated with low-voltage control circuit, owing to be subjected to the restriction of technology, generally can only draw lead from integrated circuit surface, at electric current hour, can not exert an influence to integrate circuit function and reliability, but under big electric current, when requiring less power device conducting resistance, effective die area of integrated circuit and power characteristic and circuit manufacturing cost have very big relation.At present, power device (power transistor) during most power integrated circuit is made is the vertical and horizontal hybrid conductives, general current path all is to flow to buried regions by active layer (epitaxial loayer) or more low-doped device layer, again by the buried regions transverse conductance, flows out device.Existing device architecture described in Fig. 1,2,3 is analyzed, can find out, be on Semiconductor substrate 1, to selectively form highly doped low resistivity buried layer 2, form device active layer 3 by extension (also can pass through wafer bonding attenuate mode), form low-resistance conductive region 4 by the phosphorus penetrating method, adopt general semiconductor technology to produce the current processing cellular 5 that meets requirement of withstand voltage, leak base stage, the emitter stripes champion born of the same parents of cellular and bipolar power transistor as the VDMOS source.When designing these devices, normally adopt the VDMOS method for designing that described cellular is carried out withstand voltage design, determine cellular size, cellular spacing and the terminal structure of suitable current processing cellular.These devices will produce some problems when laterally very roomy (area is very big): promptly along with the increase of area, the conduction resistance of device also increases thereupon.The unrestricted increase of the conduction resistance of limiting device for how, at present, the method for designing report that this respect is not also arranged both at home and abroad as yet, general method is to adopt dual mode to carry out Design Treatment, a kind of is the size that design result is not known the device conduction resistance, and another kind is to ignore the contribution of buried regions to the device conduction resistance.This dual mode all produces defective to power device manufacturing structure design, and when integrated circuit required the very big and conducting resistance of power device electric current very little, the operating efficiency of device will have substantial degradation.For example, device architecture about withstand voltage 100V, buried regions and epitaxial loayer (active layer) resistance per unit length ratio is 100, the cellular number of plies was at 10～100 o'clock, different methods for designing will be brought 1～5 times area utilization difference, if power device accounts for 80% (usually big current power integrated circuit is not always the case) of whole integrated circuit area in the integrated circuit, then may cause 80%～400% area utilization difference.
(3) summary of the invention
Technical problem to be solved by this invention is to provide the method for designing of the integration super-current power unit structure of better, the more economical small conduction resistance of a kind of design performance, can control the conduction resistance of the super-current power unit structure in the power integrated circuit when making design, improve area utilization.
The technical scheme that the present invention solves the problems of the technologies described above is: the current processing cellular to described power device carries out withstand voltage design, determines cellular size, cellular spacing and the terminal structure of original cellular, and described method for designing also comprises step:
(1) described original cellular is carried out the annular processing, be converted to corresponding annular cellular;
(2) determine the buried regions resistance per unit length value and the active layer resistance per unit length value of described device;
(3) carry out the circuit equivalent of described device architecture according to described annular cellular current path, draw the equivalent circuit diagram of described device;
(4) draw the annular cellular number of plies of described device and the relation curve between the conduction resistance value corresponding with it;
(5) determine machinable power cell size (the annular cellular number of plies) in parallel, shape according to the circuit performance requirement and the machined parameters ability of described device;
(6) described power unit in parallel is connected by its parallel way and repeat, determine the domain structure layout of described device.
Original cellular annularization processing method of the present invention comprises:
(1) determines its axial symmetry and center symmetric points according to described device plane figure with respect to original cellular current path;
(2) under the constant situation of the cellular size, the cellular spacing that guarantee described original cellular, be the center, described original cellular be converted to the described annular cellular that is concentric ring with described symmetric points.
The present invention draws the annular cellular number of plies of described device and the method for the conduction resistance value relation curve corresponding with it comprises:
(1) calculates the girth of determining described every layer of annular cellular;
(2) calculate active layer resistance value and the buried regions resistance value of determining corresponding to described every layer of annular cellular;
(3) equivalent circuit diagram according to described device calculates resistance value between definite described device electrode;
(4) calculate the device conduction resistance value of determining corresponding to the described annular cellular number of plies;
(5) being variable with the described annular cellular number of plies, as abscissa, is ordinate with the conduction resistance value corresponding to the annular cellular number of plies, draws out the graph of relation between the described annular cellular number of plies and the device conduction resistance value corresponding with it;
The present invention is determined by the merchant of the girth of described active layer resistance per unit length value and buried regions resistance per unit length value and corresponding described annular cellular respectively corresponding to the active layer resistance value of described every layer of annular cellular and buried regions resistance value.
Device conduction resistance value of the present invention by and the corresponding device electrode that forms by described active layer and buried regions of the described annular cellular number of plies between resistance value and determine with the long-pending of the corresponding device area of the described annular cellular number of plies.
Beneficial effect of the present invention.Because the present invention adopts technique scheme, described power device current processing cellular is carried out the reasonable annularization processing of corresponding equivalence, and formed the equivalent circuit diagram of device architecture and the cellular number of plies and and the corresponding device conduction resistance of cellular number of plies value between graph of relation, thereby the size of the conduction resistance value of super-current power unit in the control integrated circuit effectively, the size of the current processing cellular in the control device manufacturing structure (the cellular number of plies), shape, form the power of optimizing unit in parallel, improve the area utilization of power device in the integrated circuit, generally can improve 1～5 times area utilization.Therefore, method of the present invention is that a kind of existing method for designing than similar device architecture has the better and more economical integration super-current power unit structure method for designing of design performance.Certainly, the inventive method also can be used to separate the design of super-current power unit manufacturing structure.
(4) description of drawings
Fig. 1 is the schematic diagram of an integrated power unit structure of existing employing epitaxy method;
Fig. 2 is the schematic diagram of existing VDMOS power unit structure, and wherein (a) is its plane graph, (b) is its A-A generalized section;
Fig. 3 is the schematic diagram of existing BJT power unit structure, and wherein (a) is its plane graph, (b) is its B-B generalized section;
Fig. 4 carries out the original cellular of Fig. 2, Fig. 3 the annular cellular floor map that obtains after the annularization processing with the inventive method;
Fig. 5 is power unit in parallel and the whole power device plane figure schematic diagram with the power device of the inventive method acquisition, and wherein (a) is power cell schematics in parallel, (b) is whole power device plane figure schematic diagram;
Fig. 6 is that the inventive method is carried out the device equivalent circuit diagram that circuit equivalent obtains according to Fig. 1, Fig. 2, Fig. 3, Fig. 4;
Fig. 7 be a kind of power device of obtaining of the inventive method the annular cellular number of plies and and its corresponding device conduction resistance value between graph of relation;
Fig. 8 is the inventive method step block diagram.
(5) embodiment
The specific embodiment of the present invention is not limited only to following description, can obtain other similar techniques solutions according to the principle of the technology of the present invention design.
Below, with the VDMOS among Fig. 2, Fig. 3 and BJT power device explanation the inventive method, in order to give top priority to what is the most important, the grid and the base stage of VDMOS among Fig. 2, Fig. 3 and BJT device are not drawn, the number of its source and emitter cellular (current processing cellular) 5 is just signal also, the number that actual cellular number is described in the schematic diagram, leakage among the figure and collector electrode 4 (being made of foregoing low resistance conduction region and buried regions, therefore here still to number 4 expressions) are made as single annular.Here be that example further specifies with the VDMOS device, the inventive method at first is to adopt general VDMOS method for designing well-known to those skilled in the art to carry out the withstand voltage design of described power device current processing cellular (original cellular) 5, determines cellular size, cellular spacing and the terminal structure of described original cellular 5.The layout of original cellular 5 can be square or rectangle, circle etc., in order to simplify description, is square layout among the figure.
In the cellular size of determining described original cellular 5 as stated above, after cellular spacing and the terminal structure, described original cellular 5 is carried out reasonably annularization processing, so that carry out relevant calculation, promptly according to described device plane figure definite axial symmetry and center symmetric points with respect to original cellular 5 current paths, for square, the device of circular flat pattern layout, easily determine its symmetric points, device for the rectangular planes pattern layout, with its diagonal intersection point is symmetric points, in cellular size (the conducting size that guarantees described original cellular 5, thickness etc.), under the constant principle of cellular spacing, the original cellular 5 of described device is carried out corresponding reasonable annularization processing, be equivalent to the original cellular 5 of the general other than ring typeization of original design, be the cellular 5 of the original other than ring typeization that designs by universal method the center with determined symmetric points just, become be converted to accordingly be concentric ring annular cellular 5 (as shown in Figure 4, because the cellular before and after the annularization processing is corresponding, so still to number the annular cellular of 5 expressions), calculate the power of determining described device unit 6 in parallel according to the Fig. 4 that is obtained after this conversion and optimize the equivalent circuit diagram (see figure 6) of size (see figure 5) and device architecture and carry out relevant calculating.
The active layer resistance per unit length value of the buried regions resistance per unit length value of buried regions 2 of the present invention and active layer (epitaxial loayer) 3 is determined by following method, Ra among Fig. 1, Rb represent described active layer resistance per unit length and buried regions resistance per unit length respectively, are constant to its resistance value of same device.
Active layer resistance per unit length Ra (see figure 1) is from the vertical resistance on buried regions 2 directions of silicon chip surface, among Fig. 2 (b), Fig. 3 (b) perpendicular to the resistance per unit length on the paper direction.Its resistance value can be by Ra=ρ LS
-1Approximate calculation obtains, wherein ρ is the resistivity (being determined by epitaxial film materials usually) of active layer 3, L is described annular cellular 5 thickness, and S is that annular cellular 5 unit lengths described in the active layer 3 [among Fig. 2 (b) perpendicular on the paper direction] are amassed with described annular cellular 5 effective conducting sizes are.For example, if the resistivity of epitaxial loayer 3 is 2 Ω cm, annular cellular 5 thickness are 10 μ m, annular cellular 5 effective conducting size 10 μ m, cellular 5 is 1 μ m perpendicular to unit length on Fig. 2 (b) paper direction, then Ra=2 Ω cm * 10 μ m ÷ (1 μ m * 10 μ m)=20000 Ω.
Buried regions resistance per unit length Rb (see figure 1) is the value of the resistance of the buried regions contribution between the two-layer annular cellular 5 when getting unit length on the device widths direction, among Fig. 2 (b), Fig. 3 (b) perpendicular to the resistance per unit length on the paper direction.This resistance value can be by Rb=R
sLW
-1Approximate calculation is definite, wherein R
sBe buried regions square resistance (being determined by the buried regions material) that L is cellular 5 spacings, W is cellular 5 unit lengths [Fig. 3 (b) is perpendicular on the paper directions].For example, establishing the buried regions square resistance is 20 Ω/, and cellular 5 spacings 10 μ m are 1 μ m perpendicular to the unit length on Fig. 3 (b) paper direction, then Rb=20 Ω/ * 10 μ m ÷, 1 μ m=200 Ω.
The equivalent circuit diagram of device architecture of the present invention carries out circuit equivalent by the current path direction (identical with original cellular current path) of described annular cellular 5 and is depicted as, and as shown in Figure 6, is that symmetric points are drawn with source end starting point.Ra1, Ra2 among Fig. 6 ..., Ran represents in the described active layer equivalent resistance corresponding to each annular cellular 5 that converts to, i.e. active layer resistance; Rb1, Rb2 ..., Rbn is illustrated in the buried regions equivalent resistance corresponding to each annular cellular 5 that converts to, i.e. buried regions resistance.Rds1, Rds2 ..., Rdsn represents to see by the direction of arrow among Fig. 6 (from left to right) equivalent resistance of circuit network in the past, is approximate resistance value between the VDMOS device source is leaked.Correlation computations be can carry out according to Fig. 6, the cellular number of plies of annular cellular 5 of described power device and the relation curve between corresponding conduction resistance value obtained.Its method is as follows:
(1) calculates the girth of determining described every layer of annular cellular 5.If described annular cellular 5 is a square annular structure (as shown in Figure 4), but this does not lose generality.Little square cellular begins to calculate from the center of Fig. 4, because the annular cellular at center is very little, entire device is calculated influence not quite.If first square annular cellular length of side of center is H
1, then girth is 4H
1, the length of side of second annular cellular of square is H
1+ 2L
b, L herein
bBe the annular cellular repetition interval of described square (referring to described cellular conducting size and cellular spacing sum), the length of side of the 3rd the annular cellular of square is H
1+ 2 (1+1) L
b..., the length of side H of n (layer) square annular cellular
nBe H
1+ 2 (1+n) L
bCan calculate the girth of determining each (every layer) described annular cellular thus.For other shapes,, also can adopt similar approach to calculate by girth formula separately as rectangle, circular ring-shaped cellular.
(2) calculate definite active layer resistance R an and buried regions resistance R bn corresponding with described every layer of annular cellular.Ran is definite divided by the merchant of the girth of respective annular cellular layer by the value of described active layer resistance per unit length Ra, and Rbn is definite divided by the merchant of the girth of respective annular cellular layer by the value of described buried regions resistance per unit length Rb.
(3) equivalent circuit diagram according to Fig. 6 calculates resistance value Rdsn between definite described VDMOS device source leakage.Can obtain following stepping type from Fig. 6:
(4) calculate the device conduction resistance value of determining corresponding to the described annular cellular number of plies.Device conduction resistance value by and the corresponding device source that forms by described active layer and buried regions of the described annular cellular number of plies leak between resistance value and determine with the long-pending of the corresponding VDMOS device area of the described annular cellular number of plies, promptly by Rdsn on duty with the Rdsn corresponding annular cellular number of plies under the area of VDMOS device just obtain device conduction resistance value corresponding to this annular cellular number of plies.Computational tool can adopt the Excel of Microsoft or oneself compile a program and calculate.See Table 1 (calculate with Excel, establishing the cellular repeat size is 20 μ m, and original position is 10 μ m).
The length of side that is the corresponding annular cellular with the corresponding VDMOS device area of the described annular cellular number of plies multiply by the length of side long-pending (square annular cellular).For the annular cellular of other shapes, as rectangle, circle, its device area corresponding to the cellular number of plies can calculate definite with planimeter formula separately.
Table 1
| Cellular number of plies n goes in ring | Original position (μ m) | Cellular repetition interval Lb (μ m) | Active layer resistance per unit length Ra (Ω) | Buried regions resistance per unit length Rb (Ω) | Square loop length of side Hn (μ m) | Ran (Ω) | Rbn (Ω) | Rdsn (Ω) | Conduction resistance (Ω .cm2) |
| 0 | 10 | 20 | 20000 | 200 | 40 | 500 | 5 | 125.31 | |
| 1 | 10 | 20 | 20000 | 200 | 120 | 166.67 | 1.667 | 55.943 | 0.503483775 |
| 2 | 10 | 20 | 20000 | 200 | 200 | 100 | 1 | 31.684 | 0.792103511 |
| 3 | 10 | 20 | 20000 | 200 | 280 | 71.429 | 0.714 | 20.464 | 1.002748414 |
| 4 | 10 | 20 | 20000 | 200 | 360 | 55.556 | 0.556 | 14.373 | 1.164225141 |
| 5 | 10 | 20 | 20000 | 200 | 440 | 45.455 | 0.455 | 10.702 | 1.294929727 |
| 6 | 10 | 20 | 20000 | 200 | 520 | 38.462 | 0.385 | 8.3195 | 1.405993771 |
| 7 | 10 | 20 | 20000 | 200 | 600 | 33.333 | 0.333 | 6.6859 | 1.504320227 |
| 8 | 10 | 20 | 20000 | 200 | 680 | 29.412 | 0.294 | 5.5167 | 1.594335183 |
| 9 | 10 | 20 | 20000 | 200 | 760 | 26.316 | 0.263 | 4.6509 | 1.678962671 |
| 10 | 10 | 20 | 20000 | 200 | 840 | 23.81 | 0.238 | 3.9913 | 1.760180954 |
| 11 | 10 | 20 | 20000 | 200 | 920 | 21.739 | 0.217 | 3.477 | 1.839351964 |
| 12 | 10 | 20 | 20000 | 200 | 1000 | 20 | 0.2 | 3.0679 | 1.917423849 |
| 13 | 10 | 20 | 20000 | 200 | 1080 | 18.519 | 0.185 | 2.7367 | 1.995059914 |
| 14 | 10 | 20 | 20000 | 200 | 1160 | 17.241 | 0.172 | 2.4646 | 2.072723329 |
| 15 | 10 | 20 | 20000 | 200 | 1240 | 16.129 | 0.161 | 2.238 | 2.150734359 |
| 16 | 10 | 20 | 20000 | 200 | 1320 | 15.152 | 0.152 | 2.0471 | 2.229309983 |
| 17 | 10 | 20 | 20000 | 200 | 1400 | 14.286 | 0.143 | 1.8846 | 2.308591919 |
| 18 | 10 | 20 | 20000 | 200 | 1480 | 13.514 | 0.135 | 1.7448 | 2.388666813 |
| 19 | 10 | 20 | 20000 | 200 | 1560 | 12.821 | 0.128 | 1.6237 | 2.469580994 |
| 20 | 10 | 20 | 20000 | 200 | 1640 | 12.195 | 0.122 | 1.5178 | 2.551351406 |
| 21 | 10 | 20 | 20000 | 200 | 1720 | 11.628 | 0.116 | 1.4245 | 2.633973771 |
| 22 | 10 | 20 | 20000 | 200 | 1800 | 11.111 | 0.111 | 1.3419 | 2.717428731 |
| 23 | 10 | 20 | 20000 | 200 | 1880 | 10.638 | 0.106 | 1.2683 | 2.801686483 |
| 24 | 10 | 20 | 20000 | 200 | 1960 | 10.204 | 0.102 | 1.2023 | 2.886710289 |
| 25 | 10 | 20 | 20000 | 200 | 2040 | 9.8039 | 0.098 | 1.1428 | 2.972459118 |
| 26 | 10 | 20 | 20000 | 200 | 2120 | 9.434 | 0.094 | 1.089 | 3.058889632 |
| 27 | 10 | 20 | 20000 | 200 | 2200 | 9.0909 | 0.091 | 1.04 | 3.145957666 |
| 28 | 10 | 20 | 20000 | 200 | 2280 | 8.7719 | 0.088 | 0.9953 | 3.233619312 |
| 29 | 10 | 20 | 20000 | 200 | 2360 | 8.4746 | 0.085 | 0.9543 | 3.321831707 |
| 30 | 10 | 20 | 20000 | 200 | 2440 | 8.1967 | 0.082 | 0.9166 | 3.410553576 |
| 31 | 10 | 20 | 20000 | 200 | 2520 | 7.9365 | 0.079 | 0.8818 | 3.499745601 |
| 32 | 10 | 20 | 20000 | 200 | 2600 | 7.6923 | 0.077 | 0.8496 | 3.589370652 |
| 33 | 10 | 20 | 20000 | 200 | 2680 | 7.4627 | 0.075 | 0.8196 | 3.679393908 |
| 34 | 10 | 20 | 20000 | 200 | 2760 | 7.2464 | 0.072 | 0.7918 | 3.769782902 |
| 35 | 10 | 20 | 20000 | 200 | 2840 | 7.0423 | 0.07 | 0.7658 | 3.860507506 |
| 36 | 10 | 20 | 20000 | 200 | 2920 | 6.8493 | 0.068 | 0.7415 | 3.951539876 |
| 37 | 10 | 20 | 20000 | 200 | 3000 | 6.6667 | 0.067 | 0.7187 | 4.042854362 |
| 38 | 10 | 20 | 20000 | 200 | 3080 | 6.4935 | 0.065 | 0.6973 | 4.134427401 |
| 39 | 10 | 20 | 20000 | 200 | 3160 | 6.3291 | 0.063 | 0.6772 | 4.2262374 |
| 40 | 10 | 20 | 20000 | 200 | 3240 | 6.1728 | 0.062 | 0.6582 | 4.318264606 |
(5) be variable with the described annular cellular number of plies, as abscissa, with the corresponding conduction resistance value of the annular cellular number of plies be ordinate, draw as shown in Figure 7 the annular cellular number of plies and the graph of relation between device conduction resistance value.This curve is different for the withstand voltage device of difference with the different machining parameters ability.
By above-mentioned curve chart and integrated circuit performance requirement and actual machined parameters ability to power device, determine machinable device power unit 6[in parallel and see Fig. 5 (a)] reasonable size (being the annular cellular number of plies) and shape, because this annular cellular is corresponding to the original cellular of described annularization processing other than ring type before, therefore, this power unit 6 in parallel is also just directly corresponding to the power associative cell of the VDMOS device of the original cellular of other than ring typeization.
At last, described power unit 6 in parallel is carried out parallel connection and repetition according to the parallel way of described device, obtain the domain structure layout of described power device, see Fig. 5 (b).
The inventive method optimal control device conduction resistance and saving area are obvious.For example, according to foregoing data, promptly establish epitaxial loayer (active layer) resistance per unit length value Ra=20000 Ω, buried regions resistance per unit length value Rb=200 Ω, the described original cellular that obtains when cellular is carried out withstand voltage design is of a size of 10 μ m, cellular spacing 10 μ m, active bed thickness 10 μ m, find out that by Fig. 7 curve when the cellular number of plies was 10, the conduction resistance value of device was 2～3M Ω cm
2, and the cellular number of plies is at 100 o'clock, the conduction resistance value of device reaches 10M Ω cm
2, in other words, area utilization differs 5 times under two kinds of situations.Therefore, when designing this power device, just do not design the described cellular number of plies too much, should choose the rational cellular number of plies according to circuit requirement and actual machined parameters ability and make described power unit in parallel, connection and repetition by these power unit in parallel, reach the requirement of the little conduction resistance value of described power device, keep less device area simultaneously.From top description as can be known, increase the number of plies of described cellular, can reduce resistance between the device source leakage, but area utilization reduces, if the control cellular number of plies just can obtain the optimization result of resistance under actual working ability between the device source leakage in certain limit, thereby form actual machinable power unit in parallel, based on this unit in parallel, carry out parallel connection and repeat to improve the device current negotiability, keep the small conduction resistance of device.Because the annular processing of described cellular is directly corresponding and the original cellular layout of the other than ring type determined when being equivalent to original withstand voltage design, therefore, the device that the result of its optimization determines in the time of can directly being used for described withstand voltage design accordingly.For example, we get the annular cellular number of plies 30 of phase commute processing, obtain the about 3M Ω of device conduction resistance value cm by Fig. 7
2, the device of ifs circuit designing requirement 12M Ω, the device area that then needs are 3M Ω cm
2/ 12M Ω=0.25cm
2, if wiring area in parallel is 10%, then the final area of required device is 0.25cm
2* (1+0.1)=0.275cm
2If press the original cellular design of other than ring typeization, do not carry out unit optimization design in parallel, promptly the cellular number of plies is 100, then the conduction resistance value of device is about 10M Ω cm
2, to the designs of the 12M Ω of identical requirement, then needing device area is 10M Ω cm
2/ 12M Ω=0.833cm
2, the ratio of the device area that two kinds of methods for designing obtain is 0.833cm
2/ 0.275cm
2≈ 3 (doubly), the device area utilance has improved about 3 times.This shows that the inventive method is better, more economical than the design performance of the existing method for designing of similar device.
Method for designing for BJT (bipolar) power unit structure is identical with above-mentioned VDMOS device, the source drain-gate is become emitter, base stage, collector electrode get final product, and resistance became emitter inter-collector resistance between leaked in the source.Identical as for other structure Design methods of super-current power unit of the present invention and existing method, be well-known to those skilled in the art, and be not theme of the present invention, so do not repeat.
Claims (5)
1, a kind of method for designing of integration super-current power unit structure of small conduction resistance, current processing cellular to described device carries out withstand voltage design, determine cellular size, cellular spacing and the terminal structure of original cellular, it is characterized in that: this method for designing also comprises step:
(1) described original cellular is carried out the annular processing, be converted to corresponding annular cellular;
(2) determine the buried regions resistance per unit length value and active layer (epitaxial loayer) the resistance per unit length value of described device;
(3) carry out the circuit equivalent of described device architecture according to described annular cellular current path, draw the equivalent circuit diagram of described device;
(4) draw the annular cellular number of plies of described device and the relation curve between the conduction resistance value corresponding with it;
(5) determine machinable power cell size (the annular cellular number of plies) in parallel, shape according to the circuit performance requirement and the machined parameters ability of described device;
(6) described power unit in parallel is connected by its parallel way and repeat, determine the domain structure layout of described device.
2, the method for designing of the integration super-current power unit structure of small conduction resistance according to claim 1 is characterized in that: described original cellular annularization processing method comprises:
(1) determines its axial symmetry and center symmetric points according to described device plane figure with respect to original cellular current path;
(2) under the constant situation of the cellular size, the cellular spacing that guarantee described original cellular, be the center, described original cellular be converted to the described annular cellular that is concentric ring with described symmetric points.
3, the method for designing of the integration super-current power unit structure of small conduction resistance according to claim 1 is characterized in that: draw the annular cellular number of plies of described device and the method for the conduction resistance value relation curve corresponding with it and comprise:
(1) calculates the girth of determining described every layer of annular cellular;
(2) calculate active layer resistance value and the buried regions resistance value of determining corresponding to described every layer of annular cellular;
(3) equivalent circuit diagram according to described device calculates resistance value between definite described device electrode;
(4) calculate the device conduction resistance value of determining corresponding to the described annular cellular number of plies;
(5) being variable with the described annular cellular number of plies, as abscissa, is ordinate with the conduction resistance value corresponding to the annular cellular number of plies, draws out the graph of relation between the described annular cellular number of plies and the device conduction resistance value corresponding with it;
4, according to the method for designing of the integration super-current power unit structure of claim 1,2 or 3 described small conduction resistances, it is characterized in that: determine by the merchant of the girth of described active layer resistance per unit length value and buried regions resistance per unit length value and corresponding described annular cellular respectively corresponding to the active layer resistance value of described every layer of annular cellular and buried regions resistance value.
5, according to the method for designing of the integration super-current power unit structure of claim 1,2 or 3 described small conduction resistances, it is characterized in that: described device conduction resistance value by and the corresponding device electrode that forms by described active layer and buried regions of the described annular cellular number of plies between resistance value and determine with the long-pending of the corresponding device area of the described annular cellular number of plies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101042987A CN100339946C (en) | 2004-12-22 | 2004-12-22 | Design method for integration super-current power unit structure of small conduction resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004101042987A CN100339946C (en) | 2004-12-22 | 2004-12-22 | Design method for integration super-current power unit structure of small conduction resistance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1722360A true CN1722360A (en) | 2006-01-18 |
| CN100339946C CN100339946C (en) | 2007-09-26 |
Family
ID=35912537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004101042987A Expired - Fee Related CN100339946C (en) | 2004-12-22 | 2004-12-22 | Design method for integration super-current power unit structure of small conduction resistance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100339946C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112417806A (en) * | 2020-11-11 | 2021-02-26 | 无锡优波生命科技有限公司 | Design method of TCM component planar circuit diagram |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1228900B (en) * | 1989-02-27 | 1991-07-09 | Sgs Thomson Microelectronics | INTEGRATED MONOLITHIC STRUCTURE FOR TWO-STAGE PILOTING SYSTEM WITH CIRCUIT COMPONENT LEVEL TRANSLATOR OF THE PILOT SIGNAL FOR POWER TRANSISTORS. |
| FR2649828B1 (en) * | 1989-07-17 | 1991-10-31 | Sgs Thomson Microelectronics | VDMOS / LOGIC INTEGRATED CIRCUIT COMPRISING A DEPLETED VERTICAL TRANSISTOR AND A ZENER DIODE |
| IT1241050B (en) * | 1990-04-20 | 1993-12-29 | Cons Ric Microelettronica | FORMATION PROCESS OF A BURIED REGION OF DRAIN OR COLLECTOR IN MONOLITHIC SEMICONDUCTOR DEVICES. |
| JPH11102916A (en) * | 1997-09-29 | 1999-04-13 | Nec Corp | Semiconductor integrated circuit device and design method thereof |
| CN2398728Y (en) * | 1999-09-30 | 2000-09-27 | 王晓昀 | Transistor for communication apparatus overvoltage current foldback |
-
2004
- 2004-12-22 CN CNB2004101042987A patent/CN100339946C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112417806A (en) * | 2020-11-11 | 2021-02-26 | 无锡优波生命科技有限公司 | Design method of TCM component planar circuit diagram |
| CN112417806B (en) * | 2020-11-11 | 2023-12-19 | 无锡优波生命科技有限公司 | TCM element plane circuit diagram design method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100339946C (en) | 2007-09-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1040814C (en) | Surface withstand voltage zone for semiconductor device | |
| CN1314091C (en) | Trench DMOS transistor with embedded trench schottky rectifier | |
| CN104576720A (en) | Power device and a reverse conducting power IGBT | |
| CN1531756A (en) | Field effect semiconductor diode with vertical junction | |
| CN101707208A (en) | Multi-field plate LDMOS device and processing method thereof | |
| CN103579353A (en) | Semi-super-junction VDMOS (vertical double-diffused metal oxide semiconductor) provided with P type auxiliary buried layer | |
| CN100339946C (en) | Design method for integration super-current power unit structure of small conduction resistance | |
| CN114512535A (en) | Manufacturing method of double-channel SiC transverse LDMOS power device | |
| CN201540894U (en) | LDMOS device of multiple field plates | |
| CN1524296A (en) | Rf power LDMOS transistor | |
| CN112820775A (en) | SOI-LDMOS device with electron accumulation effect | |
| CN115295627B (en) | High-voltage power semiconductor device and method for manufacturing the same | |
| CN103633149B (en) | Current regulator diode and manufacture method thereof | |
| CN203631565U (en) | Current regulative diode | |
| CN113097310B (en) | Fin-type EAFin-LDMOS device with electron accumulation effect | |
| CN117317024B (en) | High-switching-characteristic semiconductor device, process, chip and electronic equipment | |
| US7253498B2 (en) | Bipolar transistor with geometry optimized for device performance, and method of making same | |
| CN218769540U (en) | Silicon carbide MOSFET with voltage-resistant structure | |
| CN116454116B (en) | Trench MOSFET device and manufacturing method thereof | |
| CN114883380B (en) | Insulated gate semiconductor device and preparation method thereof | |
| CN114883385A (en) | Three-dimensional square cellular structure, preparation method and device thereof | |
| CN107425061B (en) | Variable doped anode IGBT structure and manufacturing method thereof | |
| CN1630100A (en) | Semiconductor device | |
| CN115083919A (en) | Manufacturing method of silicon carbide MOSFET (Metal-oxide-semiconductor field Effect transistor) with increased voltage endurance capability | |
| CN113823678A (en) | High-voltage NPN device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |