CN1720493A - Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type - Google Patents
Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type Download PDFInfo
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Abstract
The present invention provides a frequency modulator apparatus of phase selection type that relaxes the restrictions as to the phase range of modulation clock signals. This frequency modulator apparatus of phase selection type comprises a poliphase clock signal generator circuit (101) for generating N-phase clock signals; a control circuit (104) for sequentially activating first clock selection signals that instruct which ones of the N-phase clock signals should be selected; an edge appearance time adjusting circuit (103) for adjusting the rising edge and/or falling edge appearance times of the first clock selection signals outputted from the control circuit (104) to output second clock selection signals; and a modulation clock signal generator circuit (102) for selecting, in accordance with the activation state of the second clock selection signals outputted from the edge appearance time adjusting circuit (103), one of the N-phase clock signals to output a modulation clock signal (MCK).
Description
Technical field
The present invention relates to reduce the phase place selection type frequency modulator and the phase place selection type frequency synthesizer of the electromagnetic interference (EMI) (being called " EMI " hereinafter) in the electronic equipment of transmitted image data etc.
Background technology
Because the fast turn-around of electronic equipment, the EMI in the electronic equipment becomes a problem, and needs to reduce EMI.As a kind of technology that is used for reducing the EMI of electronic equipment, people have proposed a kind of method that adopts spread spectrum clock.More particularly, produce shake wittingly so that can not produce the peak value of frequency spectrum on specific frequency, perhaps frequency is along with the cycle gradually changes, and this running to circuit can not exert an influence, for example, one at several kilo hertzs of periods of change in the hundreds of kilohertz range.
Figure 17 is the functional-block diagram that is illustrated in the structure of disclosed clock-signal generator among the Japanese Patent Application Publication JP-A-2001-148690.As shown in figure 17, above-mentioned clock-signal generator has clock generation unit 2001, is used to produce the phase place m phase clock signal S1m of desired frequency, and wherein the phase place of this signal is according to the constant interval transition between adjacent two clock signals; Selected cell 2003 is used to select a m phase clock signal S1m; And shake control module 2002, be used for determining selection at selected cell 2003.The m phase clock signal S1m that will produce in clock generation unit 2001 offers selected cell 2003, and is taken out by outlet terminal 2005.From shake control module 2002 control signal SEL is offered selected cell 2003.Selected cell 2003 is sequentially selected a m phase clock signal S1m according to control signal SEL, thereby and from taking out the clock signal S2 that is obtained the outlet terminal 2004.The frequency spectrum of the clock signal S2 that obtains at outlet terminal 2004 places is used to control the shake control module 2002 generation selection signal SEL of selected cell 2003, so that can be expanded as far as possible widely.
Figure 18 is the circuit block diagram that the concrete structure example of shake control module 2002 is shown.As shown in figure 18, shake control module 2002 comprises eight the D-D-flip flops 2031 to 2038 that constitute the chain of rings, and three OR circuit 2041 to 2043.When the signal of output signal S0 to S4 is in high level, just make other four signals be in low level, and this high level move in each cycle of clock signal C K between these signals.
Figure 19 is the block scheme that the concrete structure example of selected cell 2003 is shown.This selected cell 2003 comprises 2051 to 2055 and buffer circuits 2056 of five on-off circuits.Above-mentioned output signal S0 to S4 synchronously in, from five Δ T phase clock signal DC0 to DC4 at interval, select one, and produce and export modulated clock signal by buffer circuit 2056.
Figure 20 shows the operation waveform example of above-mentioned clock-signal generator.As shown in figure 20, in a time cycle A, press the select progressively clock signal of DC0, DC1, DC2, SC3, DC4, and the cycle of modulated clock signal S2 becomes T+ Δ T.On the other hand, in a time cycle B, press the select progressively clock signal of DC4, DC3, DC2, SC1, DC0, and the cycle of modulated clock signal S2 becomes T-Δ T.Here, " T " is defined as the frequency f of clock signal of system
CKInverse, and hereinafter, " T " is used for identical meaning.Because the operation in time cycle A and B is repetition, thus cancellation+Δ T and-Δ T so as modulation period T
Mod(not shown) becomes T
Mod=8 * T.According to above-mentioned clock-signal generator, can clock signal, the peak value of expansion on this frequency spectrum in this clock signal, and can adopt the electrical equipment of this clock signal reduce EMI by operation.
Yet, when stating clock-signal generator in the use, have problem as described below.To explain this problem with reference to Figure 21.Figure 21 shows in above-mentioned clock-signal generator problems in running.As shown in figure 21, when the edge of the edge of m phase clock signal S1m (rising edge 2101 shown in Figure 21 and negative edge 2103) and selection signal SEL overlaps each other, as shown in figure 19, the operation that is provided in the on-off circuit 2051 to 2055 (switch between " 0 " and " 1 ") in the selected cell 2003 is broken down, and the deterioration that becomes of the waveform of the clock signal of modulating.That is to say, as shown in figure 21 corresponding to 360 degree clock phases of the one-period of clock signal of system among (with the scope shown in the arrow), in the scope that the scope of the clock phase of clock signal of system is limited in obtaining by the scope that deducts the consideration predetermined space from 180 degree, that is exactly that wherein clock signal of system is actually and can changes less than 180 degree.
Here, with reference to figure 22A to 22C, with the relation of explanation between the spectrum intensity of modulation period and clock signal.Figure 22 A shows relation between spectrum intensity and frequency when this clock signal is not modulated.Figure 22 B shows when modulation period very short, when just 1/Tmod is very big, and the relation between spectrum intensity and frequency.Figure 22 C shows when modulation period very long, when just 1/Tmod is very little, and the relation between spectrum intensity and frequency.Here, " Tmod " expression modulation period and " T " are the frequency f of clock signal of system
CKInverse.
Shown in Figure 22 A, when this clock signal is not modulated, on the position of f=1/T, observe spectrum peak 2201.Shown in Figure 22 A, in such a case, promptly modulation clock signal is so that modulated clock frequency can become T-Δ T and T+ Δ T for spread spectrum, and the expectation peak value appears at frequency f=1/ (T+ Δ T) and f=1/ (T-Δ T) locates.Yet, very short when modulation period shown in Figure 22 B, i.e. 1/Tmod＞Δ f, nearly all spectrum component that (T+ Δ T) and f=1/ (T-Δ T) locate in frequency f=1/ all concentrates on the peak value 2201 of frequency f=1/T, and power never takes place disperses.Because,, peak value occurs with the frequency interval of 1/Tmod about the wave form varies in 1/Tmod cycle according to the characteristic of Fourier transform.On the other hand, very long when modulation period shown in Figure 22 C, promptly during 1/Tmod＜Δ f, the spectrum component of frequency f=1/ (T+ Δ T) and f=1/ (T-Δ T) shows as peak value.That is to say that except that the peak value 2201 of frequency f=1/T, peak value 2217 and peak value 2215 appear between frequency f=1/ (T+ Δ T) and the f=1/ (T-Δ T) with the frequency interval of 1/Tmod.Shown in Figure 22 A and 22B, because power disperses, the earthquake intensity of the peak value of frequency f=1/T is compared with the earthquake intensity of peak value 2201 and is become lower, and the generation of power dispersion as can be seen.
Consider to see the condition of modulation effect, be necessary to allow the frequency interval at peak value place seem shorter than the frequency interval between the 1/T and 1/ (T/ Δ T).That is to say, require to keep following formula (1).
1/Tmod＜ABS(1/T-1/(T±ΔT))≈ΔT/T
2 ...(1)
Wherein ABS (X) represents the absolute value of X.
Here, the number of phases of given multi-phase clock signal is N, by following formula (2) expression Tmod modulation period.
Tmod＝2N×T...(2)
Owing to expression formula (1) and (2) are arranged, can introduce following expression formula (3).
T/2＜N×ΔT...(3)
Here, shown in Figure 17-19, as mentioned above need be corresponding to the N in the valuable scope of phase place * Δ T in this circuit, but and the phase place ranges of value that are at least 180 degree.
Summary of the invention
Therefore, in view of above-mentioned argument, the purpose of this invention is to provide a kind of phase place selection type frequency modulator and a kind of phase place selection type frequency synthesizer that can loosen to the restriction of the phase range of modulated clock signal.
In order to address the above problem, phase place selection type frequency modulator according to an aspect of the present invention comprises: the multi-phase clock signal generation device is used for producing the N phase clock signal with phase differential mutually from each signal; Control device, be used for sequentially activating of first group of clock selection signal, wherein this clock selection signal is indicated the clock signal that chooses from the N phase clock signal of multi-phase clock signal generation device output, and first group of clock selection signal is corresponding to the N phase clock signal; Edge time of occurrence adjusting gear, be used to adjust rising edge time of occurrence and/or negative edge time of occurrence from first group of clock selection signal of control device output, with corresponding to N phase clock signal, export second group of clock selection signal from the output of multi-phase clock signal generation device; And modulated clock signal generating apparatus, be used for state of activation according to second group of clock selection signal exporting from edge time of occurrence adjusting gear, from the N phase clock signal, select a clock signal, select clock signal as modulated clock signal with output.
Further, phase place selection type frequency synthesizer according to an aspect of the present invention comprises: control device, be used for sequentially activating of first group of clock selection signal, wherein this clock selection signal is indicated and will be had the clock signal that chooses the N phase clock signal of phase differential from the multi-phase clock signal generation device, and first group of clock selection signal is corresponding to the N phase clock signal; Edge time of occurrence adjusting gear, be used to adjust rising edge time of occurrence and/or negative edge time of occurrence from first group of clock selection signal of control device output, with corresponding to N phase clock signal, export second group of clock selection signal from the output of multi-phase clock signal generation device; And modulated clock signal generating apparatus, be used for state of activation according to second group of clock selection signal exporting from edge time of occurrence adjusting gear, from the N phase clock signal, select a clock signal, select clock signal as modulated clock signal with output; Phase comparison device, the phase place that is used for the clock signal selected with the phase place of reference clock signal with by the modulated clock signal generating apparatus compares; And the multi-phase clock signal generation device, be used for producing the N phase clock signal, and export a N phase clock signal as modulated clock signal based on the comparative result of phase comparison device.
According to the present invention, because can loosen restriction, so EMI can reduce further to the phase range of modulated clock signal.
Description of drawings
By considering following detailed explanation and relevant drawings, it is clear and definite that advantages and features of the invention will become.In these figure, identical Reference numeral is indicated identical ingredient.
Fig. 1 is the block scheme that illustrates according to a kind of structure of the phase place selection type frequency modulator of the first embodiment of the present invention;
Fig. 2 is the block scheme that illustrates according to a kind of structure of the phase place selection type frequency synthesizer of the first embodiment of the present invention;
Fig. 3 is the block scheme that a kind of structure example of multi-phase clock signal generation circuit as shown in Figure 1 is shown;
Fig. 4 is the block scheme that the structure example of heterogeneous VCO as shown in Figure 2 is shown;
Fig. 5 shows a kind of structure example that the modulated clock signal generating circuit that comprises as shown in Figure 1 and edge time of occurrence are adjusted circuit;
Fig. 6 shows the clock signal generating circuit of the ten two phases modulation that comprises as shown in Figure 2 and a kind of structure example that the edge time of occurrence is adjusted circuit;
Fig. 7 A and 7B show the structure example of the on-off circuit in Fig. 5;
Fig. 8 shows the distortion example that modulated clock signal generating circuit shown in Fig. 5 or 6 and edge time of occurrence are adjusted circuit;
Fig. 9 is used to explain that the process flow diagram that the operation of circuit is adjusted in realization appears in modulated clock signal generating circuit and edge;
Figure 10 is used to explain that the process flow diagram that the operation of circuit is adjusted in realization appears in modulated clock signal generating circuit and edge;
Figure 11 is a kind of structure example that the control circuit shown in Fig. 1 or 2 is shown;
Figure 12 show as shown in figure 11 on/following ring register;
Figure 13 is the block scheme that another structure example of the control circuit shown in Fig. 1 or 2 is shown;
Figure 14 is the timetable that the operation of control circuit as shown in figure 13 is shown;
Figure 15 is a kind of block scheme of structure that the Δ X modulator of three values as shown in figure 11 is shown;
Figure 16 is the block scheme that a kind of structure of phase place selection type frequency modulator according to a second embodiment of the present invention is shown;
Figure 17 is the block scheme that a kind of structure of traditional clock-signal generator is shown;
Figure 18 is the block scheme that a structure example of the shake control module among Figure 17 is shown;
Figure 19 is the block scheme that a kind of structure of the selected cell among Figure 17 is shown;
Figure 20 is the operation oscillogram of the clock-signal generator among Figure 17;
Figure 21 is used for explaining by the operation waveform it seems the chart of problem of clock-signal generator of Figure 17; And
Figure 22 is used for explaining by spread spectrum it seems the chart of problem of clock-signal generator of Figure 17.
Preferred forms of the present invention
In phase place selection type frequency modulator according to the present invention and phase place selection type frequency synthesizer, in order to produce modulated clock signal, but in this clock signal, loosen the restriction of phase place range of value to reduce EMI, constitute a kind of circuit so that a rising edge of clock signal time of occurrence and/or a negative edge time of occurrence choosing and being used to selected the rising edge time of occurrence of clock selection signal of this clock signal and/or negative edge time of occurrence may have time lag and can not be overlapped each other from the N phase clock signal.
Here, be to be equal to, or greater than in the situation of four integer in the number of phases " N " of N phase clock signal, will tell on according to phase place selection type frequency modulator of the present invention and phase place selection type frequency synthesizer.
More particularly, when producing modulated clock signal by a clock signal of selection (being called " first clock signal ") from the N phase clock signal, and with this clock signal when being used to select the clock selection signal of first clock signal, wherein the N phase clock signal has different phase places from 1 to N, will produce second clock and select signal, this signal has the edge time of occurrence of adjusting based on another clock signal (being called " second clock signal edge "), another clock signal wherein have with the N phase clock signal in the different phase place of first clock signal, and indicate by first clock signal it chosen.According to the state of activation (for example, high level or low level) of second clock selection signal, select one of N phase clock signal CK1 to CKN, and the clock signal of selecting is exported as modulated clock signal.
Whereby, the first rising edge clock signal time of occurrence and/or negative edge time of occurrence and being used to selected the rising edge time of occurrence and/or the conversion at random of negative edge time of occurrence of second group of clock selection signal of first clock signal.
Based on above-mentioned consideration, will be with reference to phase place selection type frequency modulator according to an embodiment of the invention is described with figure below.
Fig. 1 is the block scheme that illustrates according to the structure of the phase place selection type frequency modulator of the first embodiment of the present invention.As shown in Figure 1, phase place selection type frequency modulator 100 according to first embodiment of the invention comprises that multi-phase clock signal produces circuit 101, be used to produce multi-phase clock signal, modulated clock signal generating circuit 102, be used for by selecting a clock signal to carry out modulation operations from multi-phase clock signal, the edge time of occurrence is adjusted circuit 103, and has the control circuit 104 that clock selection signal produces circuit 105 and the control logic circuit 106 that is used to control.The number of phases of multi-phase clock signal " N " is, for example, 6,12 or the like.The clock signal SELCLK that 102 outputs of modulated clock signal generating circuit are selected is as modulated clock signal MCK.
Fig. 2 shows a kind of structure of the phase place selection type frequency synthesizer that adopts the phase place selection type frequency modulator among Fig. 1.Phase place selection type frequency synthesizer 110 is modulated the reference clock signal (REFCLX) 111 of input, and it is exported as modulated clock signal 120.Phase place selection type frequency synthesizer comprises have phase detector (PD) 112, charge pump 113, and such as the phase-comparison circuit 115 of the loop filter 114 of low-pass filter (LPF), and heterogeneous (N phase place) voltage controlled oscillator (VCO) 116.In addition, be similar to shown in Figure 1, phase place selection type frequency synthesizer comprises modulated clock signal generating circuit 102, edge time of occurrence adjustment circuit 103, and has the control circuit 104 that clock selection signal produces circuit 105 and control logic circuit 106.By the output of phase-comparison circuit 115 control modulated clock signal generating circuits 102, wherein phase-comparison circuit 115 will be to being compared by the phase place of the clock signal of frequency divider 117 feedbacks and the phase place of reference clock signal (REFCLK) 111.Clock signal C K1 is cut apart by frequency divider 118 as the output of heterogeneous VCO116, and with 120 outputs of modulated clock signal, and this modulated clock signal 120 becomes expectation value with frequency modulation (PFM).
Modulated clock signal generating circuit 102 is selected one from the N phase clock signal of heterogeneous VCO116 output, and with the clock signal SELCLK of its output as selection.In phase-comparison circuit 115, compare and control the output of modulated clock signal generating circuit 102 by phase place to feedback signal and reference clock signal (REFCLK) 111, based on clock signal C K1 as the output of heterogeneous VCO 116, produce modulated clock signal 120, this signal is an expectation value with frequency modulation (PFM).
In said structure, when the selection of carrying out is constant, represent the frequency of this modulated clock signal by following formula in the selector switch of modulated clock signal generating circuit 102.
f0＝f
REFCLK·M/N
When the selection in selector switch changes, for example, once fall back one, the frequency of modulated clock signal is controlled as fmax=f013/12.When the selection in selector switch changes forward, for example, once advance one, the frequency of modulated clock signal is controlled as fmin=f011/12.The mode of the selection conversion by will be in selector switch is mixed, and the frequency of modulated clock signal can be controlled as an arbitrary value between fmax and the fmin.
By use the modulation of increment summation according to frequency, be controlled at the mode of the selection conversion in the selector switch, just may cause the value of frequency for being provided with of modulated clock signal by frequency data.The order of increment summation modulation can be first, second or more high-order.Yet, second than primary accuracy height, and same situation appear at the 3rd or more high-order in, though effect is not different with deputy situation so, circuit scales up.Therefore, it is desirable approximately being positioned at second.
Fig. 3 shows the structure example of multi-phase clock signal generation circuit 101 as shown in Figure 1.Multi-phase clock signal as shown in Figure 3 produces circuit 101 and has 201 to 203 and six comparers 211 to 216 of three differential amplifiers.Three differential amplifier 201 to 203 looping oscillators.Six comparers 211 to 216 compare the noninverting output and the anti-phase output of differential amplifier 201 to 203, and wherein noninverting output and anti-phase output have delay, convert them to the clock signal C K1 to CK6 of six phases in comparer 211 to 216.Be set to equate that six phase clock signal CK1 to CK6 can become etc. separately the whole time delays by differential amplifier 201 to 203.
Fig. 4 shows the structure example of heterogeneous VCO as shown in Figure 2.Heterogeneous VCO 116 as shown in Figure 4 has the ring oscillator that is made of 221 to 226 and 12 comparers 231 to 242 of six differential amplifiers.Control voltage by differential amplifier 221 to 226 can change the time delay on each differential amplifier, and can control this frequency.Further,, in the output of each differential amplifier, carry out level conversion, can produce ten two phase clock signal clks 1 to CLK12 by relying on two comparers that are used for normal and inverse case.
Fig. 5 shows the structure example that the modulated clock signal generating circuit 102 that comprises as shown in Figure 1 and edge time of occurrence are adjusted circuit 103.As shown in Figure 5, the edge time of occurrence is adjusted circuit 103 and is comprised trigger circuit 801 to 806, and modulated clock signal generating circuit 102 comprises corresponding to the on-off circuit 811 to 816 of trigger circuit 801 to 806 and is generally its output and the buffer circuit 821 established.
Each entry terminal for trigger circuit 801 to 806, import corresponding first group of clock selection signal SEL1 to SEL6, and, for its clock signal terminal, each clock signal C K1 to CK6 that has input has the phase differential in the preset range between these clock signals and the clock signal according to first group of clock selection signal SEL1 to SEL6 selection.For example, clock selection signal SEL1 is input to the entry terminal of trigger circuit 801, and clock signal C K5 is input to its clock signal terminal.Similarly, clock selection signal SEL2 is input to the entry terminal of trigger circuit 802, and clock signal C K6 is input to its clock signal terminal.
Whereby, the first group of clock selection signal SEL1 to SEL6 that is input to trigger circuit 801 to 806 latched, this latchs with the clock signal than the leading T/3 of each phase place (120 degree) of the clock signal C K1 to CK6 that is selected by first group of clock selection signal SEL1 to SEL6 respectively is synchronous respectively, and, in order to control the ON/OFF of corresponding first to the 6th on-off circuit 811 to 816, latched signal is exported as second group of clock selection signal (switch controlling signal) SSEL1 to SSEL6.
In order to prevent at second group of clock selection signal SSEL1 to SSEL6 and to occur overlapping between the edge time of occurrence of each clock signal of selecting whereby, obtain allowance in such a case, promptly in the clock signal of selecting and the phase differential that is used for first group of clock selection signal is latched between the clock signal of trigger circuit be set to about 90 degree.Fig. 5 for example shows, and phase differential is the situation of 120 degree.
For the input end of on-off circuit 811 to 816, input corresponding clock signals CK1 to CK6 carry out ON/OFF control according to second group of clock selection signal SSEL1 to SSEL6, and a clock signal will selecting is transferred to output terminal.The output terminal of on-off circuit 811 to 816 normally links, and by buffer circuit 821 clock signal of selecting is exported as the clock signal SELCLK that selects.
Fig. 6 shows a kind of structure example that the clock signal generating circuit 102 that comprises ten two phases modulation and edge time of occurrence are adjusted circuit 103.Because the edge time of occurrence is adjusted the activationary time that circuit 103 is adjusted second group of clock selection signal SSEL1 to SSEL12, between each clock signal of second group of clock selection signal and selection, the edge time of occurrence is fixed interval all the time, and both edges are never overlapping.
Adjust in the circuit 103 at the edge time of occurrence, first group of clock selection signal SEL1 to SEL12 is latched, make itself and each and corresponding clock signals CK1 to CK12 between to have the clock signal of predetermined phase difference synchronous, and with its output as the controlled second group of clock selection signal SSEL1 to SSEL12 in edge.Modulated clock signal generating circuit 102 is selected among the clock signal C K1 to CK12 one according to second group of clock selection signal SSEL1 to SSEL12, and with it as clock signal SELCLK output of selecting.
Fig. 7 A and 7B show the structure example of the on-off circuit 811 among the modulated clock signal generating circuit 102 in Fig. 5.On-off circuit shown in Fig. 7 A is a kind of analog switch of cmos circuit, and has N-channel MOS transistor 903, P channel MOS transistor 902 and phase inverter 901.For the control terminal (gate terminal) of N-channel MOS transistor 903, the clock selection signal (switch controlling signal) in importing second group, for example, clock selection signal SSEL1 shown in Figure 5.For the gate terminal of P channel MOS transistor 902, input is by the clock selection signal SSEL1 of phase inverter 901 counter-rotatings.When clock selection signal SSEL1 is set to high level, the analog switch conduction that become, and the clock signal C K1 that will be input to analog switch is transferred to the outlet terminal OUT of analog switch.
On-off circuit shown in Fig. 7 B adopts N-channel MOS transistor 904, and clock selection signal SSEL1 is input to the transistorized gate terminal of N-channel MOS.When second clock selects signal SSEL1 to be in high level, the clock signal C K1 that is input to on-off circuit is transferred to the outlet terminal OUT of on-off circuit.
By the way, can constitute on-off circuit among on-off circuit 812 to 816 and Fig. 6 with the same mode shown in Fig. 7 A or the 7B.
Fig. 8 shows the distortion example that modulated clock signal generating circuit shown in Fig. 5 or 6 and edge time of occurrence are adjusted circuit.Structure shown in Figure 8 and Fig. 5 or 6 difference are, clock signal entry terminal corresponding to the trigger circuit of this on-off circuit 1011, import the clock signal C K1 the same with the clock signal that is input to this respective switch circuit 1011, and difference is, is provided for postponing the delay circuit 1002 of this clock signal C K1 that is input to on-off circuit 1011 here.In fact, provide aforesaid N circuit.
Under the situation that adopts structure as shown in Figure 8, the clock signal of similarly will be with respect to clock signal C K1 and being postponed by delay circuit 1002 is input to on-off circuit 1011, therefore, clock signal can be imported in this on-off circuit 1011, and clock signal wherein is different with the clock signal C K1 that is input to trigger circuit 1001 aspect the edge time of occurrence.
With reference to figure 9 and 10, the operation of above-mentioned modulated clock signal generating circuit and edge time of occurrence adjustment circuit will be described in Fig. 9 and 10.In Fig. 9 and 10, show as a conduct among the clock signal C K1 to CK6 that is used for selecting Fig. 5 and select first group of clock selection signal SEL1 to SEL6 of signal, the waveform of second group of clock selection signal SSEL1 to SSEL6 really, for example, the clock signal SELCLK of clock signal C K1 to CK6 and selection.
In Fig. 9, transition clock signal C K1 to CK6 on the phase lag direction.According to second group of clock selection signal SSEL1 to SSEL6, sequentially select among the clock signal C K1 to CK6.Thereby the cycle of the clock signal SELCLK of the selection that produces becomes T+ Δ T.
First group of clock selection signal SEL1 to SEL6 is and the synchronous signal of selecting of clock signal SELCLK.Therefore, by first group of clock selection signal SEL1 to SEL6 latched with other predetermined clock signal Synchronization respectively, thereby produce second group of clock selection signal SSEL1 to SSEL6.In example as shown in Figure 9, about clock signal C K1, latch synchronously, thereby select signal SSEL1 to change into low level or high level second clock by rising edge with the first clock selection signal SEL1 and clock signal C K5.Further, about clock signal C K2, latch synchronously by rising edge, thereby select signal SSEL2 to change into low level or high level second clock the first selection signal SEL2 and clock signal C K6.Similarly, can produce other signal of second group of clock selection signal SSEL3 to SSEL6.
Here, as being clear that among Fig. 9, the edge of clock signal position CK1 occurs and selects signal SSEL1 to be in fixed intervals all the time with the second clock that clock signal C K5 produces synchronously, and the edge time of occurrence is never overlapping, wherein clock signal C K5 has the phase place different with clock signal C K1 (the leading T/3 of phase place, that is 120 degree).Therefore, clock signal SELCLK for the selection that produces by clock signal C K1 to CK6 order, the waveform of the clock signal of this selection never worsens, even because period T+the very long time of Δ T continuity, the edge time of occurrence of second group of clock selection signal SSEL1 to SSEL6 and the edge time of occurrence of the clock signal C K1 to CK6 of selection is also never overlapping respectively.Thereby, there is a kind of like this advantage, promptly can produce clock signal continuously corresponding to the selection of CK1 → C2 → CK3 → CK4 → CK5 → CK6 → CK1....In Fig. 9, such one-period is arranged, all second group of clock selection signal SSEL1 to SSEL6 are in low level in this cycle, however in this cycle, by the stray capacitance of element and electric wire, the output of on-off circuit is kept.
In Figure 10, and in Fig. 9, sequentially from clock signal C K1 to CK6, choose a clock signal.Yet problem is that the cycle of the clock signal SELCLK of the selection that where produces is that T-Δ T aspect is different.That is to say transition clock signal C K1 to CK6 on the leading direction of phase place.For example, as being clear that among Figure 10, the edge time of occurrence of clock signal C K1 and the clock selection signal SSEL1 that produces based on clock signal C K5 be fixed interval all the time, and the edge time of occurrence is never overlapping, wherein clock signal C K5 has the phase place different with clock signal C K1 (the leading T/3 of phase place, i.e. 120 degree).
Therefore, about the clock signal SELCLK of the selection that produces based on clock signal C K1 to CK6 order, although period T-Δ T continuity does not have problem yet and produces.Thereby, a kind of like this advantage is arranged, promptly can produce respectively clock signal SELCLK continuously corresponding to the selection of CK1 → C2 → CK3 → CK4 → CK5 → CK6 → CK1....Though what illustrate in the above-mentioned explanation is the situation of six phases, they similarly operate in the ten two phase situations.
Figure 11 shows and is used for adjusting a kind of structure example that circuit 103 provides the control circuit 104 of clock selection signal to the edge time of occurrence.As shown in figure 11, control circuit 104 comprises the control logic circuit 106 of the Δ ∑ modulator 602 with frequency data generator 601 and three values, and on having/and the clock selection signal of following ring register 603 produces circuit 105.Ring register 603 makes that the clock signal SECLK of state exchange and selection is synchronous, to produce first group of clock selection signal SEL1 to SEL12.Be imported into the Δ ∑ modulator 602 of three values from the frequency data FData of frequency data generator 601 outputs, and be converted into the control signal CSG of three values.On/following ring register 603 makes and selects conversion forward or backward, perhaps keeps it according to control signal CSG.Note that the cycle data generator has replaced the frequency data generator in phase place selection type frequency modulator as shown in Figure 1.
Figure 12 show as shown in figure 11 on/following ring register 603.Should on/following ring register 603 has D-type trigger circuit (D-FF) 501 to 512 and corresponding to the selection circuit 521 to 532 of these trigger circuit 501 to 512.The lead-out terminal of trigger circuit 501 to 512 is connected to the entry terminal (see figure 6) that the edge time of occurrence is adjusted first group of clock selection signal SEL1 to SEL12 in the circuit 103 respectively.
Select circuit 521 to 532 to constitute by the selector circuits of an output of three inputs, and by control signal (selector signal) the CSG control (seeing Figure 11) as the output of control logic circuit 106.More particularly, selecting circuit 521 to 532 is circuit of one that are used for according to three input ends of three-state output of control signal CSG.On the other hand, trigger circuit 501 to 512 are latched the output of selecting circuit 521 to 532 synchronously with the clock signal SECLK that selects, wherein the clock signal SECLK of Xuan Zeing is from modulated clock signal generating circuit output, and the output that will select circuit 521 to 532 is as first group of clock selection signal SEL1 to SEL12.Whereby, be in signal transition between first group of clock selection signal SEL1 to SEL12 of high level.
Figure 13 shows another structure example of control circuit 104.Control circuit 104 comprise have on/clock selection signal of following counter 401 and demoder 402 produces circuit 105, and is used to control the control logic circuit 106 that this clock selection signal produces circuit 105.Clock selection signal produces circuit 105 and exports first group of clock selection signal SEL1 to SEL12 according to the value of the control signal that provides from control logic circuit 106.Simultaneously, clock selection signal clock selection signal that circuit 105 activates desire according to the value of the control signal that provides from control logic circuit 106 is provided moves one or move one backward forward, perhaps keeps and does not change.
On/following counter 401 will output to demoder 402 as count value CTV corresponding to one value in " making progress ", " downwards " and " maintenance " three kinds of operations.CTV is consistent with count value, and demoder 402 activates one that is in high level among first group of clock selection signal SEL1 to SEL12.
Figure 14 shows the operation of control circuit 104 as shown in figure 13." be different in " the situation downwards with value representation in the situation that the value representation that operates in control signal CSG of control circuit 104 " makes progress " at control signal CSG.In the situation that value representation at control signal CSG " makes progress ", the signal that is in high level among first group of clock selection signal SEL1 to SEL12 changes so that as by the SE1 → SEL2 → SEL3 shown in the arrow AR1 → ...On the other hand, at the value representation of control signal CSG " in " the situation, the signal that is in high level among first group of clock selection signal SEL1 to SEL12 changes downwards so that as by the SEL4 → SEL3 → SEL2 shown in the arrow AR2 → ...
Figure 15 shows the structure of the Δ ∑ modulator 602 of three values as shown in figure 11.As shown in figure 15, this Δ ∑ modulation circuit has secondary structure, and has first to fourth totalizer 701,702,704 and 705, the digital quantizer 707 of delay circuit 703 and 706 and three values.Digital quantizer 707 output+Δs, 0 of these three values ,-control signal CS that should import in response in the Δ.About the selection of clock signal, when three the value with " conversion backward ", when " maintenance " is relevant with " conversion forward ", the frequency of modulated clock signal is controlled as f=f013/12 respectively, f=f0 and f=f011/12.
According to structure as shown in figure 15,, can be a frequency f 1 arbitrarily with the frequency control of modulated clock signal MCK by importing as frequency data FData by the value that following formula is represented.
Frequency data=Δ * (f1-f0)/(f0/12) ... (5)
Note that and to use bit Δ ∑ modulator replacement three value Δ ∑ modulators as shown in figure 15.In this case, two in a bit and " upwards transition ", " maintenances " and " downward transition " are relevant.
Thereby, can realize frequency modulation (PFM) by a kind of simple structure.Further, when the pulse width of charge pump was very big, the shake of PLL output tended to become bigger usually.On the other hand, in the modulated clock signal generating circuit,, can control the phase place of the clock signal that is used to feed back subtly, therefore, have the advantage that reduces shake by using selector switch according to embodiment 1.
According to the modulated clock-signal generator among first embodiment of the invention described above, but the modulated clock signal that the phase place range of value is not limited can be produced, and the EMI of electronic equipment can be reduced.
Secondly, please refer to the phase place selection type frequency modulator of Figure 16 understanding according to second embodiment of invention.As shown in figure 16, have according to the phase place selection type frequency modulator of second embodiment that multi-phase clock signal produces that circuit 101, modulated clock signal generating circuit 102, edge time of occurrence are adjusted circuit 103 and control circuit 104 and according to the phase place selection type frequency modulator of first embodiment shown in Figure 1.The place that is different from circuit as shown in Figure 1 is that PLL1205 is connected to the output of modulated clock signal generating circuit 102 in addition.In this embodiment, modulated clock signal MCK is by PLL 1205 outputs.According to this embodiment, the loop filter that the discrete periodic that takes place from the clock signal SELCLK of the selection of modulated clock signal generating circuit 102 outputs changes by PLL 1205 carries out filtering, therefore, can obtain the modulated clock signal of frequency change appropriateness.
Industrial applicibility
The present invention can be used in and will be used in the electronic equipment of carries out image data transfer etc. Selecting phasing type frequency modulator and Selecting phasing type frequency synthesizer.
Claims (6)
1, a kind of phase place selection type frequency modulator comprises:
The multi-phase clock signal generation device is used for producing the N phase clock signal with phase differential mutually from each signal;
Control device, be used for sequentially activating of first group of clock selection signal, wherein this clock selection signal is indicated the clock signal that chooses from the N phase clock signal of described multi-phase clock signal generation device output, and described first group of clock selection signal is corresponding to the N phase clock signal;
Edge time of occurrence adjusting gear, be used to adjust rising edge time of occurrence and/or negative edge time of occurrence from first group of clock selection signal of described control device output, with corresponding to N phase clock signal, export second group of clock selection signal from described multi-phase clock signal generation device output; And
The modulated clock signal generating apparatus, be used for state of activation according to described second group of clock selection signal of exporting from described edge time of occurrence adjusting gear, from described N phase clock signal, select a clock signal, select clock signal as modulated clock signal with output.
2, a kind of phase place selection type frequency modulator comprises:
The multi-phase clock signal generation device is used for producing the N phase clock signal with phase differential mutually from each signal;
Control device, be used for sequentially activating of first group of clock selection signal, wherein this clock selection signal is indicated the clock signal that chooses from the N phase clock signal of described multi-phase clock signal generation device output, and described first group of clock selection signal is corresponding to the N phase clock signal;
Edge time of occurrence adjusting gear, be used to adjust rising edge time of occurrence and/or negative edge time of occurrence from first group of clock selection signal of described control device output, with corresponding to N phase clock signal, export second group of clock selection signal from described multi-phase clock signal generation device output;
The modulated clock signal generating apparatus is used for the state of activation according to described second group of clock selection signal of exporting from described edge time of occurrence adjusting gear, selects a clock signal from described N phase clock signal, selects clock signal with output; And
PLL (phaselocked loop) device is used for receiving by the clock signal of described modulated clock signal generating apparatus selection with to carrying out filtering in the shake of the clock signal of selecting, to export modulated clock signal.
3, according to the phase place selection type frequency modulator of claim 1, wherein said edge time of occurrence adjusting gear is adjusted the rising edge time of occurrence and/or the negative edge time of occurrence of first group of clock selection signal, so that can not overlap according to the rising edge of clock signal time of occurrence of first clock selection signal selection that is activated by described selecting arrangement and/or the rising edge time of occurrence and/or the negative edge time of occurrence of negative edge time of occurrence and described second group of clock selection signal.
4, according to the phase place selection type frequency modulator of claim 2, wherein said edge time of occurrence adjusting gear is adjusted the rising edge time of occurrence and/or the negative edge time of occurrence of first group of clock selection signal, so that can not overlap according to the rising edge of clock signal time of occurrence of first clock selection signal selection that is activated by described selecting arrangement and/or the rising edge time of occurrence and/or the negative edge time of occurrence of negative edge time of occurrence and described second group of clock selection signal.
5, a kind of phase place selection type frequency synthesizer comprises:
Control device, be used for sequentially activating of described first group of clock selection signal, wherein this clock selection signal is indicated the clock signal that chooses the described N phase clock signal of phase differential having from the multi-phase clock signal generation device, and first group of clock selection signal is corresponding to the N phase clock signal;
Edge time of occurrence adjusting gear, be used to adjust rising edge time of occurrence and/or negative edge time of occurrence from first group of clock selection signal of described control device output, with corresponding to described N phase clock signal, export second group of clock selection signal from the output of multi-phase clock signal generation device; And
The modulated clock signal generating apparatus, be used for state of activation according to described second group of clock selection signal of exporting from described edge time of occurrence adjusting gear, from described N phase clock signal, select a clock signal, select clock signal as modulated clock signal with output;
Phase comparison device, the phase place that is used for the clock signal selected with the phase place of reference clock signal with by described modulated clock signal generating apparatus compares; And
The multi-phase clock signal generation device is used for producing described N phase clock signal based on the comparative result of described phase comparison device, and exports a described N phase clock signal as modulated clock signal.
6, according to the phase place selection type frequency synthesizer of claim 5, also comprise segmenting device, be used for the clock signal of being selected by the modulated clock signal generating apparatus is carried out frequency division, and the clock signal of output process frequency division is to described phase comparison device.
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