CN103580657B - Phase interpolation device and phase interpolation method - Google Patents
Phase interpolation device and phase interpolation method Download PDFInfo
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- CN103580657B CN103580657B CN201210268805.5A CN201210268805A CN103580657B CN 103580657 B CN103580657 B CN 103580657B CN 201210268805 A CN201210268805 A CN 201210268805A CN 103580657 B CN103580657 B CN 103580657B
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Abstract
The present invention relates to phase interpolation device, comprise: the first signal generating circuit, in order to produce first signal with first phase；3rd signal generating circuit, in order to produce the 3rd signal with second phase；4th/the 5th signal generating circuit, produces in the flrst mode and has the 4th signal of third phase, and does not the most produce the 4th signal and produce the 5th signal with this second phase；And phase interpolator, do not produce interpolated signal with the 4th signal, and produce this interpolated signal with this first signal, the 3rd signal and the 5th signal in this second mode.
Description
Technical field
The present invention is related to a kind of phase interpolation device and phase interpolation method, particularly with regard to estimating interpolation acts
And switch phase interpolation device and the phase interpolation method of the phase place being intended to interpolation in advance.
Background technology
Phase interpolation device is widely used in the electronic installation in modern times.Because phase interpolation device can use minority
Clock signal carry out interpolation and go out multiple clock signal with out of phase.Fig. 1 depicts the phase interpolation device of known technology
The block chart of 100.As it is shown in figure 1, the phase interpolation device 100 of known technology contains phase interpolator 101 and multiplexer
103、105.Multiplexer 103 is respectively provided with different even phase place (P in order to receive0、P2、P4、P6) clock signal CLK0、CLK2、
CLK4、CLK6And select one to export to phase interpolator 101, and multiplexer 105 has different strange phase place (P in order to receive1、
P3、P5、P7) clock signal CLK1、CLK3、CLK5、CLK7And select one to export to phase interpolator 101.Phase interpolator
101 can use the clock signal received to produce interpolation clock signal CIS.
It is well known, however, that phase interpolation device when switching is used for the clock signal of interpolation, easily produce unexpected prominent
Ripple.Fig. 2 (a)-(c) depicts in known technology, produces the schematic diagram of surging when producing interpolated signal.At the example shown in Fig. 2
In, phase interpolation device 100 first has phase place P with top0Clock signal CLK0With lower section, there is phase place P1Clock signal
CLK1Produce interpolation clock signal CIS, the most again by clock signal CLK0Switch to that there is clock signal CLK2Come and seasonal pulse is believed
Number CLK1Produce interpolation clock signal CIS.As shown in Fig. 2 (a), interpolation clock signal CIS is at time point T1、T2、T3、T4Ripple
Shape, is by clock signal CLK0With clock signal CLK1At time point T1、T2、T3、T4Waveform interpolation and go out.
But, as shown in Fig. 2 (b), when top is in order to the clock signal CLK of interpolation0It is intended to be switched to that there is phase place P2Time
Arteries and veins signal CLK2Time, can be because cannot switch moment and there is a transition condition, clock signal CLK under this state0Value can temporarily
Stay and cause mistake when producing interpolation clock signal CIS.For example, at the time point T of Fig. 2 (b)2Time, clock signal CLK2
Current potential be low and clock signal CLK1Current potential be also low, ought to interpolation to go out current potential be low interpolation clock signal CIS.But because of
For clock signal CLK0(the clock signal CLK being represented by dotted lines can be persisted when switching0), and clock signal CLK0At time point
T2Time current potential be high, interpolation clock signal CIS therefore can be made at time point T2Time be interpolated out surging P.Even if time point T2It
After the value of interpolation clock signal CIS be normally, but overall accuracy still can be impacted by surging P.Refer to Fig. 2
(c), time point T2The interpolated signal of back upper place has been switched to clock signal CLK2, therefore time point T3、T4Time, the meeting read
It is correct clock signal CLK2Value, therefore time point T3、T4Time can obtain correct interpolation clock signal CIS, but previously
Time point T2The surging P of Shi Zaocheng has produced and cannot eliminate.This type of mistake can make having of interpolation clock signal CIS prominent
Ripple or abnormal decay, and allow waveform become incorrect.
In order to solve such problem, association area proposes some solutions, and one of which is first to wait to have switched not
After synchronous clock signal one scheduled time, then produce interpolation clock signal.But such mechanism not only processing speed is relatively
Slowly, and needing to control respectively the action of switching and interpolation, the design that can make circuit is more complicated.
Summary of the invention
One purpose of the present invention, for providing a phase interpolation device and a phase interpolation method, is avoided in known technology
Surging problem.
One embodiment of the invention discloses a kind of phase interpolation device, comprises: the first signal generating circuit, in order to produce
There is the first signal of first phase；3rd signal generating circuit, in order to produce the 3rd signal with second phase；4th/
5th signal generating circuit, produces the 4th signal with third phase in the flrst mode, and does not produces
4th signal and produce the 5th signal with this second phase；And phase interpolator, the most not with this
4th signal produces interpolated signal, and produces with this first signal, the 3rd signal and the 5th signal in this second mode
This interpolated signal raw.
A kind of phase interpolation method can be obtained according to aforesaid embodiment, but because its step can be pushed away by previous embodiment
, therefore repeat no more in this.
According to aforesaid embodiment, can estimate and switch in advance for performing the signal phase of interpolation, known skill can be avoided
Surging problem in art and processing speed will not be reduced.And, by shared multiplexer and interpolation module, the face of circuit can be saved
Long-pending.
Accompanying drawing explanation
Fig. 1 depicts the block chart of the phase interpolation device of known technology.
Fig. 2 (a)-(c) depicts in known technology, produces the schematic diagram of surging when producing interpolated signal.
Fig. 3 depicts the block chart of phase interpolation device according to an embodiment of the invention.
Fig. 4 A and Fig. 4 B depicts the circuit diagram of a wherein demonstrative circuit structure of phase interpolator in Fig. 3.
Fig. 5 depicts the running schematic diagram of phase interpolation device according to an embodiment of the invention.
Fig. 6 depicts to produce the schematic diagram of the phase sequence of the clock signal of interpolated signal.
Fig. 7 depicts the flow chart of phase interpolation method according to an embodiment of the invention.
Main element symbol description
100,300 phase interpolation device
101,301 phase interpolator
302 control circuits
103,105,303,305,307,309 multiplexer
401,403,405,407 interpolation module
MP1、MP2、MP3、MP4PMOSFET
MN1、MN2、MN3、MN4NMOSFET
Detailed description of the invention
Fig. 3 depicts the block chart of phase interpolation device 300 according to an embodiment of the invention.As it is shown on figure 3, seasonal pulse letter
Number CLK0、CLK2、CLK4、CLK6、CLK8It is respectively provided with even phase place P0、P2、P4、P6、P8, and clock signal CLK1、CLK3、CLK5、
CLK7、CLK9It is respectively provided with strange phase place P1、P3、P5、P7、P9.Phase interpolation device 300 contains phase interpolator 301, multiplexer
303,305,307 and 309.Multiplexer 303,305 receives clock signal CLK0、CLK2、CLK4、CLK6、CLK8And export respectively
First clock signal CS1With the second clock signal CS2To phase interpolator 301.Multiplexer 307 receives clock signal CLK1、
CLK3、CLK5、CLK7、CLK9And export the 3rd clock signal CS3To phase interpolator 301.Multiplexer 309 receives clock signal
CLK1、CLK3、CLK5、CLK7、CLK9And export the 4th clock signal CS in the flrst mode4To phase interpolator 301, and in
The 5th clock signal CS is exported under two modes5To phase interpolator 301.3rd clock signal CS3With the 5th clock signal CS5Tool
There is identical phase place.Phase interpolator 301 is not the most with the 4th clock signal CS4Interpolation clock signal CIS, and
With the first clock signal CS under second pattern1, the second clock signal CS2, the 3rd clock signal CS3With the 5th clock signal CS5In
Insert out interpolation clock signal CIS.In the flrst mode, phase interpolator 301 can the first clock signal CS1, second seasonal pulse letter
Number CS2, and the 3rd clock signal CS3Its two generations interpolated signal of at least a part of which.If phase interpolation device 300 does not have multiplexing
During device 305, phase interpolator 301 is in the flrst mode with the first signal CS1And the 3rd signal CS3Produce this interpolated signal
CIS.The detailed action of phase interpolation device 300 will be in beneath detailed description.
Phase interpolator 301 can comprise various different circuit structure, Fig. 4 A and Fig. 4 B and depict phase interpolation in Fig. 3
The circuit diagram of a wherein demonstrative circuit structure of device 301.As shown in Figure 4 A, phase interpolator 301 contains phase interpolation mould
Block 401,403,405 and 407, each phase interpolation module all contains phase inverter INV1And INV2And switch SW1And SW2,
Utilize switch SW1And SW2Can determine that to use those signals to be used as interpolation is used.Phase interpolation module 401,403,405 and
The signal output of 407 is coupled together.Fig. 4 B depicts the more detailed circuit diagram of Fig. 4 A.In figure 4b, each phase interpolation mould
Block contains multiple PMOSFET (metal-oxide half field effect transistor, Metal-Oxide-Semiconductor Field-Effect
Transistor)MP1、MP2、MP3、MP4And NMOSFET MN1、MN2、MN3、MN4.These PMOSFET and NMOSFET are with series connection
Mode arranges, and signal is output in MP2And MN1Contact, and MP4And MN3Contact.The wherein PMOSFET MP in Fig. 4 B1
With NMOSFET MN2Define the phase inverter INV in Fig. 4 A1, and the PMOSFET MP in Fig. 4 B2With NMOSFET MN1Define
Switch SW in Fig. 4 A1.Same, in Fig. 4 B PMOSFET MP3With NMOSFET MN4Define the phase inverter in Fig. 4 A
INV2, and the PMOSFET MP in Fig. 4 B4With NMOSFET MN3Define the switch SW in Fig. 4 A2.Phase interpolator detailed
Structure and manner of execution are known by person familiar with the technology, therefore repeat no more in this.
Under will illustrate the function mode of phase interpolation device 300, can come more refering to Fig. 3, Fig. 4 A and Fig. 5 simultaneously
Understand present disclosure.In the example as shown in fig. 5, the first clock signal CS is assumed that1There is phase place P0(the most now Fig. 3
Multiplexer 303 exports clock signal CLK1As the first clock signal CS1), the second clock signal CS2There is phase place P0, the 3rd time
Arteries and veins signal CS3There is phase place P1, the 4th clock signal CS4There is phase place P9, and the 5th clock signal CS4There is phase place P1Say
Bright, it is not intended that in order to limit the present invention.Parameter 00,01,11,10 in Fig. 5 show respectively interpolation module 401,403,
The conducting state of 405 and 407.As a example by interpolation module 401 in Fig. 4 A, then represent switch SW when its state is 001And SW2
All it is not turned on.Contrary, switch SW is then represented when its state is 111And SW2It is both turned on.State 10 then indication circuit switch SW1
Conducting, switch SW2It is not turned on.State 01 then indication circuit switch SW1It is not turned on, switchs SW2Conducting.
Referring again to Fig. 5, as shown in state A in Fig. 5, the conducting state of conduction module 401,403,405 and 407 is respectively
Being 11,11,00,00, now the phase place of interpolation clock signal CIS isMultiplexer 309 is output as having phase place P9?
Four clock signal CS4, and be unused for producing interpolation clock signal CIS.Therefore, now the 4th clock signal CS4Leave unused for one
(idle) state, but also can be that other circuit use.And state B in Figure 5, conduction module 401,403,405 and 407
Conducting state is respectively 01,11,10,00, and the phase place of interpolation clock signal CIS isNow multiplexer 309 is defeated
Go out for having phase place P9The 4th clock signal CS4, and the output of multiplexer 309 be unused for produce interpolation clock signal CIS.And
In state C, the conducting state of conduction module 401,403,405 and 407 is respectively 00,11,11,00, interpolation clock signal CIS's
Phase place isThe now output of multiplexer 309 is still for having phase place P9The 4th clock signal CS4.Under this state, phase
Control circuit 302 in the interpolater 301 of position can be estimated in the next one according to stored phase sequence (will describe in detail in Fig. 6)
The phase place inserting clock signal CIS should beWhen two must be used to have the clock signal of phase place P1 to produce interpolation
Arteries and veins signal CIS, therefore can allow multiplexer 309 stop output the 4th clock signal CS4, change into exporting the 5th clock signal CS5。
When state D, the conducting state of conduction module 401,403,405 and 407 is respectively 00,01,11,10, now leads
Logical module 407 received signal has been to have phase place P1The 5th clock signal CS5, the therefore phase place of interpolation clock signal CIS
ForState E is then identical with state C, the conducting state of conduction module 401,403,405 and 407 is respectively 00,11,
11,00, now conduction module 407 received signal is still and has phase place P1The 5th clock signal CS5, therefore interpolation seasonal pulse
The phase place of signal CIS isIn the case of this, control circuit 302 can estimate next interpolation clock signal CIS's
Phase place should beIt is not necessary to use two to have phase place P1Clock signal produce interpolation clock signal CIS, therefore can
Multiplexer 309 is allowed to stop output the 5th clock signal CS5, change into exporting the 4th clock signal CS4.It is noted that aforesaid shape
State order, when can arbitrarily exchange or change, is not necessary to the arrangement followed in Fig. 5.
Fig. 6 depicts to produce the schematic diagram of the phase sequence of the clock signal of interpolated signal.State in Fig. 61,2,
3, state A in 4 respectively corresponding Fig. 5, B, C, D, in Fig. 6, the dark part indicated is for producing interpolation clock signal
Phase place.But, the state after state 4 and the state after state D in Fig. 5 differ, in the state of the 5th figure in Fig. 6
E, the phase place of the clock signal that interpolation module 407 receives can be from P1Become P9, but in the state 5 of Fig. 6, interpolation module 407 receives
The phase place of clock signal be still P1.It is to say, the phase sequence of the clock signal in order to produce interpolated signal is can be with
Meaning change.And via such configuration, control circuit can be allowed to estimate out which kind of phase place next stage can use, and decision is
No switching phase place.For example, when being intended to the state 8 of Fig. 6 is switched to state 9, can estimate in NextState in state 8, lead
The clock signal that logical module 405 is exported all will not be for interpolation, therefore can be by the output of multiplexer 309 from having phase place P1's
Clock signal switches to have phase place P3Clock signal.Embodiment according to Fig. 5 and Fig. 6, it may be appreciated that the priority of each state time
Sequence is the most revocable, therefore can preset to produce the phase sequence of the clock signal of interpolated signal, and according to now
Phase sequence is estimated next phase sequence and decides whether to switch the output of multiplexer according to this.
Also please noting that, the scope of the present invention is not only restricted to aforesaid embodiment.For example, phase interpolation device 300 is not
It is limited to use on clock signal.And, in the 5 embodiment of figure 5, also it is not intended to also exist two and has same
Clock signal (the such as CS of phase place1And CS2), namely the phase interpolation device 300 in Fig. 3 can only have multiplexer 303,307
With 309, not there is multiplexer 305.Additionally, the multiplexer 303,305,307 and 309 in the 3rd figure is not restricted to can only receive very
Phase place maybe can only receive even phase place one of which.And, multiplexer 303,305,307 and 309 can be by other signal generating circuits
Replace, as long as that is can produce have palpus phase place signal to the circuit of phase interpolator, all should the scope of the present invention it
In.Additionally, the aforesaid next one of estimating is in order to produce the step of the phase place of the clock signal of interpolated signal, can use and store in advance
Mode outside phase sequence is reached.The phase sequence of Fig. 5-6 arbitrarily change when can need according to difference, not with Fig. 5 and
Embodiment shown in Fig. 6 is limited.
According to aforesaid embodiment, available a kind of phase interpolation method, as shown in Figure 7 as contain the following step:
Step 701
Produce and there is the first signal of first phase (such as CS1)。
Step 703
Produce and there is the 3rd signal of second phase (such as CS3)。
Step 705
Produce in the flrst mode and there is the 4th signal of third phase (such as CS4), and the most do not produce
Four signals and produce and there is the 5th signal of this second phase (such as CS5)。
Step 707
Interpolated signal (such as state A of Fig. 5, state B, state C) is not produced with the 4th signal, and the
Interpolated signal (such as state D of Fig. 5) is produced with the first signal, the 3rd signal and the 5th signal under two modes.
According to aforesaid embodiment, can estimate and switch in advance for performing the signal phase of interpolation, known skill can be avoided
Surging problem in art and processing speed will not be reduced.And, by shared multiplexer and interpolation module, the face of circuit can be saved
Long-pending.
The foregoing is only presently preferred embodiments of the present invention, all impartial changes done according to scope of the present invention patent with
Modify, all should belong to the covering scope of the present invention.
Claims (13)
1. a phase interpolation device, comprises:
One first signal generating circuit, in order to produce one first signal with a first phase；
One the 3rd signal generating circuit, in order to produce one the 3rd signal with a second phase；
One the 4th/the 5th signal generating circuit, produces under a first mode and has one the 4th signal of a third phase, and
Do not produce the 4th signal under one second pattern and produce one the 5th signal with this second phase；And
One phase interpolator, produces an interpolation letter with at least two signal in addition to the 4th signal in the first mode
Number, and produce this interpolated signal with this first signal, the 3rd signal and the 5th signal in this second mode；
Wherein this first phase is different from this second phase and this third phase.
2. phase interpolation device as claimed in claim 1, it is characterised in that this phase interpolator, in the first mode with
This first signal and the 3rd signal produce this interpolated signal.
3. phase interpolation device as claimed in claim 1, it is characterised in that also comprise:
One secondary signal produces circuit, in order to produce a secondary signal with this first phase；
Wherein this phase interpolator, in the first mode with this first signal, this secondary signal and the 3rd signal wherein
At least its two produce this interpolated signal, and in this second mode with this first signal, this secondary signal, the 3rd signal and
5th signal produces this interpolated signal.
4. phase interpolation device as claimed in claim 1, its spy is, also comprises a control circuit, in order to estimate this phase place
Interpolater is the need of using the 5th signal to produce this interpolated signal, if judging, this phase interpolator needs to use the 5th
Signal produces this interpolated signal, then, before this phase interpolator produces this interpolated signal, allow the 4th/the 5th signal produce in advance
Raw circuit does not produce the 4th signal and produces the 5th signal.
5. phase interpolation device as claimed in claim 4, it is characterised in that this phase interpolation device stores for producing this
The phase sequence of the clock signal of interpolated signal, and estimate this phase interpolator the need of using this according to this phase sequence
5th signal.
6. phase interpolation device as claimed in claim 1, it is characterised in that this first phase be strange phase place and even phase place wherein
One of phase place, and this second, third phase place is strange phase place and even phase place another phase place wherein.
7. phase interpolation device as claimed in claim 6, it is characterised in that this first signal generating circuit, the 3rd signal
Produce circuit and the 4th/the 5th signal generating circuit is multiplexer, the letter that wherein this first signal generating circuit is received
Number it is and to have what the signal of even phase place, the 3rd signal generating circuit and the 4th/the 5th signal generating circuit were received
Signal is the signal with strange phase place.
8. a phase interpolation method, comprises:
Produce one first signal with a first phase；
Produce one the 3rd signal with a second phase；
Under a first mode, produce one the 4th signal with a third phase, and do not produce the 4th under one second pattern
Signal and produce one the 5th signal with this second phase；Wherein this first phase and this second phase and this third phase
Different；And
An interpolated signal is produced in the first mode with at least two signal in addition to the 4th signal, and at this second mould
This interpolated signal is produced with this first signal, the 3rd signal and the 5th signal under formula.
9. phase interpolation method as claimed in claim 8, it is characterised in that this phase interpolator, in the first mode with
This first signal and the 3rd signal produce this interpolated signal.
10. phase interpolation method as claimed in claim 8, it is characterised in that also comprise:
Produce a secondary signal with this first phase；And
This interpolated signal is produced in the first mode with this first signal, this secondary signal and the 3rd signal, and at this
This interpolated signal is produced with this first signal, this secondary signal, the 3rd signal and the 5th signal under second pattern.
11. phase interpolation method as claimed in claim 8, it is characterised in that also comprise:
Estimate the need of using the 5th signal to produce this interpolated signal；And
If judging to need to use the 5th signal, then before producing this interpolated signal, stop in advance producing the 4th signal and producing
Raw 5th signal.
12. phase interpolation method as claimed in claim 11, it is characterised in that also comprise:
Store the phase sequence being used for producing the clock signal of this interpolated signal；And
Estimate the need of using the 5th signal to produce this interpolated signal according to this phase sequence.
13. phase interpolation method as claimed in claim 8, it is characterised in that this first phase be strange phase place and even phase place its
One of phase place, and this second, third phase place is strange phase place and even phase place another phase place wherein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210268805.5A CN103580657B (en) | 2012-07-31 | 2012-07-31 | Phase interpolation device and phase interpolation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210268805.5A CN103580657B (en) | 2012-07-31 | 2012-07-31 | Phase interpolation device and phase interpolation method |
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| CN103580657A CN103580657A (en) | 2014-02-12 |
| CN103580657B true CN103580657B (en) | 2016-12-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1720493A (en) * | 2002-12-06 | 2006-01-11 | 哉英电子股份有限公司 | Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type |
| TW201023518A (en) * | 2008-12-11 | 2010-06-16 | Hynix Semiconductor Inc | Multi-phase clock signal generating circuit having improved phase difference and a controlling method thereof |
| CN101465633B (en) * | 2007-12-21 | 2012-05-23 | 瑞昱半导体股份有限公司 | Device for generating signal |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100543465B1 (en) * | 2003-08-04 | 2006-01-20 | 고려대학교 산학협력단 | Apparatus and method generating delayed clock signal |
| US7301410B2 (en) * | 2006-03-07 | 2007-11-27 | International Business Machines Corporation | Hybrid current-starved phase-interpolation circuit for voltage-controlled devices |
-
2012
- 2012-07-31 CN CN201210268805.5A patent/CN103580657B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1720493A (en) * | 2002-12-06 | 2006-01-11 | 哉英电子股份有限公司 | Frequency modulator apparatus of phase selection type, and frequency synthesizer of phase selection type |
| CN101465633B (en) * | 2007-12-21 | 2012-05-23 | 瑞昱半导体股份有限公司 | Device for generating signal |
| TW201023518A (en) * | 2008-12-11 | 2010-06-16 | Hynix Semiconductor Inc | Multi-phase clock signal generating circuit having improved phase difference and a controlling method thereof |
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| CN103580657A (en) | 2014-02-12 |
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