CN1716594A - Separate power source type static discharge protective circuit and integrated circuit using such circuit - Google Patents
Separate power source type static discharge protective circuit and integrated circuit using such circuit Download PDFInfo
- Publication number
- CN1716594A CN1716594A CN 200410059497 CN200410059497A CN1716594A CN 1716594 A CN1716594 A CN 1716594A CN 200410059497 CN200410059497 CN 200410059497 CN 200410059497 A CN200410059497 A CN 200410059497A CN 1716594 A CN1716594 A CN 1716594A
- Authority
- CN
- China
- Prior art keywords
- supply line
- power supply
- esd protection
- diode
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The electrostatic discharge protection circuit with separate power source is coupled across the first power source line and the second power source line, and consists of the first diode with the positive pole connected to the first power source line; one MOS semiconductor element with drain connected to the negative pole of the first diode, source connected to the second power source line and gate; and one second diode with positive pole connected to the second power source line and the negative pole connected to the first power source line. The first diode and the MOS semiconductor element constitute one SCR structure to provide electrostatic discharge path.
Description
Technical field
The present invention relates to a kind of ESD protection circuit, the integrated circuit that particularly relates to a kind of separate power supplies formula ESD protection circuit and use this circuit.
Background technology
In integrated circuit, the static because of the touching of human body etc. produces tends to enter into inner circuit through the output and input pins of integrated circuit (IC) wafer.Static also is very big voltage pulse usually; the high voltage of moment can cause damage to the internal circuit of integrated circuit; make the disabler of integrated circuit; even damage; therefore between output/input terminal and internal circuit, tend to dispose so-called ESD protection circuit (electrostaticdischargeprotectioncircuit; ESDprotectioncircuit); the electrostatic energy that makes generation is guided the ic power supply line via the discharge path that ESD protection circuit provides.
In mixed mode signal integrated circuit (IC), that is inner comprising among the hybrid integrated circuit IC of analogous circuit and digit circuit, for the factor of noise, analogous circuit normally separates with the indivedual employed power supply lines of digit circuit.Because the design of this kind separate power supplies line, the noise that produces on the numerical digit power supply line because fast state shifts in the digit circuit can not be passed on the power supply line of analogous circuit.See also shown in Figure 1, be this kind framework existing known ESD protection circuit an I/O pin to I/O pin or power pin to the esd event of power pin, the ESD electric current can't be only by a power line of width metal lines among the IC.When the interface that runs between the two separate power supplies lines, the ESD electric current can be by the path of most fragile.Usually, internal damage can occur in interface circuit.Therefore, the design of separate power supplies line bus-bar can undermine the obdurability (robustness) of IC product.
Seeing also shown in Figure 2ly, is a kind of charge member model (Charged-DeviceModel, electrostatic discharge protective circuit CDM).This kind framework also can run into very big problem in the IC of separate power supplies product.In the esd event of CDM, electrostatic charge can be stored in the matrix (bulk) of IC at the beginning, is discharged into the weld pad (pad) that is connected ground connection afterwards again.The existing known CDMESD protective circuit of this kind provides two kinds of paths; the first is via the CDM clamped circuit; it two is via the bidirectional diode string that is connected between two power supply lines (VDD_I/O and VDD_Internal, and VSS_I/O and VSS_Internal).If do not have this bidirectional diode string, under high ESD electric current, some CDM electric current can destroy input lock oxide layer.
See also shown in Figure 3ly, be U.S. Pat 6,075,686 disclosed ESD protection circuit structures.This circuit is the diode string that configuration oppositely is connected side by side between first power supply line and second source supply line.In addition, Fig. 4 is a U.S. Pat 6,040,968 disclosed ESD protection circuit structures.This circuit is the diode that configuration oppositely is connected side by side between first power supply line and second source supply line.But this kind uses diode that efficient electrostatic discharge (ESD) protection measure still can not be provided.
This shows that above-mentioned existing ESD protection circuit and integrated circuit obviously still have inconvenience and defective, and demand urgently further being improved in structure and use.In order to solve the problem that ESD protection circuit and integrated circuit exist; relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly; but do not see always that for a long time suitable design finished by development; and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.
Because the defective that above-mentioned existing ESD protection circuit and integrated circuit exist; the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge; and the utilization of cooperation scientific principle; actively studied innovation; in the hope of the separate power supplies formula ESD protection circuit of founding a kind of new structure and the integrated circuit that uses this circuit; can improve general existing ESD protection circuit and integrated circuit, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.
Summary of the invention
The objective of the invention is to; overcome the defective that existing ESD protection circuit exists; and provide a kind of separate power supplies formula ESD protection circuit of new structure; technical problem to be solved is to make it can solve the electrostatic discharge (ESD) protection between the identical polar different electrical power line among the hybrid IC effectively, thereby is suitable for practicality more.
Another object of the present invention is to; overcome the defective that existing integrated circuits exists; and a kind of integrated circuit that uses this circuit, technical problem to be solved are provided is to make it can be in order to solve the electrostatic discharge (ESD) protection between the identical polar different electrical power line among the hybrid IC.Thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of separate power supplies formula ESD protection circuit according to the present invention's proposition, be coupled between one first power supply line and the second source supply line, this separate power supplies formula ESD protection circuit comprises: one first diode, have an anode and a negative electrode, wherein this anode is coupled to this first power supply line; One first metal oxide semiconductor device has a gate, one source pole and a drain, and wherein this drain negative electrode and this source electrode of being coupled to this first diode is coupled to this second source supply line; And one second diode, have an anode and a negative electrode, wherein this anode is coupled to this second source supply line, this negative electrode is coupled to this first power supply line, wherein this first diode and this first metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that an electrostatic discharging path to be provided.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid separate power supplies formula ESD protection circuit; it more comprises one second metal oxide semiconductor device; it has a gate, one source pole and a drain; wherein this drain negative electrode and this source electrode of being coupled to this second diode is coupled to this first power supply line, makes this second diode and this second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first metal oxide semiconductor device are N type metal oxide semiconductor element.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first metal oxide semiconductor device is the P-type mos element.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first with this second metal oxide semiconductor device be N type metal oxide semiconductor element.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first with this second metal oxide semiconductor device be the P-type mos element.
The object of the invention to solve the technical problems also adopts following technical scheme to realize.A kind of separate power supplies formula ESD protection circuit according to the present invention's proposition, be coupled between one first power supply line and the second source supply line, this separate power supplies formula ESD protection circuit comprises: a plurality of first diodes, have an anode and a negative electrode respectively, the connection that is one another in series, wherein this anode of first this first diode is coupled to this first power supply line; One first metal oxide semiconductor device has a gate, one source pole and a drain, and wherein this drain negative electrode and this source electrode of being coupled to last this first diode is coupled to this second source supply line; And a plurality of second diodes, have an anode and a negative electrode respectively, connection is one another in series, wherein this anode of first this second diode is coupled to this second source supply line, and this negative electrode of last this second diode is coupled to this first power supply line, this first diode and this second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that an electrostatic discharging path to be provided.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid separate power supplies formula ESD protection circuit; it more comprises one second metal oxide semiconductor device; have a gate, one source pole and a drain; wherein this drain this negative electrode and this source electrode of being coupled to last this second diode is coupled to this first power supply line; make this second diode and this second metal oxide semiconductor device constitute structure, so that an electrostatic discharging path to be provided with parasitic silicon controlled rectifier.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first metal oxide semiconductor device are N type metal oxide semiconductor element.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first metal oxide semiconductor device is the P-type mos element.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first with this second metal oxide semiconductor device be N type metal oxide semiconductor element.
Aforesaid separate power supplies formula ESD protection circuit, wherein said first with this second metal oxide semiconductor device be the P-type mos element.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of integrated circuit according to the present invention's proposition, destroy in order to protect one first and one second internal circuit to avoid static discharge, this first internal circuit is coupled between one first high power supply line and the one first low power supply line, this second internal circuit is coupled between one second high power supply line and the one second low power supply line, wherein this first with this second high power supply line be isolated from each other and this first with this second low power supply line be to be isolated from each other, this integrated circuit comprises: one first ESD protection circuit is coupled between this first high power supply line and this first low power supply line; One second ESD protection circuit is coupled between this second high power supply line and this second low power supply line; One the 3rd ESD protection circuit, be coupled between this first high power supply line and this second high power supply line, when appearing at this first or second high power supply line when a static discharge, optionally connect this first high power supply line and this second high power supply line, wherein the 3rd ESD protection circuit comprises one first diode string and the one first metal-oxide semiconductor (MOS) electric crystal that is one another in series at least, and one second diode string, be connected in reverse parallel in this first diode string and this first metal-oxide semiconductor (MOS) electric crystal, wherein when this first diode string and this first metal-oxide semiconductor (MOS) electric crystal start because of the static discharge phenomenon, form a parasitic silicon controlled rectifier, so that a discharge path to be provided; And one the 4th ESD protection circuit; be coupled in this first low power supply line and this second low power supply line; in order to appear at when a static discharge this first or during this second low power supply line; optionally connect between this first low power supply line and this second low power supply line; wherein the 4th ESD protection circuit comprises one the 3rd diode string and the one second metal-oxide semiconductor (MOS) electric crystal that is one another in series at least; and one the 4th diode string; be connected in reverse parallel in the 3rd diode string and this second metal-oxide semiconductor (MOS) electric crystal; wherein when the 3rd diode string and this second metal-oxide semiconductor (MOS) electric crystal start because of the static discharge phenomenon; form a parasitic silicon controlled rectifier, so that a discharge path to be provided.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid integrated circuit, wherein said first with this second metal-oxide semiconductor (MOS) electric crystal be one of N type or P type.
Aforesaid integrated circuit, first and second diode string of wherein said the 3rd ESD protection circuit is at least a diode respectively, and the 3rd and the 4th diode string of the 4th ESD protection circuit is at least a diode respectively.
Aforesaid integrated circuit, the series connection number of wherein said first and second diode string is by the pressure reduction decision of this first high power supply line and this second high power supply line.
Aforesaid integrated circuit, the wherein said the 3rd is determined by this first low power supply line pressure reduction with this second low power supply line with the number of connecting of the 4th diode string.
Aforesaid integrated circuit; wherein said the 3rd ESD protection circuit more comprises one the 3rd metal-oxide semiconductor (MOS) electric crystal; connect with this second diode string; this first with the 3rd metal-oxide semiconductor (MOS) electric crystal be couple to respectively this second with this first high power supply line; and the 4th ESD protection circuit more comprises one the 4th metal-oxide semiconductor (MOS) electric crystal; connect with the 4th diode string, this second with the 4th metal-oxide semiconductor (MOS) electric crystal be couple to respectively this second with this first low power supply line.
Aforesaid integrated circuit, wherein said first to the 4th metal-oxide semiconductor (MOS) electric crystal be N type or P type both one of.
Aforesaid integrated circuit, it more comprises: one first input ESD protection circuit is coupled between an input weld pad, this first high power supply line and this first low power supply line of this first internal circuit, this first internal circuit; And one second input ESD protection circuit, be coupled between input weld pad, this second high power supply line and this second low power supply line of this second internal circuit, this second internal circuit.
The present invention compared with prior art has tangible advantage and beneficial effect.By above technical scheme as can be known, major technique of the present invention thes contents are as follows:
For reaching above-mentioned and other purposes, the present invention proposes a kind of separate power supplies formula ESD protection circuit, is coupled between first power supply line and the second source supply line.Separate power supplies formula ESD protection circuit comprises: first diode, have anode and negative electrode, and wherein anode is coupled to first power supply line; First metal oxide semiconductor device has gate, source electrode and drain, and wherein the drain negative electrode and the source electrode that are coupled to first diode is coupled to the second source supply line; And second diode, have anode and negative electrode, wherein anode is coupled to the second source supply line, and negative electrode is coupled to first power supply line.First diode and this first metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that electrostatic discharging path to be provided.
According to one embodiment of the invention, aforementioned separate power supplies formula ESD protection circuit can more comprise second metal oxide semiconductor device, has gate, source electrode and drain.Negative electrode and source electrode that drain is coupled to second diode are coupled to first power supply line, make second diode and second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier.So two-way, all can provide the discharge path of structure with parasitic silicon controlled rectifier from first to second source supply line or second to first power supply line.
According to one embodiment of the invention, in aforementioned separate power supplies formula ESD protection circuit, first metal oxide semiconductor device can be N type or P-type mos element.In addition, in another embodiment, first and second metal oxide semiconductor device can be N type or P-type mos element.
In addition, the present invention more provides a kind of separate power supplies formula ESD protection circuit, is coupled between first power supply line and the second source supply line.Separate power supplies formula ESD protection circuit comprises: a plurality of first diodes, have anode and negative electrode respectively, and connection is one another in series.Wherein the anode of first first diode is coupled to first power supply line; First metal oxide semiconductor device has gate, source electrode and drain, and wherein the drain negative electrode and the source electrode that are coupled to last first diode is coupled to the second source supply line; And a plurality of second diodes, have anode and negative electrode respectively, the connection that is one another in series, wherein the anode of first this second diode is coupled to the second source supply line, and the negative electrode of last second diode is coupled to first power supply line.Those first diodes and this second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that an electrostatic discharging path to be provided.
According to one embodiment of the invention, aforesaid separate power supplies formula ESD protection circuit can more comprise second metal oxide semiconductor device, has gate, source electrode and drain.Negative electrode and source electrode that drain is coupled to last second diode are coupled to first power supply line, make those second diodes and second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that an electrostatic discharging path to be provided.So two-way, all can provide the discharge path of structure with parasitic silicon controlled rectifier from first to second source supply line or second to first power supply line.
According to one embodiment of the invention, in the aforesaid separate power supplies formula ESD protection circuit, first metal oxide semiconductor device can be N type or P-type mos element.In another embodiment, first and second metal oxide semiconductor device can be N type or P-type mos element.
The present invention more proposes a kind of integrated circuit, destroys in order to protect first and second internal circuit to avoid static discharge.First internal circuit is coupled between the first high power supply line and the first low power supply line, and second internal circuit is coupled between the second high power supply line and the second low power supply line.First is to be isolated from each other and first and second low power supply line is to be isolated from each other with this second high power supply line.First and this second high power supply line between have pressure reduction, and have pressure reduction between first and second low power supply line.Integrated circuit comprises first ESD protection circuit, is coupled between the first high power supply line and the first low power supply line; Second ESD protection circuit is coupled between the second high power supply line and the second low power supply line; The 3rd ESD protection circuit, be coupled between the first high power supply line and the second high power supply line, when appearing at the first or second high power supply line when static discharge, optionally connect the first high power supply line and the second high power supply line, wherein the 3rd ESD protection circuit comprises the first diode string and the first metal-oxide semiconductor (MOS) electric crystal that is one another in series at least, and the second diode string, be connected in reverse parallel in this first diode string and the first metal-oxide semiconductor (MOS) electric crystal, wherein when the first diode string and the first metal-oxide semiconductor (MOS) electric crystal start because of the static discharge phenomenon, form parasitic silicon controlled rectifier, so that a discharge path to be provided; And the 4th ESD protection circuit; be coupled between the first low power supply line and the second low power supply line; when appearing at the first or second low power supply line when static discharge; optionally connect this first low power supply line and this second low power supply line; wherein the 4th ESD protection circuit comprises the 3rd diode string and the second metal-oxide semiconductor (MOS) electric crystal that is one another in series at least; and the 4th diode string; be connected in reverse parallel in the 3rd diode string and the second metal-oxide semiconductor (MOS) electric crystal; wherein when the 3rd diode string and the second metal-oxide semiconductor (MOS) electric crystal start because of the static discharge phenomenon; form a parasitic silicon controlled rectifier, so that a discharge path to be provided.
According to one embodiment of the invention, first and this second metal-oxide semiconductor (MOS) electric crystal of aforementioned integrated circuit are one of N type or P type.
According to one embodiment of the invention; first and second diode string of the 3rd ESD protection circuit of aforementioned integrated circuit is at least a diode respectively, and the 3rd and the 4th diode string of the 4th ESD protection circuit is at least a diode respectively.According to one embodiment of the invention, the series connection number of first and second diode string is by the pressure reduction decision of the first high power supply line and the second high power supply line.The 3rd is determined by the pressure reduction of the first low power supply line with the second low power supply line with the number of connecting of the 4th diode string.
According to one embodiment of the invention, the 3rd ESD protection circuit in the aforementioned integrated circuit can more comprise the 3rd metal-oxide semiconductor (MOS) electric crystal, connects with the second diode string.The first and the 3rd metal-oxide semiconductor (MOS) electric crystal is couple to the second and first high power supply line respectively, and the 4th ESD protection circuit can more comprise the 4th metal-oxide semiconductor (MOS) electric crystal, connects with the 4th diode string.The second and the 4th metal-oxide semiconductor (MOS) electric crystal is couple to the second and first low power supply line respectively.
According to one embodiment of the invention, first to fourth metal-oxide semiconductor (MOS) electric crystal can be N type or P type both one.
According to one embodiment of the invention, aforementioned integrated circuit can more comprise: the first input ESD protection circuit is coupled between input weld pad, the first high power supply line and the first low power supply line of first internal circuit, first internal circuit; And the second input ESD protection circuit, be coupled between the input weld pad, the second high power supply line and the second low power supply line of second internal circuit, second internal circuit.
Via as can be known above-mentioned, the integrated circuit that the invention relates to a kind of separate power supplies formula ESD protection circuit and use this circuit.This separate power supplies formula ESD protection circuit is coupled between first power supply line and the second source supply line.Separate power supplies formula ESD protection circuit comprises: first diode, have anode and negative electrode, and wherein anode is coupled to first power supply line; First metal oxide semiconductor device has gate, source electrode and drain, and wherein the drain negative electrode and the source electrode that are coupled to first diode is coupled to this second source supply line; And second diode, have anode and negative electrode, wherein anode is coupled to the second source supply line, and negative electrode is coupled to first power supply line.First diode and first metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, with when static discharge produces, provide electrostatic discharging path.
By technique scheme, separate power supplies formula ESD protection circuit of the present invention and use the integrated circuit of this circuit to have following advantage at least:
1, separate power supplies formula ESD protection circuit of the present invention can solve the electrostatic discharge (ESD) protection between the identical polar different electrical power line among the hybrid IC effectively, thereby be suitable for practicality more.
2, integrated circuit of the present invention can be in order to solve the electrostatic discharge (ESD) protection between the identical polar different electrical power line among the hybrid IC.Thereby be suitable for practicality more.
In sum; the separate power supplies formula ESD protection circuit of special construction of the present invention and the integrated circuit that uses this circuit; have above-mentioned many advantages and practical value; and in like product, do not see have similar structural design to publish or use and really genus innovation; no matter it all has bigger improvement on the structure of product or function; have large improvement technically; and produced handy and practical effect; and more existing ESD protection circuit and integrated circuit have the multinomial effect of enhancement; thereby be suitable for practicality more; and have the extensive value of industry, really be a novelty; progressive; practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by going out preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the schematic diagram that has the ESD protection circuit of known separate power supplies line now.
Fig. 2 is the schematic diagram that has the electrostatic discharge protective circuit of known a kind of charge element model now.
Fig. 3 is a U.S. Pat 6,075,686 disclosed ESD protection circuit structure charts.
Fig. 4 is a U.S. Pat 6,040,968 disclosed ESD protection circuit structure charts.
Fig. 5 is the schematic diagram of separate power supplies ESD protection circuit of the present invention.
Fig. 6 is the cut-away section schematic diagram of the separate power supplies ESD protection circuit of Fig. 5.
Fig. 7 is the generalized section that is used for illustrating the operating principle of separate power supplies ESD protection circuit of the present invention.
Fig. 8 is the schematic diagram of the another kind of embodiment of ESD protection circuit of the present invention.
Fig. 9 is the schematic diagram of the another kind of embodiment of ESD protection circuit of the present invention.
Figure 10 is the schematic diagram of the another kind of embodiment of ESD protection circuit of the present invention.
Figure 11 is the schematic diagram of the another kind of embodiment of ESD protection circuit of the present invention.
Figure 12 is the schematic diagram of the another kind of embodiment of ESD protection circuit of the present invention.
Figure 13 is the schematic diagram of the another kind of embodiment of ESD protection circuit of the present invention.
Figure 14 is a schematic diagram of using first application examples of separate power supplies ESD protection circuit of the present invention.
Figure 15 is a schematic diagram of using second application examples of separate power supplies ESD protection circuit of the present invention.
Figure 16 is a schematic diagram of using the 3rd application examples of separate power supplies ESD protection circuit of the present invention.
Da1, Db1: diode
Mn1: electric crystal
TA, TC: terminal
100: substrate 102N type wellblock
The 104:P type is also distinguished 104106 isolation structures
112:P type doped region 114N type doped region
122,126:N type doped region
128: gate electrode 130P type picks up doped region
202: the first internal circuit 204 second internal circuits
206: input weld pad 208 input weld pads
210,212: separate power supplies formula ESD protection circuit
214,216: ESD protection circuit
210a/b, 212a/b: separate power supplies formula ESD protection circuit
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; below in conjunction with accompanying drawing and preferred embodiment; separate power supplies formula ESD protection circuit that foundation the present invention is proposed and its embodiment of integrated circuit, structure, feature and the effect thereof of using this circuit, describe in detail as after.
Seeing also shown in Figure 5ly, is the schematic diagram of separate power supplies ESD protection circuit of the present invention.This separate power supplies ESD protection circuit comprises two diode Da1, Db1 and metal-oxide semiconductor (MOS) (MOS) electric crystal Mn1.The anode of diode Da1 is connected to end points TA, and the source electrode that negative electrode is connected to the drain NMOS electric crystal Mn1 of NMOS electric crystal Mn1 is connected to another terminal TC, and the series opposing of diode Db1 and diode Da1 and NMOS electric crystal Mn1 is connected in parallel.The anode of diode Db1 is connected to terminal TC, and negative electrode is connected to terminal TA, and then the anode of diode Da1.Terminal TA then is connected respectively to different power supply lines with TC, two high power supply lines for example, or for example be two low power supply lines of ground connection.
Seeing also shown in Figure 6ly, is the cut-away section schematic diagram of the separate power supplies ESD protection circuit of Fig. 5, the circuit diagram when promptly Fig. 6 draws the separate power supplies ESD protection circuit implemented with semiconductor integrated circuit.As shown in Figure 6, profile is the section legend along diode Da1 and electric crystal Mn1, is familiar with this skill person diode Db1 part of can correspondence drawing.As shown in Figure 6, it provides a substrate 100, and this substrate can be the substrate of P type.In this substrate 100, have N type wellblock 102 and p type wells district 104.In N type wellblock, form respectively as the anode of diode Da1 and the P type doped region 112 and N type doped region 114 of negative electrode, separate with isolation structure 106 therebetween.This isolation structure 106 can be an oxidation (fieldoxidationFOD) isolation structure or shallow slot isolation structure etc.In p type wells district 104, form respectively as the drain of NMOS electric crystal Mn1 and the N type doped region 122,126 of source electrode, be channel region in the middle of both, then form the gate electrode 128 of NMOS electric crystal Mn1 on it.The P type picks up 130 next-door neighbours of doped region N type doped region 126, as the usefulness of voltage pick-up.122 N type doped regions 114 with diode of the N type doped region of drain are isolated with isolation structure 106.
In Fig. 6, P type doped region 112 (anode of diode Da1), N type well 102, P type substrate 100, p type wells 104, N type doped region 126/P type well pick up formation thyristors (silicon-controlledrectifier) such as doped region 130.The present invention promptly utilizes diode in series and MOS electric crystal, and this framework the parasitic thyristor that exists reach the action of ESD protection circuit.This parasitic silicon controlled rectifier can be activated when the ESD electric current produces, to form discharge path.
See also Fig. 5 and shown in Figure 6, under normal operation, diode Db1 provides the voltage isolation capabilities of a diode cut-ff voltage (cut-involtage) to the path of terminal TA at terminal TC.If at the noise voltage of terminal TC during less than the cut-ff voltage of diode Db1, just noise can not arrive terminal TA place via the diode Db1 of ESD protection circuit.Otherwise, as at the noise voltage of terminal TC during greater than the cut-ff voltage of diode Db1, just noise can arrive terminal TA place via the diode Db1 of ESD protection circuit.
In addition, under normal operation, diode Da1 also provides the voltage isolation capabilities of a diode cut-ff voltage, and NMOS electric crystal Mn1 then provides a hundreds of approximately extremely resistance of thousands of ohm at terminal TA to the path of terminal TC.The resistance that NMOS electric crystal Mn1 is carried under normal operation can reduce through the accurate position of the noise of NMOS electric crystal Mn1.In other words, can utilize the gate voltage position standard of control NMOS electric crystal Mn1, to reach different isolating powers.For example provide a high voltage at gate, can make the drain of NMOS electric crystal Mn1 is hundreds of to thousands of ohms to the equivalent resistance between source electrode.In addition, for example provide an electronegative potential when gate, then almost can be equivalent between the source electrode of NMOS electric crystal Mn1 and drain for opening circuit, make its impedance up to more than 9 power ohms of 10.
When electrostatic discharge event takes place, for example static discharge produces at terminal TC, and terminal TA is when being connected to relative earth terminal, NMOS electric crystal Mn1 is for closing, diode Db1 then is a forward bias voltage drop, so static discharge current just from terminal TC, is guided the terminal TA of ground connection apace via diode Db1.
Secondly, when static discharge produces at terminal TA, and terminal TC is when being connected to relative earth terminal, and discharge path and the mechanism of this moment can be illustrated by Fig. 7.See also shown in Figure 7ly, be the generalized section of the operating principle that is used for illustrating separate power supplies ESD protection circuit of the present invention.Principle of the present invention is to utilize the parasitic silicon controlled rectifier of the circuit shown in Fig. 5 and 6 to reach the effect of electrostatic discharge (ESD) protection.As shown in Figure 7, when static discharge when terminal TA produces, at the beginning, diode Da1 is a forward bias voltage drop, is applied to the voltage Vg1 conducting NMOS electric crystal Mn1 of the gate of NMOS electric crystal Mn1.At this moment, 1. initial current can flow into along the path through diode Da1 and arrive NMOS electric crystal Mn1.Please cooperate and consult shown in Figure 5ly, electric current through N type well 102, arrives the negative electrode (the N type of Fig. 7 mixes district 114) of diode Da1 from the anode (the P type of Fig. 7 mixes district 112) that terminal TA flows into diode Da1.Afterwards, mix the drain (the N type of Fig. 7 mixes district 122) that district 114 arrives NMOS electric crystal Mn1 via the N type again, the source electrode (the N type of Fig. 7 mixes district 126) through passage arrival NMOS electric crystal Mn1 arrives terminal TC again.
This initial current can trigger parasitic thyristor, makes the ESD electric current 2. flow to terminal TC via the path.Initial current I by terminal TA after 1. the path flows to terminal TC, parasitic thyristor just is activated, make static discharge current mix district 112, N type well 102, P type substrate 100, p type wells 104, N type doped region 126 (source electrode of NMOS electric crystal Mn1), and arrive terminal TC through the P of Fig. 7 type.
Seeing also shown in Figure 8ly, is the another kind of execution mode of separate power supplies ESD protection circuit of the present invention.As shown in Figure 8, the circuit of Fig. 8 is essentially the variation of Fig. 5.That is, the terminal TA among Fig. 5 is copied to the position of terminal TC to terminal TA to the combination of circuits of terminal TC, that is between the negative electrode of the diode Db1 of original reverse parallel connection and terminal TA insertion NMOS electric crystal Mn2.So, terminal TA to terminal TC and terminal TC be the circuit structure of two symmetries to terminal TA.Its mode of operation and operating principle are same as described above, just seldom do at this and give unnecessary details.In the framework of Fig. 8, for two electrostatic discharging paths from terminal TA to terminal TC and from terminal TC to terminal TA, all be to utilize parasitic silicon controlled rectifier structure that diode and electric crystal constitute with as electrostatic discharging path, and Fig. 5 is to utilize parasitic silicon controlled rectifier structure that diode and electric crystal constitute with as electrostatic discharging path by having from terminal TA to terminal TC only.
Seeing also shown in Figure 9ly, is the another kind of execution mode of the separate power supplies ESD protection circuit of Fig. 5.In Fig. 9, the NMOS electric crystal Mn1 among Fig. 5 is changed to PMOS electric crystal Mp1.Its mode of operation and operating principle are same as described above, just seldom do at this and give unnecessary details.The difference of Fig. 9 and Fig. 5 is produced by PMOS electric crystal Mp1.At this moment, to pick up doped region 130 to p type wells district 104, N type doped region 122,126 and the P type at Fig. 6 script NMOS electric crystal place, be replaced with N type wellblock, P type doped region and N type and pick up doped region, (anode of diode Da1, N type wellblock, the substrate of P type, N type wellblock (PMOS electric crystal) pick up doped region with the N type and make parasitic silicon controlled rectifier become P type doped region.
Seeing also shown in Figure 10ly, is the another kind of embodiment of ESD protection circuit of the present invention, and this embodiment is the variation example of Fig. 8.Also two NMOS electric crystal Mn1, Mn2 that are about among Fig. 8 change to PMOS electric crystal Mp1, Mp2, and in addition, mode of operation and principle are much at one.Certainly, two electrostatic discharging paths that constitute from terminal TA to terminal TC and from terminal TC to terminal TA, diode is done corresponding correction with the dopant profile outline of the parasitic silicon controlled rectifier structure that electric crystal is constituted.
Seeing also shown in Figure 11ly, is the another kind of embodiment of ESD protection circuit of the present invention, and this embodiment is the variation example of Fig. 8.In Fig. 8, two electrostatic discharging paths from terminal TA to terminal TC and from terminal TC to terminal TA are connected with a NMOS electric crystal by a diode and are constituted, and the structure of Figure 11 then is to be connected with a NMOS electric crystal and constituted by two diodes.It is the pressure reduction that causes being connected the power supply line on terminal TA and the terminal TC that this kind changes architecture concept.That is, according to the size (about 0.4V to 0.6V) of the cut-ff voltage of the magnitude of pressure differential that is connected the power supply line on terminal TA and the terminal TC and each diode, can freely adjust the serial connection number of diode.That is, if the magnitude of pressure differential of the power supply line on terminal TA and the terminal TC is about the fashionable of two diode cut-ff voltages, just can be connected in series two diodes, and become the circuit structure of Figure 11.In addition, mode of operation and principle much at one, so also omit the explanation of its operating principle at this.Seeing also shown in Figure 12ly, then is the variation example that illustrates Figure 11, and the place of its change is only for to change to PMOS electric crystal Mp1, Mp2 with NMOS electric crystal Mn1, Mn2, and remaining operation is then same as described above, seldom does at this and gives unnecessary details.Seeing also shown in Figure 13ly, then is the example of drawing a plurality of diodes of serial connection, the serial connection number with on terminal TA and the terminal TC the magnitude of pressure differential of power supply line decides.NMOS electric crystal shown in Figure 13 also can be replaced by the PMOS electric crystal.
Then, enumerate numerical example and illustrate ESD protection circuit of the present invention is applied in situation in the actual integrated circuit particularly have the integrated circuit structure of different electrical power supply line.
Seeing also shown in Figure 14ly, is first application examples of using separate power supplies ESD protection circuit of the present invention.Separate power supplies ESD protection circuit 210,212 of the present invention is to be configured between first internal circuit 202 and second internal circuit 204.Separate power supplies ESD protection circuit 210 is made of diode Da21, Db21 and NMOS electric crystal Mn21; separate power supplies ESD protection circuit 212 is made of diode Da11, Db11 and NMOS electric crystal Mn11, and both all are configured to structure as shown in Figure 5.
Aforesaid first internal circuit can for example be a digit circuit, and second internal circuit can for example be an analogous circuit.First internal circuit 202 is coupled in the first high power supply line VDD1 and the first low power supply line VSS1, the first low power supply line VSS1 is a low relatively voltage source, as earthed voltage etc., the first high power supply line VDD1 then is the voltage source that is relatively higher than the first low power supply line VSS1; In like manner, second internal circuit 204 is coupled in the second high power supply line VDD2 and the second low power supply line VSS2, and the first low power supply line VSS2 also is a low relatively voltage source.Separate power supplies ESD protection circuit 210 is configured between first high power supply line VDD1 (aforesaid TA end) and the second high power supply line VDD2 (aforesaid TC end), and separate power supplies ESD protection circuit 212 is configured between first low power supply line VSS1 (aforesaid TA end) and the second low power supply line VSS2 (aforesaid TC end).
Input pad (inputpad) 206 is couple to first internal circuit 202, and is connected to the anode of diode Dp1 and arrives the first high power supply line VDD1, and is connected to the negative electrode of diode Dn1 and arrives the first low power supply line VSS1.Input pad 208 is couple to second internal circuit 204, and is connected to the anode of diode Dp2 and arrives the second high power supply line VDD2, and is connected to the negative electrode of diode Dh2 and arrives the second low power supply line VSS2.In addition; the inverter that is made of PMOS electric crystal Mp1 and NMOS electric crystal Mn1 is connected between the TA end (the first high power supply line VDD1 and the first low power supply line VSS1) and first internal circuit 202 of separate power supplies ESD protection circuit 210,212, and the inverter that is made of PMOS electric crystal Mp2 and NMOS electric crystal Mn2 is connected between the TC end (the second high power supply line VDD2 and the second low power supply line VSS2) and second internal circuit 204 of separate power supplies ESD protection circuit 210,212.
In addition, between the first high power supply line VDD1 that connects first internal circuit 202 and the first low high power supply line VSS1, also dispose ESD protection circuit 214.In like manner, between the second high power supply line VDD2 that connects second internal circuit 204 and the second low high power supply line VSS2, also dispose ESD protection circuit 216.Dispose ESD protection circuit the 214, the 216th, offer the ESD protection circuit of the extremely low power supply line (VDD1 to VSS1, VDD2 to VSS2) of high power supply line in first internal circuit 202 and second internal circuit 204 respectively.
Generally speaking, the gate voltage position standard of control NMOS electric crystal Mn1 can reach different isolating powers.For example provide a high voltage at gate, can make the drain of NMOS electric crystal Mn1 is hundreds of to thousands of ohms to the equivalent resistance between source electrode.In addition, provide an electronegative potential when gate, then NMOS electric crystal Mn1 is a closed condition, almost can be equivalent for opening circuit between its source electrode and drain.Under normal operation, the noise on power supply line VDD1 or the VDD2 need be greater than a critical voltage, so that power supply line VDD1 and VDD2 coupling, otherwise noise will be isolated, and two power supply line VDD1 and VDD2 are isolated.And under the very high situation of noise, can increase the number of diodes of serial connection.Power supply line VSS1 and VSS2 also have similar situation under normal operation.
With separate power supplies ESD protection circuit 210 is example; under normal operation, diode Db21 provides the voltage isolation capabilities of a diode cut-ff voltage to the path of the first high power supply line VDD1 (TA end) at the second high power supply line VDD2 (TC end).If at the noise voltage of the second high power supply line VDD2 during less than the cut-ff voltage of diode Db21, just noise can not arrive the first high power supply line VDD1 via diode Db21.Otherwise, as at the noise voltage of the second high power supply line VDD2 during greater than the cut-ff voltage of diode Db21, just noise can arrive the first high power supply line VDD1 via diode Db21.In addition, under normal operation, diode Da21 also provides the voltage isolation capabilities of a diode cut-ff voltage, and NMOS electric crystal Mn21 then provides a hundreds of approximately extremely resistance of thousands of ohm on the path of the high power supply line VDD2 of the first high power supply line VDD1 to the second.The resistance that NMOS electric crystal Mn21 is carried under normal operation can reduce through the accurate position of the noise of NMOS electric crystal Mn21.
With separate power supplies ESD protection circuit 212 is example; under normal operation, diode Db11 hangs down the voltage isolation capabilities that a diode cut-ff voltage is provided on the path of power supply line VSS1 (TA end) at the second low power supply line VSS2 (TC end) to first.If at the noise voltage of the second low power supply line VSS2 during less than the cut-ff voltage of diode Db11, just noise can not arrive the first low power supply line VSS1 via diode Db11.Otherwise, as at the noise voltage of the first high power supply line VSS2 during greater than the cut-ff voltage of diode Db11, just noise can arrive the first low power supply line VSS1 via diode Db11.In addition, under normal operation, diode Da11 also provides the voltage isolation capabilities of a diode cut-ff voltage, and NMOS electric crystal Mn11 then provides a hundreds of approximately extremely resistance of thousands of ohm on the path of the low power supply line VSS2 of the first low power supply line VSS1 to the second.The resistance that NMOS electric crystal Mn11 is carried under normal operation can reduce through the accurate position of the noise of NMOS electric crystal Mn11.
Situation when electrostatic discharge event produces then is described.When a positive static discharge voltage is applied to input pad 206; and power supply line VSS2 is when being ground connection; the static discharge voltage that is applied to input pad 206 can make diode Dp1 and conducting; static discharge current can be from the first high power supply line VDD1 through ESD protection circuit 214; flow to the first low power supply line VSS1, flow to the second low power supply line VSS2 through separate power supplies ESD protection circuit 212 more afterwards.When static discharge voltage was delivered to the first low power supply line VSS1, at the beginning the time, the diode Da11 of separate power supplies ESD protection circuit 212 was a forward bias voltage drop, and NMOS electric crystal Mn11 is in conducting state.At this moment, the parasitic silicon controlled rectifier of diode Da11 and NMOS electric crystal Mn11 formation can be activated.So static discharge current along the path that parasitic silicon controlled rectifier provided, flows to the second low power supply line VSS2 by the first low power supply line VSS1.This mechanism can be with reference to the explanation of figure 7.Secondly, the static discharge voltage that is applied to input pad 206 can allow diode Dp1 forward bias voltage drop, makes static discharge voltage be passed to the first high power supply line VDD1.At this moment, the diode Da11 of separate power supplies ESD protection circuit 210 is a forward bias voltage drop, and NMOS electric crystal Mn11 is in conducting state.At this moment, the parasitic silicon controlled rectifier of diode Da21 and NMOS electric crystal Mn21 formation can be activated.So static discharge current along the path that parasitic silicon controlled rectifier provided, flows to the second low power supply line VDD2 by the first high power supply line VDD1.Afterwards, flow to the second low power supply line VSS2 from ESD protection circuit 216 again.When the static discharge voltage that is applied to input pad when negative, enclose with above-mentioned opposite in the path of its process.
In addition; when a positive static discharge voltage is applied to input pad 208; and power supply line VSS1 is when being ground connection; the static discharge voltage that at first is applied to input pad 208 can make diode Dp2 and conducting; static discharge current can flow to the second low power supply line VSS2 through ESD protection circuit 216 from the second high power supply line VDD2, flows to the first low power supply line VSS1 through separate power supplies ESD protection circuit 212 more afterwards.When static discharge voltage is delivered to the second low power supply line VSS2, can make diode Db11 forward bias voltage drop and conducting, static discharge current just flows to the first low power supply line VSS1 by the second low power supply line VSS2.Secondly; when static discharge voltage is delivered to the second high power supply line VDD2 through diode Dp2; can make the diode Db21 forward bias voltage drop of separate power supplies ESD protection circuit and conducting, static discharge current just flows to the first high power supply line VDD1 by the second high power supply line VDD2.Afterwards, flow to the first low power supply line VSS1 via ESD protection circuit 214 again.When the static discharge voltage that is applied to input pad when negative, enclose with above-mentioned opposite in the path of its process.
Seeing also shown in Figure 15ly, is the schematic diagram of using first application examples of separate power supplies ESD protection circuit of the present invention.The discrepancy of Figure 15 and Figure 14 is that the TC of separate power supplies ESD protection circuit 210,212 holds the diode Db11, the Db21 that hold to TA to insert NMOS electric crystal Mn22, Mn21 respectively again.Therefore, in operation, from TA hold to the discharge mechanism of TC end with outside Figure 14 is identical, it also is to hold to TC with TA to hold identical that TC holds to the discharge mechanism of TA end.In other words, all be that the thyristor framework that utilizes diode and electric crystal to constitute is reached between power supply line VDD1 and the VDD2 and between power supply line VSS1 and the VSS2.The operation of Figure 15 is identical with Figure 14 basically, so do not add to give unnecessary details at this.
Seeing also shown in Figure 16ly, is the first application examples schematic diagram of using separate power supplies ESD protection circuit of the present invention.The discrepancy of Figure 16 and Figure 14 is that NMOS electric crystal Mn22, the Mn21 of separate power supplies ESD protection circuit 210,212 are replaced by PMOS electric crystal Mp11, Mp21; therefore; mode basic and Figure 14 is similar in the operation, can be with reference to the explanation of figure 9, so do not add to give unnecessary details at this.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (20)
1, a kind of separate power supplies formula ESD protection circuit is coupled between one first power supply line and the second source supply line, it is characterized in that this separate power supplies formula ESD protection circuit comprises:
One first diode has an anode and a negative electrode, and wherein this anode is coupled to this first power supply line;
One first metal oxide semiconductor device has a gate, one source pole and a drain, and wherein this drain negative electrode and this source electrode of being coupled to this first diode is coupled to this second source supply line; And
One second diode has an anode and a negative electrode, and wherein this anode is coupled to this second source supply line, and this negative electrode is coupled to this first power supply line,
Wherein this first diode and this first metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that an electrostatic discharging path to be provided.
2, separate power supplies formula ESD protection circuit according to claim 1; it is characterized in that it more comprises one second metal oxide semiconductor device; it has a gate, one source pole and a drain; wherein this drain negative electrode and this source electrode of being coupled to this second diode is coupled to this first power supply line, makes this second diode and this second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier.
3, separate power supplies formula ESD protection circuit according to claim 1 is characterized in that wherein said first metal oxide semiconductor device is a N type metal oxide semiconductor element.
4, separate power supplies formula ESD protection circuit according to claim 1 is characterized in that wherein said first metal oxide semiconductor device is the P-type mos element.
5, separate power supplies formula ESD protection circuit according to claim 2, it is characterized in that wherein said first with this second metal oxide semiconductor device be N type metal oxide semiconductor element.
6, separate power supplies formula ESD protection circuit according to claim 2, it is characterized in that wherein said first with this second metal oxide semiconductor device be the P-type mos element.
7, a kind of separate power supplies formula ESD protection circuit is coupled between one first power supply line and the second source supply line, it is characterized in that this separate power supplies formula ESD protection circuit comprises:
A plurality of first diodes have an anode and a negative electrode respectively, the connection that is one another in series, and wherein this anode of first this first diode is coupled to this first power supply line;
One first metal oxide semiconductor device has a gate, one source pole and a drain, and wherein this drain negative electrode and this source electrode of being coupled to last this first diode is coupled to this second source supply line; And
A plurality of second diodes have an anode and a negative electrode respectively, the connection that is one another in series, and wherein this anode of first this second diode is coupled to this second source supply line, and this negative electrode of last this second diode is coupled to this first power supply line,
This first diode and this second metal oxide semiconductor device constitute the structure with parasitic silicon controlled rectifier, so that an electrostatic discharging path to be provided.
8, separate power supplies formula ESD protection circuit according to claim 7; it is characterized in that it more comprises one second metal oxide semiconductor device; have a gate, one source pole and a drain; wherein this drain this negative electrode and this source electrode of being coupled to last this second diode is coupled to this first power supply line; make this second diode and this second metal oxide semiconductor device constitute structure, so that an electrostatic discharging path to be provided with parasitic silicon controlled rectifier.
9, separate power supplies formula ESD protection circuit according to claim 7 is characterized in that wherein said first metal oxide semiconductor device is a N type metal oxide semiconductor element.
10, separate power supplies formula ESD protection circuit according to claim 7 is characterized in that wherein said first metal oxide semiconductor device is the P-type mos element.
11, separate power supplies formula ESD protection circuit according to claim 8, it is characterized in that wherein said first with this second metal oxide semiconductor device be N type metal oxide semiconductor element.
12, separate power supplies formula ESD protection circuit according to claim 8, it is characterized in that wherein said first with this second metal oxide semiconductor device be the P-type mos element.
13, a kind of integrated circuit; destroy in order to protect one first and one second internal circuit to avoid static discharge; this first internal circuit is coupled between one first high power supply line and the one first low power supply line; this second internal circuit is coupled between one second high power supply line and the one second low power supply line; wherein this first with this second high power supply line be isolated from each other and this first with this second low power supply line be to be isolated from each other, it is characterized in that this integrated circuit comprises:
One first ESD protection circuit is coupled between this first high power supply line and this first low power supply line;
One second ESD protection circuit is coupled between this second high power supply line and this second low power supply line;
One the 3rd ESD protection circuit, be coupled between this first high power supply line and this second high power supply line, when appearing at this first or second high power supply line when a static discharge, optionally connect this first high power supply line and this second high power supply line, wherein the 3rd ESD protection circuit comprises one first diode string and the one first metal-oxide semiconductor (MOS) electric crystal that is one another in series at least, and one second diode string, be connected in reverse parallel in this first diode string and this first metal-oxide semiconductor (MOS) electric crystal, wherein when this first diode string and this first metal-oxide semiconductor (MOS) electric crystal start because of the static discharge phenomenon, form a parasitic silicon controlled rectifier, so that a discharge path to be provided; And
One the 4th ESD protection circuit; be coupled in this first low power supply line and this second low power supply line; in order to appear at when a static discharge this first or during this second low power supply line; optionally connect between this first low power supply line and this second low power supply line; wherein the 4th ESD protection circuit comprises one the 3rd diode string and the one second metal-oxide semiconductor (MOS) electric crystal that is one another in series at least; and one the 4th diode string; be connected in reverse parallel in the 3rd diode string and this second metal-oxide semiconductor (MOS) electric crystal; wherein when the 3rd diode string and this second metal-oxide semiconductor (MOS) electric crystal start because of the static discharge phenomenon; form a parasitic silicon controlled rectifier, so that a discharge path to be provided.
14, integrated circuit according to claim 13, it is characterized in that wherein said first with this second metal-oxide semiconductor (MOS) electric crystal be one of N type or P type.
15, integrated circuit according to claim 13; first and second diode string that it is characterized in that wherein said the 3rd ESD protection circuit is at least a diode respectively, and the 3rd and the 4th diode string of the 4th ESD protection circuit is at least a diode respectively.
16, integrated circuit according to claim 15 is characterized in that the pressure reduction decision of the series connection number of wherein said first and second diode string by this first high power supply line and this second high power supply line.
17, integrated circuit according to claim 15 is characterized in that the wherein said the 3rd is determined by this first low power supply line pressure reduction with this second low power supply line with the number of connecting of the 4th diode string.
18; integrated circuit according to claim 13; it is characterized in that wherein said the 3rd ESD protection circuit more comprises one the 3rd metal-oxide semiconductor (MOS) electric crystal; connect with this second diode string; this first with the 3rd metal-oxide semiconductor (MOS) electric crystal be couple to respectively this second with this first high power supply line; and the 4th ESD protection circuit more comprises one the 4th metal-oxide semiconductor (MOS) electric crystal; connect with the 4th diode string, this second with the 4th metal-oxide semiconductor (MOS) electric crystal be couple to respectively this second with this first low power supply line.
19, integrated circuit according to claim 16, it is characterized in that wherein said first to the 4th metal-oxide semiconductor (MOS) electric crystal be N type or P type both one of.
20, integrated circuit according to claim 16 is characterized in that it more comprises:
One first input ESD protection circuit is coupled between an input weld pad, this first high power supply line and this first low power supply line of this first internal circuit, this first internal circuit; And
One second input ESD protection circuit is coupled between an input weld pad, this second high power supply line and this second low power supply line of this second internal circuit, this second internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410059497 CN1716594A (en) | 2004-06-28 | 2004-06-28 | Separate power source type static discharge protective circuit and integrated circuit using such circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410059497 CN1716594A (en) | 2004-06-28 | 2004-06-28 | Separate power source type static discharge protective circuit and integrated circuit using such circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1716594A true CN1716594A (en) | 2006-01-04 |
Family
ID=35822222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200410059497 Pending CN1716594A (en) | 2004-06-28 | 2004-06-28 | Separate power source type static discharge protective circuit and integrated circuit using such circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1716594A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109813976A (en) * | 2017-11-20 | 2019-05-28 | 上海普锐马电子有限公司 | A kind of hand-held electrostatic discharging generator |
| CN112909906A (en) * | 2021-01-27 | 2021-06-04 | 维沃移动通信有限公司 | Circuit and electronic device |
| CN109813976B (en) * | 2017-11-20 | 2024-05-10 | 上海普锐马电子有限公司 | Handheld electrostatic discharge generating device |
-
2004
- 2004-06-28 CN CN 200410059497 patent/CN1716594A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109813976A (en) * | 2017-11-20 | 2019-05-28 | 上海普锐马电子有限公司 | A kind of hand-held electrostatic discharging generator |
| CN109813976B (en) * | 2017-11-20 | 2024-05-10 | 上海普锐马电子有限公司 | Handheld electrostatic discharge generating device |
| CN112909906A (en) * | 2021-01-27 | 2021-06-04 | 维沃移动通信有限公司 | Circuit and electronic device |
| CN112909906B (en) * | 2021-01-27 | 2023-03-10 | 维沃移动通信有限公司 | Circuit and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN2805093Y (en) | Electrostatic discharging protection circuit | |
| CN1181548C (en) | Circuit for protection against static electricity, and semiconductor integrated circuit using same | |
| CN1212672C (en) | Electrostatic discharge protection element structure with high base trigger effect, and use circuit thereof | |
| CN1658388A (en) | Electrostatic discharge protection circuit | |
| CN1414678A (en) | Electrostatic discharge protective circuit using base trigger silicon rectifier | |
| CN1053067C (en) | Electrostatic discharge protection circuit for integrated circuit | |
| CN1203553C (en) | Low voltage triggered SCR containing Si in insulating layer and protecting circuit for electrostatic discharge | |
| TWI240404B (en) | Separated power ESD protection circuit and integrated circuit using the same | |
| CN1252820C (en) | Semiconductor integrated circuit device with body bias circuit | |
| CN101079418A (en) | Electrostatic discharge circuit and method for reducing input capacitance of semiconductor chip including same | |
| US20090290271A1 (en) | Multi-chip module package including external and internal electrostatic discharge protection circuits, and/or method of making the same | |
| CN1881582A (en) | Esd protection circuit and semiconductor structure | |
| CN1467844A (en) | Semiconductor integrated circuit device | |
| CN1362743A (en) | Semicondcutor integrated circuit | |
| CN1284237C (en) | Input protection circuit | |
| CN1870436A (en) | Signal alignment circuit, drawing down circuit and pulling up circuit | |
| CN1933154A (en) | Semicoductor circuit, inverter circuit, semiconductor apparatus | |
| CN1187833C (en) | Semiconductor memory | |
| CN1627520A (en) | Decoupling capacitors and semiconductor integrated circuit | |
| CN1855724A (en) | Buffer circuit | |
| TW201027711A (en) | Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer | |
| CN1209816C (en) | Antistatic assembly and antistatic circuit for electrostatic discharge protection assembly | |
| CN2743976Y (en) | Electrostatic discharging protection circuit | |
| CN1130020C (en) | Electrostatic protection circuit | |
| CN101211909B (en) | ESD protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |