CN1209816C

CN1209816C - Antistatic assembly and antistatic circuit for electrostatic discharge protection assembly

Info

Publication number: CN1209816C
Application number: CN 02104721
Authority: CN
Inventors: 柯明道; 张恒祥; 王文泰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2002-02-09
Filing date: 2002-02-09
Publication date: 2005-07-06
Anticipated expiration: 2022-02-09
Also published as: CN1437258A

Abstract

The present invention discloses an electrostatic discharge (ESD) protecting assembly with a deep well region and a related ESD protecting circuit. The ESD protecting assembly is coupled to a P-type substrate of a relatively low voltage source and comprises a side silicon controlled rectifier and a deep N-type well, and the side silicon controlled rectifier (SCR) comprises a P-type layer, an N-type layer, a first N-type well and a first P-type well, wherein the P-type layer is used as a positive electrode of the SCR, and the N-type is used as a negative layer of the SCR; the first N-type well is arranged between the P-type layer and the N-type layer and is adjacent to the P-type layer, the P-type layer well is adjacent to the N-type layer and the first N-type well, and the deep N-type well is arranged between the first P-type well and the P-type substrate to isolate the electric connection between the first P-type well and the P-type substrate. A plurality of ESD protecting assemblies of the present invention can be connected in series freely to increase the total hold voltage of the ESD protecting circuit and prevent bolt locking phenomena.

Description

A kind of electrostatic discharge protective assembly and electrostatic storage deflection (ESD) protection circuit

Technical field

The present invention relates to a kind of electrostatic discharge protective assembly and application circuit thereof, especially refer to a kind of static discharge (electrostatic discharge that is used for, ESD) thyristor (silicon controlled rectifier, SCR) assembly protection circuit, that have the deep-well region structure.

Background technology

ESD has been that reliability important in the semiconductor product one of is considered, particularly for CMOS (Complementary Metal Oxide Semiconductor) (complementary metal oxide semiconductor, the CMOS) technology of minification.Because MOS (metal-oxide-semiconductor) transistor (metal oxide semiconductor, the breakdown voltage of gate oxide MOS) is step-down along with the technological progress of manufacture process, therefore, the ESD protection circuit is set at each I/O port place and just becomes prevention ESD stress one of hurtful effective way of gate oxide.

Because the sustaining voltage V of SCR itself _HoldLow (being approximately about 1V) very, in esd event, the thermal power (I that SCR produced _ESD* V _Hold) will be than the ESD guard assembly of other kind, for example (bipolar junction transistor, BJT) etc., that comes is low for diode, MOS, bipolar junction transistor.So SCR can tolerate higher ESD stress under area identical.Also therefore, SCR is widely used in many ESD protection circuits.Generally in the CMOS manufacture process, SCR utilizes well region and heavily doped region to be formed at substrate surface, so be called horizontal SCR (LSCR) again.Fig. 1 (a) for traditional be the ESD protection circuit figure of main ESD guard assembly with a LSCR.Fig. 1 (b) is the generalized section of the LSCR among Fig. 1 (a).PNPN structure among the LSCR is formed by P+ doped region 10, N type trap 12, P type substrate 14 and N+ doped region 16.Fig. 1 (c) is the IV curve chart of Fig. 1 (b).The trigger voltage V of LSCR among Fig. 1 (b) _TriggerApproximate the breakdown voltage that PN between N type trap 12 and the P type substrate 14 connects face greatly, about 30 to 50 volts.This trigger voltage V _TriggerThe breakdown voltage that is higher than the gate oxide of NMOS and PMOS is so LSCR usually needs the assistance of a secondary ESD guard assembly (as, the MESD among Fig. 1 (a)) to reach complete ESD protective benefits.

The SCR that low-voltage triggers in order to make the more effective protection I/O port of SCR energy, also to develop in the prior art, be called for short LVTSCR.Fig. 2 (a) is the general use LVTSCR circuit diagram as the ESD guard assembly.Fig. 2 (b) is the generalized section of the LVTSCR among Fig. 2 (a) figure.Fig. 2 (c) is the IV curve chart of the LVTSCR among Fig. 2 (b).By Fig. 2 (c) as can be known, by assisting of NMOS, trigger voltage can be reduced to about 10 volts.

General traditional SCR or LVTSCR directly couples with the P type substrate 14 of ground connection (VSS) mutually, shown in Fig. 1 (b) and Fig. 2 (b).Therefore, can only be as exporting/go into joint sheet or VDD ESD protection circuit to VSS.And, also because the P type substrate 14 of common ground is arranged, so SCR (or LVTSCR) also can't be connected in series each other mutually.

(integratedcircuit IC), generally can add dark N type trap manufacture process in the manufacture process of CMOS, in order to the P type substrate of isolated ground connection and the P type trap of placing NMOS in order to produce simulation with high antinoise function or high-frequency integrated circuit.And, also often adding dark N type trap manufacturing process in the DRAM manufacture process with NMOS and peripheral circuit in the isolated memory array, the prevention noise effect that peripheral circuit produced is to the data that are stored in the memory array.Yet in case noise has triggered as SCR and LVTSCR among Fig. 1 (a) or Fig. 2 (a), the voltage that output is gone on the joint sheet will produce the bolt-lock phenomenon, and can't receive correct message.

Summary of the invention

Technical problem to be solved by this invention is to be the deep-well region structure of utilizing thyristor (SCR) assembly to have, and a kind of SCR structure that can be connected in series is provided.

Another main purpose of the present invention is to make the I/O port of integrated circuit not be subjected to The noise, can prevent the generation of bolt-lock phenomenon.

For realizing above-mentioned purpose, the present invention proposes a kind of ESD guard assembly, is located at one and is coupled in the P type substrate (substrate) in a low-potential voltage source.This ESD guard assembly includes a horizontal thyristor and a dark N type trap, this horizontal thyristor has a p type layer, a N type layer, one the one N type trap and one the one P type trap, this p type layer is as the anode of this SCR, this N type layer is as the negative electrode of this SCR, the one N type trap is located between this p type layer and this N type layer, be abutted to this p type layer, the one P type trap is abutted to this a N type layer and a N type trap, this dark N type trap is located between a P type trap and this P type substrate, in order to intercept the electrical connection of a P type trap to this P type substrate.

In order to realize above-mentioned purpose better, the invention allows for a kind of electrostatic storage deflection (ESD) protection circuit, be coupled between one first joint sheet and one second joint sheet., this electrostatic storage deflection (ESD) protection circuit includes an ESD guard assembly with a negative electrode and an anode, this ESD guard assembly is located at one and is coupled in the P type substrate in a low-potential voltage source, include a horizontal SCR and a dark N type trap, this horizontal SCR includes a p type layer, one N type layer, one the one N type trap and one the one P type trap, this p type layer is as the anode of this SCR, this N type layer is as the negative electrode of this SCR, the one N type trap is located between this p type layer and this N type layer, be abutted to this p type layer, the one P type trap is abutted to this a N type layer and a N type trap, this dark N type trap is located between a P type trap and this P type substrate, in order to intercept the electrical connection of a P type trap to this P type substrate, wherein, when an esd event took place, this anode and this negative electrode system were coupled to this first joint sheet and this second joint sheet respectively.

Described electrostatic discharge protective assembly wherein, has one the 2nd N type trap to be adjacent to this N type layer below, and this dark N type trap includes the first dark N type trap and one second dark N type trap separately, contacts a N type trap and the 2nd N type trap respectively.

The invention has the advantages that increase the one P type trap that this dark N type trap can be suitable to the equivalent resistance between this P type substrate, even through after the suitable design, can completely cut off being electrically connected between a P type trap and this P type substrate.Therefore, ESD guard assembly of the present invention can a plurality ofly be chained together, and to increase total sustaining voltage of whole ESD protection circuit, prevents the generation of bolt-lock incident.

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:

Description of drawings

Fig. 1 (a) for traditional be the ESD protection circuit figure of main ESD guard assembly with a LSCR;

Fig. 1 (b) is the generalized section of the LSCR among Fig. 1 (a);

Fig. 1 (c) is the IV curve chart of Fig. 1 (b);

Fig. 2 (a) is the general use LVTSCR circuit diagram as the ESD guard assembly;

Fig. 2 (b) is the generalized section of the LVTSCR among Fig. 2 (a);

Fig. 2 (c) is the IV curve chart of the LVTSCR among Fig. 2 (b);

Fig. 3 (a) and Fig. 3 (b) be two NSCR of the present invention generalized section with and conventional letter figure;

Fig. 4 (a) and Fig. 4 (b) be two PSCR of the present invention generalized section with and conventional letter figure;

Fig. 5 is the profile of another kind of NSCR of the present invention;

Fig. 6 is the profile of another kind of PSCR of the present invention;

Fig. 7 is a kind of VDD of application NSCR of the present invention and the ESD clamped circuit between the VSS;

Fig. 8 is a kind of embodiment of Fig. 7;

Fig. 9 is a kind of VDD of application PSCR of the present invention and the ESD clamped circuit between the VSS;

Figure 10 is a kind of embodiment of Fig. 9;

Figure 11 is in the SCR serial, mixes a kind of embodiment schematic diagram that uses NSCR of the present invention and PSCR;

Figure 12 and Figure 13 are the VDD that is connected in series with diode of two utilization NSCR of the present invention and the ESD clamped circuit between VSS;

Figure 14 and Figure 15 are the VDD that is connected in series with diode of two utilization PSCR of the present invention and the ESD clamped circuit between VSS;

Figure 16 is the present invention's NSCR and the schematic diagram that PNSCR is applied to an input;

Figure 17 is a kind of embodiment of Figure 16;

Figure 18 is applied to the schematic diagram of an output for NSCR of the present invention and PNSCR;

Figure 19 is a kind of embodiment of Figure 18;

Figure 20 is applied to the schematic diagram of an input for NSCR of the present invention and PSCR;

Figure 21 is applied to the schematic diagram of output for NSCR of the present invention and PSCR;

Figure 22 is the ESD protection circuit schematic diagram of a kind of utilization NSCR of the present invention (or PSCR) between the VDD (or VSS) that separates; And

Figure 23 is the ESD protection circuit schematic diagram of another kind of utilization NSCR of the present invention (or PSCR) between the VDD (or VSS) that separates.

Embodiment

First embodiment

In Fig. 3 (a), the generalized section of NSCR of the present invention with and conventional letter figure.NSCR represents the SCR that triggers with NMOS.NSCR among Fig. 3 (a) has three electrodes: anode (anode), negative electrode (cathode) and control grid (V_GN).PNPN structure among the NSCR is constituted with P type trap 38, N type trap 42, P type trap 40 and N+ doped region 46.P type trap 38 and P+ doped region 52 are as the anode of NSCR.Be isolated with dark N type trap 32 in the middle of the P type substrate 30 of P type trap 40 and ground connection.A NMOS is arranged in the P type trap 40.The drain electrode of NMOS is constituted to cross over the N+ doped region 44 that PN between P type trap 40 and the N type trap 42 connects face.The source electrode of NMOS is constituted with N+ doped region 46, and the while is as the negative electrode of NSCR.P type trap 40 is couple to negative electrode by P+ doped region 48.Dark N type trap sees through N type trap 34 and is connected to VDD, is placed between whole PNPN structure and the P type substrate 30.On the layout of reality, the N type trap 34 that is connected to VDD is around whole NSCR assembly.P type substrate 30 is connected to VSS by P type trap 36 and P+ doped region 54.Therefore, the main body of NSCR can be described as on the P type substrate 30 that electricity floats on ground connection.

When bestowing positive voltage of grid, NMOS will be unlocked and provide a firing current to enter in the P type trap 40, and by the mechanism of bolt-lock positive feedback, this firing current can trigger NSCR, make voltage difference between negative electrode and the anode maintain sustaining voltage (~ 1V).Current path after NSCR opens is shown in the dotted line among Fig. 3 (a).Because P type trap 40 is isolated with P type substrate 30, therefore, can not be distributed to P type substrate 30 by the firing current that NMOS provided.This is the difference place of NSCR of the present invention and traditional LVTSCR maximum.Because firing current is limited to be flowed into, flowed out from negative electrode by N+ doped region 44, therefore, is enough to effectively trigger NSCR, the opening speed of NSCR can be very fast.Especially when esd event, the opening speed of ESD guard assembly has often determined the ESD tolerance of IC.The ESD guard assembly is more early opened, and has represented the more release ESD electric current of morning, is enough to make the effect of ESD protection more complete.

Fig. 3 (b) and Fig. 3 (a) are similar, for the generalized section of another NSCR of the present invention with and conventional letter figure.Wherein, the P type trap 38 among Fig. 3 (a) replaces with N type trap, as the N type trap 42 among the 3rd (b) figure.Therefore, be located in the N type trap 42 as the P+ doped region 52 of anode.The PNPN structure of NSCR is constituted with P+ doped region 52, N type trap 42, P type trap 40 and N+ doped region 46 among Fig. 3 (b).

Second embodiment

Identical reason, the present invention also can be implemented on PSCR.Fig. 4 (a) be a PSCR of the present invention generalized section with and conventional letter figure.PSCR among Fig. 4 (a) has three electrodes: anode (anode), negative electrode (cathode) and control grid (VGP).PNPN structure among the PSCR is the same to be constituted with P type trap 38, N type trap 42, P type trap 40 and N+ doped region 46.P type trap 38 and P+ doped region 52 are as the anode of PSCR.Be isolated with dark N type trap 32 between the P type substrate 30 of P type trap 40 and ground connection.A PMOS is arranged in the N type trap 42.The source electrode of PMOS is constituted with the P+ doped region 52 that PN between the N type trap 42 connects face to cross over P type trap 38, and the while is as the anode of PSCR.The drain electrode of PMOS is constituted with the P+ doped region 56 that the PN that crosses between P type trap 40 and the N type trap 42 connects on the face.P type trap 40 sees through P+ doped region 48, is couple to negative electrode.Dark N type trap 32 is connected to VDD by N type trap 34, is placed between whole PNPN structure and the P type substrate 30.On the layout of reality, the N type trap 34 that is connected to VDD is around whole PSCR assembly.P type substrate 30 is connected to VSS by P type trap 36 and P+ doped region 54.Therefore, the main body of PSCR can be described as on the P type substrate 30 that electricity floats on ground connection.

When bestowing one of grid with respect to the negative voltage of source electrode, PMOS will be unlocked and provide P type trap 40 1 firing currents, and by the mechanism of bolt-lock positive feedback, this firing current can trigger PSCR, makes the voltage difference between negative electrode and the anode maintain sustaining voltage.Current path after PSCR opens is shown in the dotted line among Fig. 4 (a).Because P type trap 40 is isolated with P type substrate 30, therefore, can not be distributed to P type substrate 30 by the firing current that PMOS provided.This is the difference place of PSCR of the present invention and traditional LVTSCR maximum.Because firing current is limited to flow out from negative electrode, therefore, is enough to effectively trigger PSCR, the opening speed of PSCR can be very fast, has more ageing ESD safeguard function to provide.

Fig. 4 (b) and Fig. 4 (a) are similar, for the generalized section of another PSCR of the present invention with and conventional letter figure.Wherein, the P type trap 38 among Fig. 4 (a) replaces with N type trap, as the N type trap 42 among Fig. 4 (b).Therefore, be located in the N type trap 42 as the P+ doped region 52 of anode.The PNPN structure of PSCR is constituted with P+ doped region 52, N type trap 42, P type trap 40 and N+ doped region 46 among Fig. 4 (b).

The 3rd embodiment

NSCR of the present invention also can use another kind of structure to implement, as shown in Figure 5.Fig. 5 is the profile of another kind of NSCR of the present invention.NSCR in Fig. 5 has three electrodes: anode (anode), negative electrode (cathode) and control grid (VGN).PNPN structure among the NSCR is constituted with P+ doped region 52, N type trap 42, P type trap 40 and N type trap 60 (or N+ doped region 46).P+ doped region 52 is as the anode of NSCR.A NMOS is arranged in the P type trap 40.The drain electrode of NMOS is constituted to cross over the N+ doped region 44 that PN between P type trap 40 and the N type trap 42 connects face.The source electrode of NMOS is constituted with N+ doped region 46, and the while is as the negative electrode of NSCR.It is very close that dark

N type trap

3201 and 3202 is placed each other, to increase the equivalent resistance between P type trap 40 and the P type substrate 30.Dark N type trap 3201 is connected to N type trap 60, and dark N type trap 3202 is connected to N type trap 42.As long as VGN provides suitable voltage at the control grid,, can quicken the opening speed of NSCR by the restriction of dark

N type trap

3201 and 3202 pairs of activated currents.Dotted line among Fig. 5 is represented the release way of ESD electric current.

The 4th embodiment

Fig. 6 is the profile of another kind of PSCR of the present invention.PSCR in Fig. 6 has three electrodes: anode (anode), negative electrode (cathode) and control grid (VGP).PNPN structure among the PSCR is constituted with P+ doped region 52, N type trap 42, p type trap 40 and N type trap 60 (or N+ doped region 46).P+ doped region 52 is as the anode of NSCR.A PMOS is arranged in the N type trap 42.The drain electrode of PMOS is constituted to cross over the P+ doped region 56 that PN between P type trap 40 and the N type trap 42 connects face.The source electrode of PMOS is constituted with P+ doped region 52, and the while is as the anode of PSCR.N type trap 42 sees through N+ doped region 62 and is coupled to anode.It is very close that dark

N type trap

3201 and 3202 is placed each other, to increase the equivalent resistance between P type trap 40 and the P type substrate 30.Dark N type trap 3201 is connected to N type trap 60, and dark N type trap 3202 is connected to N type trap 42.As long as VGP provides suitable voltage at the control grid, see through the restriction of dark

N type trap

3201 and 3202 pairs of activated currents, can quicken the opening speed of PSCR.Dotted line among Fig. 6 is represented the release way of ESD electric current.

The 5th embodiment

Fig. 7 is a kind of VDD of application NSCR of the present invention and the ESD clamped circuit between the VSS.Forward Chuan Jie NSCR_1 ~ NSCR_n is connected to VDD power line and VSS power line.The control gate of all NSCR all links together, and is controlled by an ESD observation circuit 70.When the esd event cross-pressure was on VDD and VSS power line, ESD observation circuit 70 was monitored out the generation of esd event, and provided a high voltage to all control gates, and NSCR_1 ~ NSCR_n is opened, to discharge the ESD electric current.The purpose of many NSCR serial connections is generations of prevention bolt-lock problem.Forward Chuan Jie NSCR can be considered as a special SCR, its total sustaining voltage V _{Hold_total}Value equal the summation that all forward are connected in series the sustaining voltage of indivedual NSCR.That is to say, as long as V _{Hold_total}VDD during greater than normal running and the voltage difference between the VSS even if noise has caused this special SCR to open, can not produce the bolt-lock phenomenon yet.If each NSCR is the same, avoid the condition that the bolt-lock phenomenon takes place to be

n＞(VDD-VSS)/V _hold-NSCR；

Wherein, n is the serial connection number of NSCR, V _{Hold_NSCR}Sustaining voltage for each NSCR.

In Fig. 8 and Fig. 7, a kind of embodiment of the present invention, ESD observation circuit 70 with the resistance R of a serial connection and capacitor C as a monitor.The CMOS reverser is as a driver.When normal running, monitor is output as high voltage, the CMOS reverser then output LOW voltage to close the NMOS among all NSCR.NSCR is closed condition.When esd event took place, because the RC late effect, the output meeting of monitor temporarily was a low-voltage.So the CMOS reverser provides power supply by VDD, output HIGH voltage is opened the NMOS of all NSCR.NSCR is an opening, can discharge the ESD electric current.In order to distinguish normal running and esd event, the time constant of resistance R and capacitor C is approximately 0.1 ~ 1 microsecond.

The 6th embodiment

The same ESD clamped circuit that also can be applied between VDD and the VSS of PSCR of the present invention, as shown in Figure 9.Forward Chuan Jie PSCR_1 ~ PSCR_n is connected to VDD power line and VSS power line.The control gate of all PSCR all links together, and is controlled by an ESD observation circuit 74.When the esd event cross-pressure was on VDD and VSS power line, ESD observation circuit 74 was monitored out the generation of esd event, and provided a low-voltage to all control gates, and PSCR_1 ~ PSCR_n is opened, to discharge the ESD electric current.When normal running, ESD observation circuit 74 is output as high voltage, closes the PMOS among all PSCR, and PSCR is closed condition.

In Figure 10 and Fig. 9, a kind of embodiment of the present invention.ESD observation circuit 74 with the resistance R of a serial connection and capacitor C as a monitor.The CMOS reverser of two series connection is as a driver.When normal running, monitor is output as high voltage, and then output HIGH voltage is to close the PMOS among all PSCR for driver, and PSCR is closed condition.When esd event took place, because the RC late effect, the output meeting of monitor temporarily was a low-voltage.So driver provides power supply by VSS, output LOW voltage is opened the PMOS of all PSCR.PSCR is an opening, can discharge the ESD electric current.In order to distinguish normal running and esd event, the time constant of resistance R and capacitor C is approximately 0.1 ~ 1 microsecond.

The 7th embodiment

In Figure 11, in the SCR serial, mix a kind of embodiment schematic diagram that uses NSCR and PSCR.When normal power operation, ESD observation circuit 76 provides low-voltage to give control gate among all NSCR, and provides high voltage to give control gate among all PSCR.When the esd event cross-pressure was between VDD and VSS, ESD observation circuit 76 provided high voltage to give control gate among all NSCR opening NMOS, and provided low-voltage to give control gate among all PSCR to open PMOS.

The 8th embodiment

NSCR of the present invention can be connected with the diode serial to form the ESD clamped circuit between a VDD and the VSS, the same problem that also can prevent bolt-lock.Figure 12 and Figure 13 be two embodiment of idea for this reason.The purpose that is connected in series with diode is to improve the sustaining voltage V of whole ESD protection circuit _HoldNSCR of the present invention can be inserted in any one position in the diode serial, for example, and in the position (as Figure 12) of the most close VDD, or the position (Figure 13) of the most close VSS, or even middle any position (not shown).When esd event took place, ESD observation circuit 70 can provide a high voltage, with the NMOS among the unlatching NSCR, and triggered NSCR.

The 9th embodiment

PSCR of the present invention can be connected with the diode serial to form the ESD clamped circuit between a VDD and the VSS, the same problem that also can prevent bolt-lock.Figure 14 and Figure 15 be two implementation columns of idea for this reason.The purpose that is connected in series with diode is to improve the sustaining voltage V of whole ESD protection circuit _HoldPSCR of the present invention can be inserted in any one position in the diode serial, for example, and in the position (Figure 14) of the most close VDD, or the position (Figure 15) of the most close VSS, or even middle any position (not shown).When esd event took place, ESD observation circuit 72 can provide a low-voltage, with the PMOS among the unlatching PSCR, and triggered PSCR.

The tenth embodiment

Figure 16 is applied to the schematic diagram of an input for NSCR of the present invention and PSCR.Figure 17 is a kind of embodiment of Figure 16.Wherein, be provided with the PSCR_1 ~ PSCR_n that forward be connected in series between input joint sheet 84 and the VDD, import between joint sheet 84 and the VSS and be provided with the NSCR_1 ~ NSCR_n that forward is connected in series.All control gates all are subjected to 80 controls of ESD observation circuit among PSCR1_1 ~ PSCR_n, and all control gates all are subjected to 82 controls of ESD observation circuit among NSCR_1 ~ NSCR_n.RC among ESD observation circuit 80 or 82 couples the generation of circuit in order to the monitoring esd event.When a positive esd pulse with respect to VSS impacted in input joint sheet 84, ESD observation circuit 82 was opened all NMOS among NSCR_1 ~ NSCR_n, to trigger NSCR_1 ~ NSCR_n and to discharge the ESD electric current.Identical reason, when a negative esd pulse with respect to VDD impacted in input joint sheet 84, ESD observation circuit 80 was opened all PMOS among PSCR_1 ~ PSCR_n, to trigger PSCR_1 ~ PSCR_n and to discharge the ESD electric current.The number n of serial connection as before described, depends on, when general power operation, and the maximum voltage difference between input joint sheet 84 and the VDD, or the maximum voltage difference between input joint sheet 84 and the VSS.

The 11 embodiment

Figure 18 is applied to the schematic diagram of an output for NSCR of the present invention and PNSCR.Figure 19 is a kind of embodiment of Figure 18.Output joint sheet 86 is driven by output buffer 85.Be provided with the PSCR_1 ~ PSCR_n that forward be connected in series between output joint sheet 86 and the VDD, import between joint sheet 86 and the VSS and be provided with the NSCR_1 ~ NSCR_n that forward is connected in series.All control gates all are subjected to 80 controls of ESD observation circuit among PSCR_1 ~ PSCR_n, and all control gates all are subjected to 82 controls of ESD observation circuit among NSCR_1 ~ NSCR_n.

The 11 embodiment

NSCR of the present invention and PSCR can be connected with the diode serial to form one and be applied to export/the ESD protection circuit of inbound port.Figure 20 is applied to the schematic diagram of input for NSCR of the present invention and PSCR.Figure 21 is applied to the schematic diagram of output for NSCR of the present invention and PSCR.NSCR_1 is connected in series mutually with a plurality of diode Dn_2 ~ Dn_k, and PSCR_1 is connected in series mutually with a plurality of diode Dp_2 ~ Dp_k.NSCR all is not defined as independent one with the number of the diode that is connected in series mutually, but decides on the demand of sustaining voltage.Identical, PSCR is not defined as independent one with the number of the diode that is connected in series mutually yet.

The 12 embodiment

NSCR of the present invention and PSCR can be applied to the ESD protection circuit between the separate power source line.The separate power source line generally is that the noise that produces for fear of a circuit group sees through power line and disturbed another circuit group.Yet the separate power source line has also caused the ESD infringement of not expecting simultaneously easily.Therefore, also must install the ESD protection circuit additional between the separate power source line.Figure 22 is the ESD protection circuit schematic diagram of a kind of utilization NSCR of the present invention (or PSCR) between the VDD (or VSS) that separates.Two bi-directional ESD protection circuits 90 and 92 are located at respectively between VDDH and the VDDL, and between VSSH and the VSSL.PSCR_1 and diode Dp_2 ~ Dp_k forward are serially connected with between VDDH and the VDDL each other.When a VDDH is the esd event of positive pulse when taking place to VDDL, ESD observation circuit 94 provides PMOS among a relative negative voltage and the PSCR_1 with triggering PSCR_1.ESD protection when diode Dp_a is the esd event of negative pulse as VDDH to VDDL.NSCR_1 and diode Dn_2 ~ Dn_k forward are serially connected with between VSSH and the VSSL each other.When a VSSH is the esd event of positive pulse when taking place to VSSL, ESD observation circuit 96 provides NMOS among a relative positive voltage and the NSCR_1 with triggering NSCR_1.ESD protection when diode Dn_a is the esd event of negative pulse as VSSH to VSSL.And the number of diode as before described, can determine the sustaining voltage of bi-directional ESD protection circuit 90 and 92, depends on the size of the noise feasible value between the power line.

The 13 embodiment

Figure 23 is the ESD protection circuit schematic diagram of another kind of utilization NSCR of the present invention (or PSCR) between the VDD (or VSS) that separates.Two two-way ESD protection circuits 90 and 92 are located at respectively between VDDH and the VDDL, and between VSSH and the VSSL.PSCR_1, PSCR_3 and diode Dp_2, Dp_4 ... Deng forward being serially connected with between VDDH and the VDDL each other.When a VDDH was the esd event generation of positive pulse to VDDL, ESD observation circuit 94 provided a relative negative voltage to trigger PSCR_1 and PSCR_3.ESD protection when diode Dp_a is the esd event of negative pulse as VDDH to VDDL.NSCR_1, NSCR_3 and diode Dn_2, Dn_4 ... Deng forward being serially connected with between VSSH and the VSSL each other.When a VSSH was the esd event generation of positive pulse to VSSL, ESD observation circuit 96 provided a relative positive voltage to trigger NSCR_1 and NSCR_3.ESD protection when diode DN_a is the esd event of negative pulse as VSSH to VSSL.And the number of the number of diode and NSCR (or PSCR) can determine the sustaining voltage of bi-directional ESD protection circuit 90 and 92.If need higher isolation of noise effect between VDDL and the VDDH, then the number of the PSCR in the ESD the protection circuit 90 or number of diode will increase.Identical reason also is applicable to ESD protection circuit 92.

Than existing NSCR or PSCR, P type trap wherein all directly is coupled to the P type substrate of ground connection, P type trap among NSCR of the present invention or the PSCR has utilized the dark N type trap that is produced in the manufacture process to increase P type trap to the resistance between the substrate of P type, or even has completely cut off P type trap to the electric connection between the substrate of P type.Therefore, NSCR of the present invention and PSCR can use a plurality of forward modes of polyphone, improve the sustaining voltage of ESD protection circuit, reach the generation of avoiding the bolt-lock phenomenon.And, no matter be that output is gone into end to power line, or the ESD protection circuit between the power line, all can use NSCR of the present invention or PSCR.

Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is that the claimed scope of claims is as the criterion.

Claims

1. electrostatic discharge protective assembly is located at a P type substrate that is coupled to a low-potential voltage source, it is characterized in that: include:

One horizontal thyristor SCR, it includes:

One p type layer is as the anode of this SCR;

One N type layer is as the negative electrode of this SCR;

One the one N type trap is located between this p type layer and this N type layer, is abutted to this p type layer; And

One the one P type trap is abutted to this a N type layer and a N type trap; And

One dark N type trap is located between a P type trap and this P type substrate, in order to the electrical connection of an isolated P type trap to this P type substrate.

2. electrostatic discharge protective assembly as claimed in claim 1 is characterized in that: this N type layer is constituted with one the one a N type doped region of being located in the P type trap.

3. electrostatic discharge protective assembly as claimed in claim 1 is characterized in that: a P type trap is to be coupled to this negative electrode.

4. electrostatic discharge protective assembly as claimed in claim 1 is characterized in that: this dark N type trap is and decides bias voltage N type trap and be connected, is coupled to a high-potential voltage source.

5. electrostatic discharge protective assembly as claimed in claim 4 is characterized in that: this decides bias voltage N type trap, this dark N type trap and a N type trap is electrically to have completely cut off a P type trap and this P type substrate.

6. electrostatic discharge protective assembly as claimed in claim 4 is characterized in that: this decides bias voltage N type trap, this dark N type trap and a N type trap is electrically to have completely cut off this P type layer and this P type substrate.

7. electrostatic discharge protective assembly as claimed in claim 4 is characterized in that: this N type trap of deciding bias voltage is around this horizontal SCR.

8. electrostatic discharge protective assembly as claimed in claim 1 is characterized in that: this horizontal SCR is a N type.

9. electrostatic discharge protective assembly as claimed in claim 1 is characterized in that: this horizontal SCR is a P type SCR.

10. electrostatic discharge protective assembly according to claim 1, it is characterized in that: have one the 2nd N type trap to be adjacent to this N type layer below, this dark N type trap includes the first dark N type trap and one second dark N type trap separately, contacts a N type trap and the 2nd N type trap respectively.

11. electrostatic discharge protective assembly according to claim 1, it is characterized in that: this p type layer is to be located in the N type trap.

12. an electrostatic storage deflection (ESD) protection circuit is coupled between one first joint sheet and one second joint sheet, it is characterized in that: include:

One electrostatic discharge protective assembly has an anode and a negative electrode, is located at one and is coupled in the P type substrate in a low-potential voltage source, includes:

One horizontal SCR, it includes:

One p type layer is as the anode of this SCR;

One N type layer is as the negative electrode of this SCR;

One dark N type trap is located between a P type trap and this P type substrate, in order to the electrical connection of an isolated P type trap to this P type substrate;

Wherein, when a static discharge took place, this anode and this negative electrode were coupled to this first joint sheet and this second joint sheet respectively.

13. the electrostatic storage deflection (ESD) protection circuit as claim 12 is characterized in that: this electrostatic storage deflection (ESD) protection circuit includes a diode in addition, be coupled between one first joint sheet and one second joint sheet, and forward with this horizontal SCR polyphone.

14. electrostatic storage deflection (ESD) protection circuit as claim 12, it is characterized in that: this horizontal SCR is a NSCR, and this electrostatic storage deflection (ESD) protection circuit includes a static discharge observation circuit in addition, when a static discharge takes place, in order to the control grid that provides an activation voltage to give this NSCR, to trigger this NSCR.

15. electrostatic storage deflection (ESD) protection circuit as claim 12, it is characterized in that: this horizontal SCR is a PSCR, and this electrostatic storage deflection (ESD) protection circuit includes a static discharge observation circuit in addition, when a static discharge takes place, in order to the control grid that provides an activation voltage to give this PSCR, to trigger this PSCR.

16. the electrostatic storage deflection (ESD) protection circuit as claim 14 or 15 is characterized in that: this static discharge observation circuit includes a RC circuit, in order to monitor the generation of this static discharge.

17. the electrostatic storage deflection (ESD) protection circuit as claim 12 is characterized in that: this first joint sheet is as the power supply input in a high-potential voltage source, and this second joint sheet is the power supply input as this low-potential voltage source.

18. the electrostatic storage deflection (ESD) protection circuit as claim 12 is characterized in that: this first joint sheet is as the power supply input in a high-potential voltage source, and this second joint sheet is as output or input joint sheet.

19. the electrostatic storage deflection (ESD) protection circuit as claim 12 is characterized in that: this first joint sheet is as output or input joint sheet, and this second joint sheet is as the power supply input in this low-potential voltage source.

20. the electrostatic storage deflection (ESD) protection circuit as claim 12 is characterized in that: this first joint sheet is as the power supply input of one first voltage source, and this second joint sheet is as the power supply input of one second voltage source.

21. electrostatic storage deflection (ESD) protection circuit as claim 12, it is characterized in that: this electrostatic storage deflection (ESD) protection circuit includes a reverse electrostatic discharge protective assembly in addition, this reverse electrostatic discharge protective assembly has an anode and is coupled to this second joint sheet, and a negative electrode is coupled to this first joint sheet.

22. the electrostatic storage deflection (ESD) protection circuit as claim 12 is characterized in that: this electrostatic storage deflection (ESD) protection circuit includes a plurality of forward horizontal SCR of series connection, is coupled between this first joint sheet and this second joint sheet.

23. electrostatic storage deflection (ESD) protection circuit as claimed in claim 22, it is characterized in that: these a plurality of horizontal SCR have a plurality of corresponding sustaining voltages, and the summation of these a plurality of sustaining voltages is poor greater than the maximum normal both end voltage of one between this first joint sheet and this second joint sheet.

24. electrostatic storage deflection (ESD) protection circuit as claimed in claim 23 is characterized in that: this first joint sheet and this second joint sheet are power line, and the normal both end voltage difference of this maximum is the voltage difference between this power line.