For overcoming the shortcoming of above-mentioned prior art, the purpose of this invention is to provide a kind of electrostatic storage deflection (ESD) protection circuit, the output/input circuit that it utilizes the high low-voltage of matrix triggering technique to hold altogether carries out electrostatic discharge protective, thereby improves the electro-static discharge protective ability of the output/input circuit that high low-voltage holds altogether.
Electrostatic storage deflection (ESD) protection circuit of the present invention, the output/input circuit that utilizes the matrix triggering technique that high low-voltage is held altogether carries out electrostatic discharge protective.This electrostatic storage deflection (ESD) protection circuit comprises: the stacked type nmos pass transistor, have first nmos pass transistor and second nmos pass transistor that pile up, the drain electrode of this first nmos pass transistor is connected in the I/O contact, and the grid of this first nmos pass transistor is connected in one first operating voltage, the source electrode of this first nmos pass transistor is connected in the drain electrode of this bi-NMOS transistor, and the grid of this second nmos pass transistor is connected in an internal circuit, and the source electrode of this second nmos pass transistor is connected in one second operating voltage; The side two-carrier transistor of one parasitism, the transistorized collection utmost point of this side two-carrier is connected in the drain electrode of first nmos pass transistor, and emitter-base bandgap grading is connected in the source electrode of second nmos pass transistor; One trigger current produces circuit, first end is connected in the I/O contact, and second end is connected in second operating voltage, and the 3rd end is connected in the transistorized base stage of side two-carrier, when being higher than a set point, send a trigger current from the 3rd end so as to voltage at the I/O contact; And the substrate resistance of a parasitism, an end is connected in the transistorized base stage of two-carrier, and the other end is connected in second operating voltage, gives the two-carrier transistor so as to utilizing trigger current to produce a bias voltage.
The output/input circuit that the present invention adopts the matrix triggering technique that high low-voltage is held altogether carries out electrostatic discharge protective, the NMOS element of stack is difficult for because of static discharge burns, thereby improves the electro-static discharge protective ability of the output/input circuit that high low-voltage holds altogether greatly.
Be accompanying drawing of the present invention below:
Fig. 1 is the electrostatic storage deflection (ESD) protection circuit of prior art;
Fig. 2 is the profile of the electrostatic storage deflection (ESD) protection circuit of prior art;
Fig. 3 is the transistor drain of Fig. 1 and the graph of a relation of source voltage and drain current;
Fig. 4 is first embodiment of electrostatic storage deflection (ESD) protection circuit of the present invention;
Fig. 5 show the present invention be applied to mixed type voltage esd protection circuit have a profile that trigger current produces the stacked NMOS transistors structure of circuit;
Fig. 6 shows the number of diodes of SPICE simulation and the graph of a relation of trigger current;
Fig. 7 shows the transistorized width of PMOS of SPICE simulation and the graph of a relation of trigger current;
Fig. 8 is second embodiment of electrostatic storage deflection (ESD) protection circuit of the present invention;
Fig. 9 shows the kenel of 4 kinds of static discharges;
Figure 10 is for using the circuit of electrostatic storage deflection (ESD) protection circuit of the present invention.
Component symbol parameter declaration among the figure:
10 electrostatic storage deflection (ESD) protection circuit 11I/O contacts
12 internal circuits 13 promote the PMOS transistor
20 stacked NMOS transistors, 21 upside nmos pass transistors
22 downside nmos pass transistors, 30 side two-carrier transistors
40 trigger currents produce circuit 50 parasitic substrate resistance
Describe the present invention in detail below with reference to accompanying drawing:
Fig. 4 is first embodiment of electrostatic storage deflection (ESD) protection circuit of the present invention.As shown in the drawing, electrostatic storage deflection (ESD) protection circuit 10 of the present invention is to comprise a stack of nmos pass transistor 20, a side two-carrier transistor 30, a parasitic substrate resistance R sub and a trigger current to produce circuit 40.This nmos pass transistor that piles up 20 can be with the voltage embedding of I/O contact in the predeterminated voltage scope, and trigger current to produce circuit 40 be to be used for producing trigger current Itrig.When trigger current Itrig surpasses a critical electric current value, via the pressure drop that parasitic substrate resistance R sub is produced, trigger side two-carrier transistor 30 ahead of time, so as to getting rid of the electric current of static discharge, to promote the ESD pressure withstanding degree of this protective circuit.
This nmos pass transistor that piles up 20 comprises upside nmos pass transistor 21 and downside nmos pass transistor 22.The drain electrode of last side transistor 21 (drain) is connected to an I/O contact (pad) 11, and grid (gate) is connected to the first operating voltage Vdd.The drain electrode of following side transistor 22 is connected to the source electrode (source) of side transistor 21, and grid is connected to internal circuit 12, and source electrode is connected to the second operating voltage Vss, that is ground connection.Note that the source electrode of last side transistor 21 also forms shared diffusion zone (shared difffusion) with the drain electrode of following side transistor 22.And the grid system of following side transistor 22 is connected in internal circuit 12, but not is connected to the second operating voltage Vss.
The collection utmost point of two-carrier transistor 30 (collector electrode) is connected in the drain electrode of side transistor 21, that is is connected in I/O contact 11.And the emitter-base bandgap grading of two-carrier transistor 30 (emitter electrode) is connected in down the source electrode of side transistor 22, that is is connected in the second operating voltage Vss.Parasitic substrate resistance R sub is connected between the base stage (bas electrode) and the second operating voltage Vss of two-carrier transistor 30.Therefore, as trigger current Itrig during greater than a critical value during Ith, that is during greater than the base stage of two-carrier transistor 30-emitter junction forward bias voltage drop, this two-carrier transistor 30 can conductings, so as to being guided to second from I/O contact 11, static discharge current makes voltage Vss, that is ground connection.
Trigger current produces circuit 40 and is used for producing trigger current Itrig.As shown in Figure 4, trigger current produce circuit 40 comprise a tandem diode D1, D2 ..., Dm, a PMOS transistor 42, a nmos pass transistor 43 and a resistance R d.Tandem diode D1, D2 ..., the anode of Dm is connected to I/O contact 11, and negative terminal is connected to the first electric current utmost point (first current electrode) of PMOS transistor 42.The drain electrode of nmos pass transistor 43 is connected to the second electric current utmost point of PMOS transistor 42, and source electrode is connected to the second operating voltage Vss.PMOS transistor 42 is connected to the first operating voltage Vdd with the grid (gate electrode) of nmos pass transistor 43 through resistance R d.Trigger current Itrig promptly from I/O connect 11 through tandem diode D1, D2 ..., Dm, the 42 back outputs of PMOS transistor.The effect of nmos pass transistor 43 is to avoid under the operate as normal situation, big leakage current triggering two-carrier transistor 30 is arranged and make its conducting (turnon).Resistance R d can use the n+ diffusion resistance of the diode with parasitism (parasitic) p-sub/n+.The diode of this parasitism (parasitic) p-sub/n+ can be used as antenna diodes (antennadiode), so as to solving the antenna effect (antenna effect) when the manufacture process.
Under normal situation, the ESD circuit is the state that remains on not conducting, therefore can not influence the voltage quasi position of (interfere) I/O contact 11.When I/O contact 11 during as input buffer (inputbuffer), the Das Vorderradfahrwerkmit Vorderradantrieb of internal circuit 12 (not shown) can output logic 0 to the grid of side transistor 22 down, therefore not having leakage current flows through the nmos pass transistor 20 that piles up.Stride across tandem diode D1, D2 ..., the voltage Vstring of Dm can formula (1) expression:
Wherein, m is that number, the n of diode are that desirable factors and β are the beta gain of parasitic-PNP transistor.
As the voltage Vpad of I/O contact 11 during greater than Vstring+|Vtp|+Vdd, trigger current produces circuit 40 promptly can produce trigger current Itrig.This trigger current produce circuit 40 can according to the required leakage current under working temperature adjust tandem diode D1, D2 ..., the length of Dm, and the voltage of trigger current generation circuit 40 actions, to keep the state of ESD circuit not conducting under the operate as normal situation.
When the situation of ESD takes place, owing to the de-coupling electric capacity of the first operating voltage Vdd makes the grid of PMOS transistor 42 be similar to ground connection near the second operating voltage Vss.So when Vpad 〉=Vstring+|Vtp|, trigger current produces circuit 40 conductings, and electric current can flow through tandem diode D1, D2 ..., Dm and PMOS transistor 42 be to substrate (substrate).Therefore, a suitable parasitic substrate resistance R sub makes the pressure drop Vsub of this parasitic substrate resistance R sub greater than 0.6V, makes 30 conductings of two-carrier transistor.Fig. 5 shows that the present invention is applied to the profile that trigger current produces the stacked NMOS transistors structure of circuit that has of esd protection circuit that high low-voltage holds altogether.
Fig. 6 shows the number of diodes of SPICE simulation and the relation of trigger current Itrig, and wherein the voltage of I/O contact 11 is 10ns in the rise time of 0V to 8V, with simulation ESD situation (breakdown voltage of stacked NMOS transistors 20 is approximately near 10V).Can recognize the relation that the number of diode and trigger current Itrig are inversely proportional to from this figure.Fig. 7 shows the width of PMOS transistor 42 of SPICE simulation and the relation of trigger current Itrig, wherein the number of diode be 5 and the length of PMOS transistor 42 be 3 μ m.Can recognize the relation that the width of PMOS transistor 42 is directly proportional with trigger current Itrig from this figure.Can adjust the width of number of diodes and PMOS transistor 42 according to Fig. 6,7 SPICE analog result, so that under the ESD situation, before stacked NMOS transistors 20 is not collapsed as yet, there are enough electric current I trig to trigger parasitic side two-carrier transistor 30 early.
Fig. 8 shows second embodiment of electrostatic storage deflection (ESD) protection circuit of the present invention.As shown in the drawing, the structure of electrostatic storage deflection (ESD) protection circuit 10 ' is identical with the electrostatic storage deflection (ESD) protection circuit 10 of first embodiment, unique difference be tandem diode D1, D2 ..., the anode of Dm is connected in a n-well (n-well) that promotes the suspension joint (floating) of PMOS transistor 13, and this PMOS transistor 13 is the some of output buffer.Under the ESD situation, parasitic p+/n-well diode and trigger current generation circuit 40 that electric current flows through PMOS transistor 13 at first come quick conducting to be contained in the parasitic side two-carrier transistor 30 of stacked NMOS transistors 20 so as to producing trigger current Itrig, and the ESD electric current is got rid of (Shunt).The purpose of second embodiment provides an embedding system structure can not produce extra input capacitance to guarantee I/O contact 11.This structure is even more important for the analogy integrated circuit.
Fig. 9 shows the kenel of four kinds of static discharges.As shown in the drawing, owing under ESD test, can produce positive voltage or negative voltage with respect to the first operating voltage Vdd and the second operating voltage Vss for I/O contact 11, so have the kenel of four kinds of static discharges.Under these ESD kenels, ESD voltage can be with respect to the first operating voltage Vdd and the second operating voltage Vss and is poured into I/O contact 11, but other contact is a floating.So esd protection circuit must be with ESD current bypass (bypass) to the first operating voltage Vdd and the second operating voltage Vss.Below with reference to Figure 10 the working method of circuit of the present invention in the kenel of four kinds of static discharges is described respectively down:
1. produce the positive voltage input with respect to the second operating voltage Vss.Under this kenel, high input voltage can make trigger current produce the also esd protection circuit of conducting stacked NMOS transistors of circuit 40 actions, and with most ESD current bypass to the second operating voltage Vss.
2. produce the positive voltage input with respect to the first operating voltage Vdd.Under this kenel, high defeated A voltage can make trigger current produce the also esd protection circuit of conducting stacked NMOS transistors of circuit 40 actions, and with most ESD current bypass to the second operating voltage Vss.Simultaneously, increase, force parasitic diode Dw conducting because second operating voltage is made the voltage of Vss, and with ESD current bypass to the first operating voltage Vdd.And parasitic diode Dw is formed by P type substrate and n-well.
3. produce the negative voltage input with respect to the second operating voltage Vss.Under this kenel, high negative input voltage can make parasitic diode Dn conducting, and with ESD current bypass to the second operating voltage Vss.And parasitic diode Dn is formed by P type substrate and n+ zone.
4. produce the negative voltage input with respect to the first operating voltage Vdd.Under this kenel, high negative input voltage can make parasitic diode Dn conducting, and with the ESD electric current via parasitic diode Dn and Rail embedding system circuit bypass to the first operating voltage Vdd.
So electrostatic storage deflection (ESD) protection circuit of the present invention can effectively reach the effect of electrostatic discharge protective.
Though more than with embodiment the present invention is described, therefore do not limit scope of the present invention, only otherwise break away from main idea of the present invention, these those skilled in the art can carry out various distortion or change.