CN100382313C

CN100382313C - Electrostatic discharge protective circuit and relevant techniques

Info

Publication number: CN100382313C
Application number: CNB2005101288407A
Authority: CN
Inventors: 陈科远
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2005-12-07
Filing date: 2005-12-07
Publication date: 2008-04-16
Anticipated expiration: 2025-12-07
Also published as: CN1805142A

Abstract

The present invention provides an electrostatic discharge protective circuit and relevant techniques. When electrostatic discharge occurs between a cushion to be protected and a grounding cushion on a chip, the present invention can trigger a clamp circuit between the cushion to be protected and the grounding cushion according to the voltage difference between the cushion to be protected and another power source cushion to carry out the electrostatic discharge protection. Generally, a capacity effect essentially exists between the power source cushion and the grounding cushion of the chip and acts as a decoupling capacitor which is used for maintaining the electric stability, so that when the electrostatic discharge occurs, voltage on the power source cushion can not quickly increase along with the voltage on the cushion to be protected, and the voltage difference which is enough to trigger the clamp circuit can be provided. According to the principle, the present invention can reduce the layout area of the electrostatic discharge protective circuit by utilizing the capacity effect which essentially exists on the chip.

Description

Electrostatic storage deflection (ESD) protection circuit

Skill this area

The present invention relates to a kind of electrostatic storage deflection (ESD) protection circuit and correlation technique, particularly relate to a kind of electrostatic storage deflection (ESD) protection circuit and correlation technique that can effectively realize electrostatic discharge protective with the layout of simplifying.

Background technology

In order to make chip can receive extraneous grid bias power supply, and can with extraneous other circuit/chip swap data, can be provided with the connection pad (pad) of conduction on the chip.For example, for positive voltage and the ground voltage that transmits the grid bias power supply two ends, can be provided with power supply connection pad (power pad) and ground connection pad (groundpad) on the chip; In like manner, also can be provided with signal on the chip and export/go into connection pad (I/O pad), with receiving inputted signal or/and send output signal.

Yet when the connection pad false touch static power supply (for example being human body or machining machine and tool etc.) of a chip, a large amount of static discharge current of this static power supply will flow into via connection pad in the chip; If the chip internal circuit born excessive electric current, may will burn and can't normal operation.Therefore, in general, all can be provided with electrostatic storage deflection (ESD) protection circuit between each connection pad of chip.The basic function of electrostatic storage deflection (ESD) protection circuit is, when chip between two connection pads during false touch static power supply, electrostatic storage deflection (ESD) protection circuit can be between two connection pads low-impedance current path of conducting, make the electric current of static power supply discharge can be preferentially from then on a current path flow through and can not flow into other internal circuit of chip; So, just can protect other internal circuit in the chip not to be subjected to electrostatic discharge effect.In the equivalence, when electrostatic discharge event took place, electrostatic discharge protection circuit was exactly the electric current of two connection pad short circuits being guided static discharge, with the electric current of bypass (bypass) static discharge, made it can not flow into other internal circuit in the chip.But, when chip during in normal operation, electrostatic discharge circuit will be ended its current path of setting up between two connection pads, with the normal function of obstruction free chip.

In other words, electrostatic storage deflection (ESD) protection circuit itself must want to differentiate the difference between electrostatic discharge event and chip normal operation, to avoid wrong startup.In order to differentiate above-mentioned these two kinds of situations, electrostatic discharge protection circuit is to power on according to connection pad to press the time rate of change that rises and judge it is normal power initiation (power-on) or unusual electrostatic discharge event usually.In electrostatic discharge event, static power supply regular meeting causes the voltage on the connection pad to raise fast, its rise time (raise time) about tens of to hundreds of nanoseconds (ns, 1 nanosecond=10 ^-9Second) degree.In normal power initiation process, the rate of voltage rise on the connection pad (similarly being the power supply connection pad) will be slower, be everlasting millisecond (ms, 1 millisecond=10 of its rise time ^-3Second) degree.According to the difference in size of this voltage rise time (time rate of change), electrostatic storage deflection (ESD) protection circuit just can be differentiated normal start or electrostatic discharge event.

According to above-mentioned principle; when prior art will be protected a given connection pad (similarly being a power supply connection pad); existing electrostatic storage deflection (ESD) protection circuit can connect contact in regular turn a resistance and an electric capacity and hold resistance (electric capacity-resistance to form one on this given connection pad; RC) network; hold the resistance network with this and differentiate the time rate of change that this connection pad voltage rises, and judge in view of the above on this desire protection connection pad whether electrostatic discharge event has taken place.When on the desire protection connection pad electrostatic discharge event taking place, the voltage on this given connection pad can rise rapidly, and its rise time can be less than the time constant of holding the resistance network (time constant, the i.e. product of capacitance and resistance value in the appearance resistance network); Hold the resistance network and have little time response, so the cross-pressure of electric capacity can temporarily be kept inconvenience, and the voltage that rises suddenly on the given connection pad will be reflected as the cross-pressure that increases rapidly on the resistance.According to the cross-pressure that rises suddenly on the resistance, existing electrostatic storage deflection (ESD) protection circuit just can trigger clamped circuit and begin conductive current path on the given connection pad of desire protection, with the current bypass of static discharge.Relatively, when chip is wanted normal operation and when carrying out normal power initiation, the voltage on the given connection pad only can slowly rise in the power initiation process, its rise time can be much larger than the time constant of holding the resistance network, hinders network and can fully respond so hold.Therefore, in the power initiation process, the voltage that rises gradually on this given connection pad can be reflected in the cross-pressure that increases gradually on the electric capacity, makes the resistance cross-pressure very little and almost remain unchanged, and the conducting so clamped circuit can not be triggered is with the normal operation of obstruction free chip.

But, above-mentioned prior art also has shortcoming.One of its shortcoming can take bigger layout area exactly.In order to form the above-mentioned appearance resistance network that can differentiate electrostatic discharge event/normal operation, existing electrostatic storage deflection (ESD) protection circuit must realize out sizable electric capacity of capacitance and the sizable resistance of resistance value, and this will take a large amount of layout areas.In general, to hold the resistance network and can differentiate difference between electrostatic discharge event and normal operation in order to make, the time constant of holding the resistance network was required to be about 150 to 200 nanoseconds, and this time constant need could be realized with sizable electric capacity.Because must including the electric capacity of this big capacitance in, existing electrostatic discharge protective technology could realize electrostatic storage deflection (ESD) protection circuit, so existing electrostatic storage deflection (ESD) protection circuit will take sizable layout area, the integrated level that is unfavorable for chip also makes the chip design production cost increase.

Summary of the invention

Therefore, main purpose of the present invention is to propose a kind of electrostatic storage deflection (ESD) protection circuit and correlation technique that can economization electric capacity layout area, to overcome the shortcoming of prior art.In general, chip itself will be set up sizable electric capacity between power supply connection pad and ground connection pad, and the present invention just can directly utilize this potential electric capacity/capacity effect to realize the appearance resistance network that electrostatic storage deflection (ESD) protection circuit is required.Therefore, electrostatic storage deflection (ESD) protection circuit of the present invention does not just need to include large-area electric capacity again in, makes the present invention realize electrostatic storage deflection (ESD) protection circuit with less layout area, the circuit arrangement of simplifying, for chip is set up electrostatic discharge protective mechanism.

In an embodiment of the present invention; in the time of will between a certain given connection pad (can be that connection pad or power supply connection pad are exported/gone into to signal) of chip and a ground connection pad, setting up electrostatic discharge protective mechanism; can utilize independently power supply connection pad of another one, between these three connection pads (connection pad-ground connection pad-another power supply connection pad of desire protection), set up the present invention's electrostatic storage deflection (ESD) protection circuit.In one embodiment of this invention, can protect between connection pad and the ground connection pad in desire a clamped circuit is set, this clamped circuit has a controlled end to accept triggering signal.In order to control the triggering of clamped circuit; one embodiment of the invention can be with a p type metal oxide semiconductor transistor as circuits for triggering; its source electrode is connected in desire protection connection pad; grid is connected to the power supply connection pad via one as the resistance of transmission circuit, and drain electrode then is connected in the controlled end of clamped circuit.Dispose with this, the present invention just can utilize and come framework to go out one with regard to the capacity effect that has originally between the resistance of this transistor gate and power supply connection pad-ground connection pad to hold the resistance network; When electrostatic discharge event betided on the desire protection connection pad, this holds the resistance network will make clamped circuit conductive current path between desire protection connection pad and ground connection pad via the trigger circuit triggers clamped circuit, carries out electrostatic discharge protective.

On the other hand; one embodiment of the invention can be established a p type metal oxide semiconductor transistor in addition as a countercharge circuit in protection circuit; this transistorized grid can be adjusted circuit via one and be connected in this desire protection connection pad; drain electrode is used for sending a countercharge signal, and its source electrode then is connected with the transistorized grid of circuits for triggering.Arrange in pairs or groups this one the countercharge circuit, protection circuit of the present invention also can be provided with a n-type metal oxide semiconductor transistor as anti-circuits for triggering, its drain electrode is connected in the controlled end of clamped circuit, and source electrode is connected in the ground connection pad, and grid then is controlled by the countercharge signal of the circuit of countercharging.When chip will begin normal operation and when carrying out power initiation (power on), countercharge circuit/anti-circuits for triggering will make not conducting of clamped circuit, in order to avoid influence the normal operation of chip.When chip is finished power initiation and during normal operation, countercharge circuit/anti-circuits for triggering also can be maintained at clamped circuit the state of not conducting constantly.

Except that the foregoing circuit unit, electrostatic storage deflection (ESD) protection circuit of the present invention also can be provided with other interlock circuit unit, similarly be as an auxiliary circuit with a n-type metal oxide semiconductor transistor or another clamped circuit, this transistorized grid is controlled by the controlled end of former clamped circuit, and drain electrode and source electrode then are connected between transistorized grid of circuits for triggering and ground connection pad.When circuits for triggering begin when the controlled end of clamped circuit triggers clamped circuit, auxiliary circuit can be triggered in the lump, and to the ground connection pad, acceleration/enhancing circuits for triggering are to the triggering of clamped circuit with the transistorized gate turn-on of circuits for triggering.

Basically, one of advantage of the present invention can directly be utilized exactly between power supply connection pad and ground connection pad and realize that with regard to setting up good capacity effect the appearance in the electrostatic storage deflection (ESD) protection circuit hinders network originally, so the present invention can simplify the required extra layout area of electric capacity in electrostatic storage deflection (ESD) protection circuit, so that can realize electrostatic discharge protective mechanism more economically.The present invention has multiple different embodiment, will describe for example in the back.

Description of drawings

Fig. 1 is the circuit diagram of conventional electrostatic discharge protection circuit.

Fig. 2 is the circuit arrangement schematic diagram of protection circuit one embodiment of the present invention.

Fig. 3 is the schematic diagram of circuit when meeting with electrostatic discharge event among Fig. 2.

Fig. 4 is the schematic diagram of circuit under normal operation among Fig. 2.

Fig. 5 is the circuit arrangement schematic diagram of another embodiment of protection circuit of the present invention.

Fig. 6 is the schematic diagram of circuit when meeting with electrostatic discharge event among Fig. 5.

Fig. 7, Fig. 8 and Fig. 9 have illustrated the different embodiment of protection circuit of the present invention respectively.

Figure 10 has further illustrated the operation principles and the implementation of circuit among Fig. 9.

Figure 11, Figure 12 and Figure 13 have illustrated the different embodiment of protection circuit of the present invention respectively.

The reference numeral explanation

10,20,50,80,100,120,140,160,180 protection circuits

12,34,64,104,124,144,164,184 internal circuits

14,40,70,90,110,130,170,190 chips

16,32,62,92,94,102,126,146,166,182 clamped circuits

22,52,82 circuits for triggering

24,54,84 anti-circuits for triggering

26,56,86 countercharge circuit

28,58,88,122,142,162 adjust circuit

30,60,91 transmission circuits

66 auxiliary circuits

68,96,98,106 intermediate circuits

Pb, Pi, Ni, Nb, Nm, Nn node

R0, R, Ra, Rg resistance

CO, Cd electric capacity

D, Df1-Df2, Db1-Db2, DF diode

Qn, Qp, Mn, Mp, Ma, Mb, Mc, Md, Me, Mf transistor

VDD, VCC, GND, VSS, I/O, VEE, PD connection pad

Vesd static power supply

Vcc, Vdd grid bias power supply

The Vx input

Vy output

Vee, Vss voltage

P-well p type trap

N-well n type trap

The substrate of p-substrate p type

The G grid

The S source electrode

The D drain electrode

The B body utmost point

Embodiment

Please refer to Fig. 1; Fig. 1 is the circuit diagram of a traditional protection circuit 10.This traditional protection circuit 10 is located in the chip 14, is used for realizing an electrostatic discharge protective mechanism into chip 14.Chip 14 is provided with connection pad VDD and connection pad GND, so that internal circuit 12 energy and external circuitry in the chip 14 are electrically connected.Wherein, internal circuit 12 can include core processing circuit (similarly being all gate/computings/processing/circuit such as storage) and the interface circuit of exporting buffering, to realize the major function of chip 14.Connection pad VDD can be a power supply connection pad (power pad), and connection pad GND then can be a ground connection pad (ground pad); Utilize this two connection pads, internal circuit 12 just can be connected to the outer grid bias power supply of chip, so that internal circuit 12 can be respectively be biased in the positive voltage and the ground voltage of grid bias power supply via connection pad VDD and GND.For the electrostatic discharge event that protects between connection pad VDD and the connection pad GND (similarly is a static discharge between so-called holotype power supply, positive mode power-rail ESD), just be provided with the protection circuit 10 of traditional design between this two connection pad, with as an electrostatic storage deflection (ESD) protection circuit.

As shown in Figure 1, in traditional protection circuit 10, be between connection pad VDD and connection pad GND, contact in regular turn a resistance R 0 and a capacitor C 0, hold the resistance network to form one.P type metal oxide semiconductor transistor Qp and n-type metal oxide semiconductor transistor Qn then are connected to an inverter between connection pad VDD and connection pad GND, the grid of this two transistor (being equivalent to the input of inverter) promptly is controlled by and holds the voltage of resistance network at node Pi, and the triggering of a clamped circuit 16 is then controlled in the drain electrode of two transistor (being equivalent to the output of inverter) at node Pb.When being connected clamped circuit 16 between connection pad VDD and connection pad GND when being subjected to high voltage and triggering, clamped circuit 16 will be between this two connection pad the low-impedance current path of conducting.

The principle of tradition protection circuit 10 runnings can be described below.When the one static power supply Vesd of false touch between connection pad VDD and the connection pad GND (similarly being static discharge power supply between the power supply of holotype), the cross-pressure between connection pad VDD and connection pad GND can raise rapidly; In other words, with respect to the voltage (can be considered the ground end of static power supply Vesd) of connection pad GND, the voltage on the connection pad VDD can raise rapidly.For the node Pi that holds the resistance network, the voltage that has little time to respond at connection pad VDD owing to capacitor C 0 rises suddenly, so the voltage of node Pi can temporarily be maintained at the low-voltage of connection pad GND.Because the level of node Pi is maintained at low-voltage, but the source electrode of transistor Qp is a high voltage because being connected in connection pad VDD again, both voltage differences just can make transistor Qp conducting.The transistor Qp of conducting can make node Pb voltage follower connection pad VDD voltage and raise, and then trigger clamped circuit 16 and come into operation; And clamped circuit 16 also will be between connection pad VDD and connection pad GND conducting one low impedance current path with the static discharge current of conduct static power supply Vesd; So, the static discharge current that is flowed into by the connection pad vdd terminal will preferentially be back to connection pad GND by clamped circuit 16, can not flow into internal circuit 12, to realize the purpose of electrostatic discharge protective.

Relatively, when chip will begin normal operation and begin to carry out power initiation, hold the electric capacity response signal levels variation fully in the resistance network, so voltage that the voltage of node Pi will be followed node VDD, this can make transistor Qp stop conducting, so clamped circuit 16 will stop to be triggered, and stops at conducting between connection pad VDD and the connection pad GND, with the normal operation of obstruction free chip 12.

But, just as shown in fig. 1,,, be unfavorable for the chip application of high integration so can significantly increase total layout area of protection circuit 10 because the conventional art among Fig. 1 need be included a capacitor C 0 in protection circuit 10.

In order to overcome the shortcoming of above-mentioned having now/traditional protection circuit, the present invention proposes the electrostatic storage deflection (ESD) protection circuit of preferred architecture.Please refer to Fig. 2, Fig. 2 is the circuit arrangement schematic diagram of electrostatic storage deflection (ESD) protection circuit one embodiment 20 of the present invention.Protection circuit 20 is arranged in the chip 40, and this chip 40 can be provided with two connection pad VCC and VDD as the power supply connection pad, and the connection pad VSS as the ground connection pad, is used for making the internal circuit 34 of chip 40 can receive extraneous grid bias power supply.When chip 40 normal operations, connection pad VCC can make internal circuit 34 be biased in two different positive voltages respectively with VDD, and connection pad VSS then is the bias voltage of internal circuit 34 transmission ground voltages.For instance, connection pad VCC can be the bias plasma pressure side of 3.3 volts (volt), and connection pad VDD then can be 2.5 volts a bias plasma pressure side, with the needed different bias voltages of the electronic circuit that difference in functionality in the internal circuit 34 is provided.For preventing electro-static discharge incident between connection pad VDD and connection pad VSS (for example being electrostatic discharge event between the power supply of holotype), the present invention can be provided with protection circuit 20 between connection pad VCC, VDD and VSS.Concerning the embodiment of Fig. 2, under the preferred application environment of protection circuit 20 of the present invention, connection pad VCC is used for accepting higher bias voltage, and connection pad VDD then is used for accepting lower bias voltage.

In general, chip all can be connected with sizable electric capacity between its power supply connection pad and ground connection pad, similarly be decoupling capacitor, so that it is stable to assist to keep power supply when chip operates, various noises in the opposing power supply similarly are Switching Noise (simultaneous switching noise).Since chip itself will be set up sizable electric capacity between power supply connection pad and ground connection pad, the present invention just can directly utilize this potential electric capacity/capacity effect to realize the appearance resistance network that electrostatic storage deflection (ESD) protection circuit is required.In the embodiment of Fig. 2, the present invention will utilize the potential capacity effect that originally just has between connection pad VCC and VSS to realize the present invention's electrostatic defending technology.

In the embodiment of Fig. 2, protection circuit 20 of the present invention can be provided with circuits for triggering 22, one anti-circuits for triggering 24, a countercharge circuit 26, a transmission circuit 30, an adjustment circuit 28 and a clamped circuit 32 that is arranged between connection pad VDD, VSS; And node Nb just can be considered the controlled end of clamped circuit 32.When the controlled thus termination of clamped circuit 32 is received a high-tension triggering signal, clamped circuit 32 just can be between connection pad VDD, VSS conducting one low-impedance current path; Otherwise 32 of clamped circuits can stop conducting (stopping at conducting between connection pad VDD, VSS).As for the triggering signal of node Nb, then control by circuits for triggering 22 and anti-circuits for triggering 24.As shown in Figure 2, circuits for triggering 24 are connected in connection pad VDD, also are connected to connection pad VCC via transmission circuit 30; Via the transmission of transmission circuit 30, these circuits for triggering 24 can be obtained the power level (for example being voltage) on the connection pad VCC, and can compare the power level on connection pad VCC and the connection pad VDD.The power level and the difference between the two that are higher than on the connection pad VCC when the power level on the connection pad VDD have surpassed one first definite value, and circuits for triggering 22 just can send a triggering signal to clamped circuit 32; Otherwise circuits for triggering 22 will stop to send triggering signal.26 in circuit of countercharge is connected in connection pad VCC via transmission circuit 30, and is connected in connection pad VDD via adjusting circuit 28.Adjust circuit 28 and can produce a reference level according to the power level on the connection pad VDD; In this embodiment, adjust circuit 28 be directly with the power level on the connection pad VDD as reference level.When the power level on the connection pad VCC greater than this reference level and difference between the two during greater than one second definite value, countercharge circuit 26 just can send the signal of countercharging at node Nn; Otherwise this countercharge circuit can stop to send this countercharge signal.24 of anti-circuits for triggering are connected in countercharge circuit 26 in node Nn; When countercharge circuit 26 sent the countercharge signal, anti-circuits for triggering 24 just can stop clamped circuit is sent triggering signal with circuits for triggering 22.

As shown in Figure 2, in protection circuit 20, be to realize circuits for triggering 22, realize anti-circuits for triggering 24, and realize transmission circuit 30 respectively and adjust circuit 28 with resistance R, Ra with a n-type metal oxide semiconductor transistor Mn with a p type metal oxide semiconductor transistor Mp.Wherein, the source electrode of transistor Mp is connected in connection pad VDD, and grid (node Nm) then is connected in connection pad VCC via resistance R.The drain electrode of transistor Mn and Mp then is connected in the triggering of node Nb with control clamped circuit 32 jointly.In addition, 26 available another p type metal oxide semiconductor transistor Ma of countercharge circuit realize, the source electrode of this transistor Ma is connected in connection pad VDD at node Nm via resistance R a, grid is connected in connection pad VCC in node Ni via resistance R, grid then can be in node Nn with the anti-circuits for triggering 24 of countercharge signal controlling.Just can find out that by Fig. 2 the protection circuit 20 of the present invention not traditional protection circuit 10 in the image pattern 1 equally needs to include in electric capacity and is combined into and holds the resistance network.

More particularly, adjust the grid that circuit 28 is connected in connection pad VDD and countercharge circuit 26, using provides a reference level to the circuit 26 of countercharging.When the power level on the connection pad VCC greater than this reference level and difference between the two during greater than one second definite value, countercharge circuit 26 just can send the signal of countercharging at node Nn; Otherwise this countercharge circuit can stop to send this countercharge signal.In the present embodiment, 26 available another p type metal oxide semiconductor transistor Ma of countercharge circuit realize that then this second definite value is the threshold voltage value of this p type metal oxide semiconductor transistor Ma | Vth_Ma| (thresholdvoltage).24 of anti-circuits for triggering are connected in countercharge circuit 26 in node Nn; When countercharge circuit 26 sent the countercharge signal, anti-circuits for triggering 24 just can stop clamped circuit is sent triggering signal with circuits for triggering 22.

In addition, adjust the electric current that produces when resistance R a in the circuit 28 also can prevent the electric current of static discharge or abnormal operation when electrostatic discharge event the takes place countercharge circuit 26 of directly flowing through, with the damage of the circuit 26 of avoiding countercharging.Similarly, the electric current that the resistance R in the transmission circuit 30 produces in the time of can the preventing abnormal operation circuits for triggering 22 of directly flowing through are to avoid the damage of circuits for triggering 22.

About the situation of protection circuit 20 runnings of the present invention, please continue with reference to figure 3 (and in the lump with reference to figure 2); Embodiment among continuity Fig. 2, Fig. 3 are the situation of Fig. 2 chips 40 when meeting with electrostatic discharge event.As chip 40 false touch one static power supply Vesd and when meeting with electrostatic discharge event, the cross-pressure between connection pad VDD and VSS can raise rapidly between connection pad VDD and VSS; That is to say that with respect to the power level on the connection pad VSS (it can be considered the earth terminal of static power supply Vesd), the power level on the connection pad VDD can rise rapidly.In comparison, the voltage at connection pad VCC end then can be maintained at low-voltage.Just as discussed earlier, just had potential electric capacity (similarly being decoupling capacitor) between connection pad VCC and the VSS originally, it can equivalence be the capacitor C d among Fig. 3; When meeting with electrostatic discharge event between connection pad VDD/VSS, connection pad VCC can be considered suspension joint, and the resistance R in this capacitor C d and the transmission circuit 30 just can form an equivalence appearance resistance network naturally.When the voltage on the connection pad VDD rose suddenly, this appearance resistance network will temporarily be kept the power level on the connection pad VCC, makes it be maintained low-voltage, and related grid with transistor Mp is maintained at low-voltage.At this moment, the transistor Mp in circuits for triggering 22, its source voltage is a high voltage because of being connected in connection pad VDD, its grid voltage is a low-voltage because of the effect of connection pad VCC (with capacitor C d) then, make between the two power level can surpass the threshold voltage of transistor Mp | Vth_Mp|, so circuits for triggering 22 will conducting, and the power level on the connection pad VDD is coupled to node Nb, just sends a triggering signal with the high voltage on the connection pad VDD to clamped circuit 32 in the equivalence; And clamped circuit 32 is triggered by this; just can be between connection pad VDD and VSS conducting one low-impedance current path; attract the discharging current of static power supply Vesd, allow most discharging current directly pass through and to flow out, with the internal circuit 34 of protection chip 40 by connection pad VSS by clamped circuit 32.

When circuits for triggering 22 when triggering clamped circuit 32, the transistor Ma in countercharge circuit 26, the voltage of its grid (node Ni) is high voltage (because of connection pad VDD just meets with electrostatic discharge event), its source electrode then is maintained at low-voltage because of connection pad VCC (with capacitor C d), so not conducting of transistor Ma.Jointly, the transistor Mn in the anti-circuits for triggering 24 can conducting yet, and the power level of node Nb will be by circuits for triggering 22 master controls.In other words, when circuits for triggering 22 when triggering clamped circuit 32, countercharge circuit 26 and anti-circuits for triggering 24 can not act on, and can not interfere the triggering of 22 pairs of clamped circuits 32 of circuits for triggering.

The embodiment of continuity Fig. 2 and Fig. 3 please continue with reference to figure 4; What Fig. 4 illustrated is the situation of Fig. 2 chips 40 when normal operation.For the protection circuit of the present invention 20 among Fig. 2, under its preferable applied environment, connection pad VDD is to be used for accepting different bias voltages respectively with VCC, and when coming into operation/carrying out power initiation (power-on) at chip, connection pad VDD can set up its bias voltage more quickly, and connection pad VCC can set up its bias voltage more slowly.That is to say, as shown in Figure 4, when chip 40 will begin normal operation and will begin to accept the bias voltage of extraneous grid bias power supply Vdd, Vcc respectively between connection pad VDD, VCC and VSS, voltage on the connection pad VCC can be higher than the voltage on the connection pad VDD, make the transistor Mp in the circuits for triggering 22 can conducting, circuits for triggering 22 just can not trigger clamped circuit 32 yet, with the normal operation of obstruction free chip 40.By the time power initiation finishes and connection pad VDD, VCC when beginning stably to accept specified running bias voltage, connection pad VCC can be greater than the reference level at node Ni at the voltage of node Nm, and difference between the two is greater than the threshold voltage of transistor Ma | Vth_Ma|, so can make transistor Ma conducting.The transistor Ma of conducting can be coupled to the voltage of node Nm node Nn, and making the voltage of node Nn is high voltage, and makes the transistor Mn conducting in the anti-circuits for triggering 24.The transistor Mn of conducting can be coupled to the voltage of node Nb the voltage of ground connection pad VSS, makes the voltage of node Nb be maintained at low-voltage, constantly clamped circuit 32 is maintained at the state that is not triggered.In the equivalence, the conducting of transistor Ma just is equivalent to send a high-tension countercharge signal to node Nn in the countercharge circuit 26, this countercharge signal makes anti-circuits for triggering 24 begin effect, clamped circuit 32 is continued to be maintained at the state of (not conducting) of not being triggered, in order to avoid clamped circuit 32 hinders the normal operation of chips 40.Shown in the circuit arrangement among Fig. 4, when anti-circuits for triggering 24 are done the time spent, the transistor Mp in the circuits for triggering 22 can't conducting, makes clamped circuit 32 can come master control by anti-circuits for triggering 24 in the controlled end of node Nb.

Complex chart 2 to Fig. 4 as can be known, the present invention can not be used in and include electric capacity in the protection circuit in, when connection pad VDD upward rises suddenly because of electrostatic discharge event voltage, the present invention just can directly utilize between power supply connection pad VCC/ ground connection pad VSS and originally keep the low-voltage of power supply connection pad VCC with regard to the capacity effect that has, and utilizes connection pad VDD/VCC big voltage difference between the two to come start triggering circuit, triggering clamped circuit to begin to carry out electrostatic discharge protective.Also therefore, the present invention can effectively realize electro-static discharge protection function with less layout area more economically in chip.Concerning the embodiment among Fig. 2 to Fig. 4, under the preferred application environment of protection circuit 20,, between connection pad VDD and the VCC suitable electrical isolation can be arranged in order when electrostatic discharge event takes place, to keep the voltage difference between the connection pad VDD/VCC.For example, between connection pad VDD and the VCC can be electric insulation (isolated); Perhaps, can be connected with the diode of one or more polyphone between the connection pad VDD to VCC, when electrostatic discharge event takes place, suitably to keep voltage difference between the two.

Please refer to Fig. 5, Fig. 5 is the circuit arrangement schematic diagram of another embodiment 50 of protection circuit of the present invention; This protection circuit 50 is located in the chip 70.Chip 70 is provided with connection pad VCC, VDD (can be two power supply connection pads) and connection pad VSS (can be the ground connection pad), is used for making the internal circuit 64 of chip 70 can accept the bias voltage of extraneous grid bias power supply respectively; Protection circuit 50 promptly is located between this three connection pad, with the performance electro-static discharge protection function, for example is to take precautions against electrostatic discharge event between contingent holotype power supply between connection pad VDD and the VSS.Be similar to the embodiment among Fig. 2, the protection circuit 50 among Fig. 5 also is provided with circuits for triggering 52, one anti-circuits for triggering 54, a countercharge circuit 56, a clamped circuit 62, a transmission circuit 60, an adjustment circuit 58.Different with protection circuit 20 is that the protection circuit 50 among Fig. 5 also is provided with an auxiliary circuit 66 in addition; In addition, between connection pad VDD and node Nm, also be provided with an intermediate circuit 68.As shown in Figure 5, auxiliary circuit 66 can realize that the grid of this transistor Mb is connected in contact Nb with a n-type metal oxide semiconductor transistor Mb, with the clamped circuit 62 the same voltage signals that are controlled by on the node Nb; The drain electrode of transistor Mb, source electrode then are connected between node Nm and the Nn.68 available strings of intermediate circuit meet at least one diode D and realize.

Please continue with reference to figure 6; The embodiment of continuity among Fig. 5, that illustrates among Fig. 6 is the situation of Fig. 5 chips 70 when meeting with electrostatic discharge event.When between the connection pad VDD of chip 70 and VSS during false touch one static power supply Vesd, when can be considered a static power supply Ves d and being connected between connection pad VDD, VSS, with respect to the voltage on the connection pad VSS, the power level on the connection pad VDD (voltage) can rise rapidly.Relatively, on the connection pad VCC of suspension joint (floating), then can make the voltage of connection pad VCC be maintained at low-voltage because of the capacity effect that originally exists between connection pad VCC and VSS (its can equivalence be a capacitor C d); So, will between connection pad VDD and VCC, form voltage difference; Simultaneously, 68 of intermediate circuits can assist/guarantee between connection pad VDD and connection pad VCC certain voltage difference to be arranged.Voltage difference between connection pad VDD and VCC can be via connection pad VDD and node Nm and is made transistor Mp conducting.The transistor Mp of conducting can be coupled to the high voltage of connection pad VDD node Nb, be equivalent to send a high-tension triggering signal at node Nb, to trigger clamped circuit 62 beginnings at connection pad VDD, the low-impedance current path of VSS conducting, the performance electro-static discharge protection function.

When the transistor Mp in the circuits for triggering 52 begins conducting and when triggering clamped circuit 62 with high voltage, auxiliary circuit 66 also can be triggered by activation together; And the auxiliary circuit 66 that triggers that is enabled just can further make the power level of node Nm (and connection pad VCC) reduce, and the power level difference between connection pad VCC and connection pad VDD is further increased.As shown in Figure 6, the high voltage of node Nb (with the low-voltage of connection pad VSS) can make the transistor Mb conducting in the auxiliary circuit 56, makes node Nm be coupled to connection pad VSS via the transistor Mb of conducting; In the equivalence, the voltage on the connection pad VCC also will be pulled low to the voltage of connection pad VSS jointly.As shown in Figure 6, when the electrostatic discharge event among chip 70 experience Fig. 6, connection pad VCC is suspension joint basically; Though capacitor C d (with intermediate circuit 68) can be with being maintained at lower voltage and can not following the voltage that rises suddenly on the connection pad VDD on the connection pad VCC, but the voltage on the connection pad VCC may still be higher than the voltage on the connection pad VSS, make the voltage difference between connection pad VDD and connection pad VCC may can only make the transistor Mp in the circuits for triggering 52 that preliminary conducting takes place, can't make the complete conducting of transistor Mp.Jointly, upward the voltage of triggering signal also can be lower slightly than the voltage on the connection pad VDD for node Nb, and can't fully make clamped circuit 62 conductings.Yet after auxiliary circuit 66 beginning conductings, the voltage of node Nm will be dragged down further by the transistor Mb of conducting, make the voltage (voltage on the connection pad VCC just) of node Nm can be more near the voltage of connection pad VSS.So, the voltage difference between connection pad VDD and VCC will further enlarge, and guarantees the transistor Mp conducting fully in the circuits for triggering 52, so that the voltage that node Nb goes up triggering signal is more near the voltage of connection pad VDD; Jointly, can guarantee clamped circuit 62 conducting fully, bring into play better electro-static discharge protection function.

In other words, when meeting with electrostatic discharge event, via the assistance of auxiliary circuit 66, the voltage difference between connection pad VDD and VCC can be deepened, with faster, trigger clamped circuit 62 more completely, given play to better electro-static discharge protection function.

Be similar to the embodiment among Fig. 2, with the embodiment of the present invention in Fig. 5, under the preferred application environment of protection circuit 50, connection pad VDD and VCC are used for accepting higher Yu a lower bias voltage respectively, and when coming into operation/carrying out power initiation (power-on) at chip, transistor Mp in the circuits for triggering 52 can not be switched on, and clamped circuit 62 (with the auxiliary circuit 66) activation that can not be triggered is with the normal operation of obstruction free chip 70.Be similar to the embodiment among Fig. 2, under the preferred application environment of protection circuit 50 (Fig. 5),, between connection pad VDD and the VCC suitable electrical isolation can be arranged in order when electrostatic discharge event takes place, to keep the voltage difference between the connection pad VDD/VCC.Picture just is provided with intermediate circuit 68, suitably to keep voltage difference between the two when electrostatic discharge event takes place between connection pad VDD and the VCC in Fig. 5.Intermediate circuit 68 can be that more than one diode serial connection is formed, and this voltage difference can and select suitable diode to be controlled via the number of diodes that is connected in series.

Please refer to Fig. 7.Fig. 7 is the circuit diagram of another embodiment 80 of protection circuit of the present invention.Protection circuit 80 is arranged in the chip 90, and this chip 90 has two power supply connection pad VCC, VDD and two ground connection pad VSS, GND; When chip 90 during in normal operation, connection pad VCC, VDD can make chip 90 be biased in two different positive voltages respectively, and connection pad VSS and GND then can make chip 90 be biased in ground voltage.And protection circuit 80 of the present invention can be located between these four connection pads, with the electrostatic discharge event between the protection connection pad, for example is electrostatic discharge event between the holotype power supply between connection pad VDD and the VSS.Be similar to the circuit arrangement among Fig. 5, the protection circuit 80 among Fig. 7 also is provided with circuits for triggering 82 (with p type metal oxide semiconductor transistor Mp realization), anti-circuits for triggering 84 (realizing with n-type metal oxide semiconductor transistor Mn), a countercharge circuit 86 (realizing with p type metal oxide semiconductor transistor Ma), a clamped circuit 92, a transmission circuit 91 (realizing with resistance R) and an adjustment circuit 88 (realizing with resistance R a).The clamped circuit 92 between connection pad VDD and VSS, also be provided with another clamped circuit 94 between connection pad VCC and the GND; Clamped circuit 92 is the same with 94 to be controlled end with node Nb, and therefore, when clamped circuit 92 was triggered, clamped circuit 94 also can be triggered.

In addition, also be provided with intermediate circuit 98 between connection pad VDD and the VCC, also be provided with another intermediate circuit 96 between connection pad VSS and the GND.As shown in Figure 7, can be provided with the back to back diode Df1 and the Db1 of a plurality of serial connections in the intermediate circuit 98; In like manner, also can be provided with the back to back diode Df2 and the Db2 of a plurality of serial connections in the intermediate circuit 96.

In fact, in protection circuit 80, be connected to two clamped circuits 92,94 between two pairs of power supply connection pad-ground connection pads, its configuration is just as clamped circuit in the protection circuit 50 (Fig. 5) 52 and auxiliary circuit 66.In other words, the clamped circuit 94 among Fig. 7, its effect just as same auxiliary circuit, when protection circuit 80 when carrying out electrostatic discharge protective, clamped circuit 94 can assist to make clamped circuit 92 acceleration, deepen its conducting degree.The situation of protection circuit 80 when carrying out electrostatic discharge protective can be described below.As shown in Figure 7, when meeting with electrostatic discharge event (similarly being electrostatic discharge event between a holotype power supply) as the one static power supply Vesd of false touch between connection pad VDD and VSS, voltage on the connection pad VDD rises suddenly, relatively, voltage on the connection pad VCC then can be maintained at a lower voltage because of the effect of capacity effect between power supply connection pad-ground connection pad (similarly being the capacity effect that is provided by decoupling capacitor) and intermediate circuit 98, and the voltage difference between connection pad VDD and VCC just can make the transistor Mp conducting in the circuits for triggering 82, high voltage on the connection pad VDD is coupled to node Nb, triggers clamped circuit 92 and 94.Clamped circuit 92 is can conducting between connection pad VDD and VCC after the triggering, and clamped circuit 94 further drags down with the voltage with connection pad VCC then can conducting between connection pad VCC and connection pad GND after the triggering, makes it level off to the voltage of connection pad GND.Via the transmission of intermediate circuit 96, the voltage of connection pad GND can approach the voltage of connection pad VSS.Therefore, clamped circuit 94 is subjected to will make the voltage of connection pad VCC lower after the triggering and conducting, makes voltage difference between connection pad VDD and connection pad VCC apart from increasing, and feedback makes its conducting degree of clamped circuit 92,94 acceleration/intensifications, strengthens electro-static discharge protective ability.That is to say that the function of clamped circuit 94 can equivalence be the auxiliary circuit 56 among Fig. 5.

With the embodiment of the present invention in Fig. 7, under the preferred application environment of protection circuit 80, connection pad VDD and VCC are used for accepting higher Yu a lower bias voltage respectively, and when coming into operation/carrying out power initiation (power-on) at chip, connection pad VDD can set up its higher biased more quickly, and connection pad VCC can set up its low bias voltage more slowly.So when chip 80 will begin normal operation and carry out power initiation, the transistor Mp in the circuits for triggering 82 can not be switched on, clamped circuit 92,94 activation that can not be triggered is with the normal operation of obstruction free chip 90.After all stably setting up other specified bias voltage on connection pad VDD, the VCC respectively, the transistor Ma of conducting can make transistor Mn conducting, and clamped circuit 92,94 is maintained at the state of not conducting, guarantees that the normal operation of chip 90 is unaffected.

In protection circuit 80, the intermediate circuit 98 that is connected between connection pad VCC, VDD can be used to realize a specific electrical couplings relation for these two connection pads.When carrying out electrostatic discharge protective, the diode Df1 of serial connection will guarantee to have between connection pad VDD and VCC enough voltage differences to come transistor Mp in the conducting circuits for triggering 82 in the intermediate circuit 98.Relatively, when chip 90 during in normal operation, each diode Db1 of each diode Df1 in intermediate circuit 98 and reversed polarity configuration just can be used to keep the interconnection coupling between connection pad VDD, VCC.Also draw the another kind of embodiment of intermediate circuit 98 among Fig. 7, just between connection pad VDD to VCC, established several diode Df1 more, can then can guarantee the startup of electrostatic discharge protective mechanism on the one hand as the electrical couplings path between connection pad VDD to VCC on the one hand; Diode Db1 then can be as the electrical couplings path between connection pad VCC to VDD.

When also can preventing to come into operation/carry out power initiation (power-on) at chip, intermediate circuit 98 becomes the possibility of circuits for triggering 82 false triggerings.Say more significantly, when coming into operation/carrying out power initiation (power-on) at chip, if connection pad VCC sets up its higher biased fast, and the bias voltage of connection pad VCC was higher than the bias voltage of connection pad VDD at that time, can improve the bias voltage of connection pad VDD via intermediate circuit 98, and the diode Db2 that is connected in series in the intermediate circuit 98 will guarantee to prevent the voltage difference between connection pad VDD and VCC the transistor Mp in the conducting circuits for triggering 82, thereby avoid the possibility of circuits for triggering 82 false triggerings.

The present invention is to be the situation that example illustrates protection circuit of the present invention protection power supply connection pad with the power supply connection pad in aforesaid embodiment; But, technical scheme of the present invention can certainly be used for protecting the signal of chip to export/go into connection pad.Please refer to Fig. 8; That Fig. 8 illustrates promptly is another embodiment 100 of protection circuit of the present invention; This protection circuit 100 is located in the chip 110.Connection pad VCC, VSS are arranged on the chip 100, and this two connection pad can be respectively power supply connection pad and ground connection pad; And connection pad I/O is a signal and exports/go into pad, and it can be used to make internal circuit 104 to be able to and extraneous other chip/circuit-switched signals (comprise from extraneous receiving inputted signal or/and the internal circuit signal is sent to the external world).In order to protect the last contingent electrostatic discharge event of connection pad I/O (similarly is so-called PS pattern static discharge pattern, be positive currentstress from i/o to VSS), can between connection pad I/O, connection pad VCC and VSS, constitute protection circuit 100 of the present invention.

As shown in Figure 8, an available transistor Mp is to realize circuits for triggering, to realize anti-circuits for triggering, realize a countercharge circuit, realize an auxiliary circuit, realize a transmission circuit, realize that with a resistance R a one adjusts circuit with a resistance R with a transistor Mb with a transistor Ma with a transistor Mn in the protection circuit 100, and between connection pad VCC and connection pad I/O, be provided with an intermediate circuit 106, then be provided with a clamped circuit 102 between connection pad I/O and the VSS.With connection pad I/O is desire protection connection pad, and transistor Ma can trigger clamped circuit 102 from node Nb according to the voltage difference between connection pad I/O and the connection pad VCC; Then can quicken/deepen the conducting degree of clamped circuit 102 as the transistor Mb of auxiliary circuit.When chip 110 during in normal operation, as the transistor Ma of countercharge circuit with all can conducting as the transistor Mn of anti-circuits for triggering so that clamped circuit 102 stop conductings.In addition, in the embodiment of Fig. 8, be to cooperate a resistance R g and a plurality of diode Df1, Db1 to realize intermediate circuit 106 with a p type metal oxide semiconductor transistor Mc; And this intermediate circuit 106 also can be connected in another power supply connection pad VEE.In addition, diode D also can be considered the intermediate circuit between connection pad I/O and VCC.In other words, illustrated the various realization technology of intermediate circuit among Fig. 8.

Shown just as Fig. 8, when meeting with an electrostatic discharge event as false touch one static power supply Vesd between connection pad I/O and the connection pad VSS, the voltage on the connection pad I/O can rise rapidly; In comparison, because the capacity effect between connection pad VCC and VSS and the effect of intermediate circuit 106 (with diode D), the voltage on the connection pad VCC can be maintained at a lower voltage; So, voltage difference between connection pad I/O and connection pad VCC will make transistor Mp conducting, voltage on the connection pad I/O is coupled to node Nb, be equivalent to clamped circuit 102 is sent a triggering signal, trigger clamped circuit 102 beginning conductings, to provide a low-impedance current path, prevent that the electric current of static discharge from directly entering internal circuit 104 and causing the static discharge injury at connection pad I/O and connection pad VSS.When clamped circuit 102 is triggered, as the transistor Mb of the auxiliary circuit conducting that also can be triggered, the voltage on the connection pad VCC is further dragged down, and even the conducting degree of intensification/acceleration circuits for triggering clamped circuit 102, any enhanced protection ability.

Concerning the embodiment of the present invention in Fig. 8, under the preferred application environment of protection circuit 100, the signal voltage cutting edge of a knife or a sword value (peak value) of exporting on the connection pad I/O/going into can be less than the bias voltage that is received on the connection pad VCC.When chip 110 will begin normal operation and carry out power initiation, voltage on the connection pad VCC can rise, voltage on the connection pad I/O closely voltage (because chip 110 also do not have commencing signal export into), so the voltage on the connection pad VCC can be greater than the voltage on the connection pad I/O, not conducting of transistor Mp as circuits for triggering, clamped circuit 102 is also with regard to not being triggered conducting, in order to avoid influence the power initiation of chip.Finish and chip 110 can normal operation the time Deng power initiation, the voltage on the connection pad VCC can be greater than the signal voltage cutting edge of a knife or a sword value on the connection pad I/O, and voltage difference between the two should make transistor Ma conducting; And the transistor Ma of conducting just can be coupled to node M n with the high voltage on the connection pad VCC and make transistor Mn conducting.Jointly, the transistor Mn of conducting just can be pulled low to the signal of node Nb the low-voltage of connection pad VSS, is not triggered so that clamped circuit 102 is maintained at, the state of not conducting, avoids clamped circuit 102 to hinder the normal operation of chips 110.

Please refer to Fig. 9.Fig. 9 has illustrated the configuration scenario of another protection circuit 120 of the present invention in a chip 130.Be similar to the embodiment among Fig. 8, the protection circuit 120 among Fig. 9 also be disposed at power supply connection pad VCC, connection pad VSS and signal export/go between the connection pad I/O, I/O goes up contingent electrostatic discharge event with the protection connection pad.In protection circuit 120, also realize circuits for triggering, realize anti-circuits for triggering, realize a countercharge circuit, realize an auxiliary circuit, realize a transmission circuit, and between connection pad I/O and VSS, be provided with a clamped circuit 126 with a resistance R with a transistor Mb with a transistor Ma with a transistor Mn with a transistor Mp; And between connection pad I/O and node Ni, then be provided with one and adjust circuit 122.In this embodiment, adjusting circuit 122 can realize with a n-type metal oxide semiconductor transistor Md.Chip 130 is when normal operation, the bias voltage (for example being to be provided by internal circuit 124) of a voltage Vee is provided its grid that can be transistor Md, and adjust circuit 122 will provide a correspondence according to the signal on the connection pad I/O on node Nb reference level (also can be described as a reference signal), and this reference signal goes up the result that signal carries out amputation (truncation) gained to connection pad I/O exactly.

Further, when chip 130 normal operations, the bias value of the bias value of connection pad I/O and connection pad VCC may be close.The bias voltage difference that is to say connection pad I/O and connection pad VCC can be less than the threshold voltage of transistor Ma | Vth_Ma|, make not conducting of transistor Ma, and give transistor Mn and send the countercharge signal.In the present embodiment, be serially connected between the grid and connection pad I/O of transistor Ma, can provide the reference level of a correspondence to be less than or equal to one the 3rd definite value, make transistor Ma can keep conducting via adjusting circuit 122.When these chip 130 normal operations, transistor Ma can send countercharge signal a to signal of countercharging and give transistor Mn, with guarantee clamped circuit 126 be maintained at be not triggered, the state of not conducting.

As shown in Figure 9, when meeting with an electrostatic discharge event as false touch one static power supply Vesd between connection pad I/O and the connection pad VSS, the voltage on the connection pad I/O can rise rapidly and voltage on the connection pad VCC can be maintained at a lower voltage; Voltage difference between connection pad I/O and connection pad VCC will make transistor Mp conducting, and then triggers clamped circuit 126 beginning conductings, carries out electrostatic discharge protective.Similarly, the transistor Mb conducting that also can be triggered, and even the conducting degree of intensification/acceleration circuits for triggering clamped circuit 126, any enhanced protection ability.

As for the operation principles of adjusting circuit 122, please further with reference to Figure 10; Embodiment among continuity Fig. 9, what Figure 10 illustrated is operation principle and the correlation technique of adjusting circuit 122 among Fig. 9.If with the signal voltage on the connection pad I/O is input Vx, serves as output Vy with the reference signal on the node Ni (reference level), then adjusts the output of circuit 122 and go into relation (transfer curve is gone in output just) just as shown in Figure 10; As input Vx during, adjust circuit 122 and can make output Vy follow input Vx (for example being to make Vy=Vx) less than the grid bias Vee of transistor Md; But if input Vx is during greater than the grid bias Vee of transistor Md, adjust the size that circuit 122 will limit output Vy, make output Vy can not surpass one the 3rd definite value, the 3rd definite value is the difference (Vee-|Vth_Md|) of the threshold voltage of the grid bias Vee of transistor Md and transistor Md.As discussed earlier, when chip 130 during, should keep conducting as the transistor Ma of countercharge circuit, to guarantee that via anti-circuits for triggering (transistor Mn) clamped circuit 126 is not triggered in normal operation.In order to keep the conducting of transistor Ma, the voltage on the node Ni than the voltage on the connection pad VCC low (and difference between the two should surpass the threshold voltage of transistor Ma | Vth_Ma|).Running via adjusting circuit 122 makes the voltage extremity of node Ni be no more than the 3rd definite value, to guarantee having enough voltage differences to keep the conducting of transistor Ma between connection pad VCC and node Ni.

In other words, because the signal that adjustment circuit 122 can reduce on the connection pad I/O provides reference signal, even the signal peak during the chip normal running on the connection pad I/O can be near the specified running bias voltage on (or equaling) connection pad VCC, adjust circuit 122 and all still can make transistor Ma continue conducting, so that clamped circuit 126 is maintained at the state of not conducting.On the other hand, because the body utmost point (bulk) of transistor Md can be connected to the connection pad I/O that signal changes with source electrode, so transistor Md can adopt the n-type metal oxide semiconductor transistor of multiple well structure.Also drawn the schematic diagram of multiple well structure among Figure 10.Just so shown in the schematic diagram, each utmost point of the n-type metal oxide semiconductor transistor of multiple well structure (comprising source S, grid G, drain D and body utmost point B) is to build on the n type trap (n-well), also have a p type trap (p-well) to center on and this n type trap is peripheral, so that transistorized body utmost point B is isolated from outside the n type substrate (n-substrate).So,, also can not disturb the bias voltage of n type substrate even the body utmost point B of transistor Md and source S all are connected in connection pad I/O, can be between the body utmost point B of transistor Md and the substrate of p type the conducting leakage current.In comparison, each source S, grid G, drain D and the body utmost point B of general n-type metal oxide semiconductor transistor (for example being transistor Mp or Ma) just can build on the substrate of n type, as shown in Figure 10.Modern semiconductor technology can realize the metal oxide semiconductor transistor of multiple trap at large.

Relatively the present invention in the embodiment of Fig. 5 and Fig. 9 as can be known, technical solution of the present invention can be used for protecting power supply connection pad (as the connection pad VDD among Fig. 5) and signal to export/go into connection pad (as the connection pad I/O among Fig. 9) widely.In like manner, the protection circuit of the present invention in Fig. 2 also can be used to protection and exports connection pad; About this situation, please refer to Figure 11.Figure 11 is the circuit arrangement schematic diagram of another embodiment 140 of protection circuit of the present invention.Protection circuit 140 is arranged between connection pad I/O (can be signal to export/go into to fill up), the connection pad VCC (can be a power supply connection pad) and connection pad VSS (can be a ground connection pad) of chip 150, to prevent electrostatic discharge event (for example being the electrostatic discharge event of PS pattern) the damage chip internal circuit 144 on the connection pad I/O.Be similar to the embodiment among Fig. 2, protection circuit 140 among Figure 11 is to realize drive circuit, realize anti-drive circuit, realize the countercharge circuit, realize transmission circuit with a resistance R with a transistor Ma with a transistor Mn with a transistor Mp, and is provided with a clamped circuit 146 between connection pad I/O and VSS; And between connection pad I/O and node Ni, then be provided with one and adjust circuit 142.In this embodiment, adjust the technology that circuit 142 can be continued to use embodiment among Fig. 9, realize with a n-type metal oxide semiconductor transistor Md.When chip 150 during in normal operation, its grid that can be transistor Md provides the bias voltage of a voltage Vee, and adjust circuit 122 will provide a correspondence according to the signal on the connection pad I/O on node Ni reference level (also can be described as a reference signal), make this reference level be no more than one the 3rd definite value.

When meeting with electrostatic discharge event as false touch static power supply Vesd between connection pad I/O and the VSS, clamped circuit 146 will be triggered conducting and carry out electrostatic defending; The principle of its running can repeat no more in this with reference to the embodiment among the figure 2.When chip 150 is wanted normal operation, the reference level that adjusting circuit 142 provides to guarantee the to countercharge conducting of circuit (transistor Ma) and anti-circuits for triggering (transistor Mn), so that clamped circuit 146 is maintained at the state of not conducting, with the normal operation of obstruction free chip 150.Operation situation and the implementation of adjusting circuit 142 can under the situation that does not influence the technology of the present invention disclosure, repeat no more in this with reference to the explanation among figure 9, Figure 10.

Please refer to Figure 12; What Figure 12 illustrated is that protection circuit 160 of the present invention is disposed at the situation in the chip 170.Protection circuit 160 is arranged between connection pad VCC (it can be a power supply connection pad), connection pad VSS (can be a ground connection pad) and the connection pad PD, with protection connection pad PD.This connection pad PD can be a signal and exports/go into connection pad; Perhaps, connection pad PD also can be another power supply connection pad (for example being connection pad VDD), is used for receiving the bias voltage that another differs from connection pad VCC.Be similar to the circuit arrangement among Figure 11, protection circuit 160 is to realize circuits for triggering, anti-circuits for triggering, a countercharge circuit and a transmission circuit respectively with transistor Mp, Mn, Ma and resistance R, with the triggering of control clamped circuit 166.Between the node Ni of connection pad PD and countercharge circuit (transistor Ma), then be provided with one and adjust circuit 162.In this embodiment, adjusting circuit 162 is to form an inverter with a p type metal oxide semiconductor transistor Me and a n-type metal oxide semiconductor transistor Mf, the source electrode of these two transistor Me, Mf is biased in voltage Vee and voltage Vss respectively, the visual input of an inverter for this reason of power level on the connection pad PD (voltage), the then visual output of an inverter for this reason of power level on the node Ni, and this output also just becomes the reference signal (being reference level) of countercharge circuit (transistor Ma).When chip 170 normal operations, voltage Vee and Vss just can be provided (for example being to be provided by internal circuit 164), adjustment circuit 162 can be operated.And when adjusting circuit 162 runnings, no matter the voltage swing on the connection pad PD why, adjusting circuit 162 can be with the voltage limit on the node Ni between voltage Vee and Vss.

When between connection pad PD and the connection pad VSS during false touch static power supply Vesd, clamped circuit 166 will be triggered and between this two connection pad conductive current path, the electric current of conduct static discharge; Relevant triggering/operation principles can repeat no more in this with reference to the embodiment among the figure 2.And when chip 170 during in normal operation, adjusting circuit 162 can be with the voltage limit on the node Ni between voltage Vee and Vss; In other words, as long as configure the value of voltage Vee, just can make between node Nm and node Ni has enough big voltage difference to keep the conducting of transistor Ma, with transistor Mn clamped circuit 166 is maintained at the state that is not triggered, avoids clamped circuit 166 to influence the normal operation of chip 170 via conducting.During adjustment circuit 162 in realizing Figure 12, because all being biased in, the source electrode of transistor Me and body level decide voltage Vee, so transistor Me can be general p type metal oxide semiconductor transistor, needn't realize with the p type metal oxide semiconductor transistor of multiple well structure (can with reference to Figure 10).

Please refer to Figure 13.Figure 13 is to be that example illustrates the consideration of the present invention in clamped circuit design/running aspect with the circuit among Fig. 5.In the example of Figure 13, protection circuit 180 of the present invention has been continued to use the interlock circuit configuration of protection circuit 50 among Fig. 5, also has identical functions and operation principles, with protection connection pad VDD, makes chip internal circuit 184 be unlikely the infringement that is subjected to static discharge.Comparatively different is that in the example of Figure 13, one or more diode DF in addition also can contact between clamped circuit 182 and the desire protection connection pad (being connection pad VDD in this example).This kind is to be used for preventing contingent breech lock (latch-up) phenomenon on the clamped circuit in the complementary circuit arrangement on the clamped circuit.For instance, clamped circuit 182 can be a thyristor (SCR, silicon-controlled rectifier); As is known to the person skilled in the art, one section retaining zone (holdingregion) is arranged in the current-voltage indicatrix of thyristor, just when the cross-pressure of thyristor reaches certain certain value gripping voltage V_hold, the cross-pressure of thyristor can almost keep necessarily, can increase with the electric current of flowing through hardly to change; And this section zone also just can be used to provide electrostatic discharge protective.But, when chip during in normal operation, also can trigger clamped circuit 182 mistakenly sometimes, clamped circuit 182 conducting and can't return back to original state voluntarily mistakenly influences the normal operation of chip, and this is the latch phenomenon of clamped circuit.For the anti-generation of latch phenomenon here, the multistage diode DF of polyphone just can be set as among Figure 13.Specifically, the feature sustaining voltage (V_hold) of thyristor adds the specified bias value of the diode cross-pressure summation that thyristor is connected in series (N*V_DF, wherein N is the number of diode DF, V_DF is the cross-pressure of diode) greater than connection pad VDD.Therefore, as long as the diode of selecting proper number, having appropriate characteristics just can prevent that latch phenomenon takes place improperly.Even by false triggering, clamped circuit 182 also can return back to not on-state because of electricity shortage to clamped circuit 182 in normal operation.In each embodiment of Fig. 2 to Figure 12, can guarantee all that the running of clamped circuit is correct in the present invention in this way.

In summary; in the time of will realizing electrostatic discharge protective mechanism for some desire protection connection pads (can be that connection pad is exported/gone into to power supply connection pad or signal); the present invention can utilize the capacity effect (similarly being decoupling capacitor) that originally just has between other power supply connection pad/ground connection pad that certain low-voltage is provided; with utilize desire protection connection pad therewith the voltage difference between low-voltage trigger clamped circuit, start electrostatic defending mechanism.Compared to existing/traditional electrostatic storage deflection (ESD) protection circuit, because the present invention can effectively utilize original capacity effect in the chip, so protection circuit of the present invention can be included electric capacity in, also therefore can reduce the layout area of electrostatic storage deflection (ESD) protection circuit, can realize electrostatic discharge protective mechanism more economically.In each embodiment of Fig. 2 to Figure 13, all available other the equivalent circuit of each interlock circuit replaces in the present invention.For example, the present invention has disclosed intermediate circuit between various connection pad (similarly being intermediate circuit 68,98 and 106 etc.) in Fig. 5, Fig. 7 and Fig. 8, the design of these intermediate circuits can be exchanged (for example being that intermediate circuit 98 with Fig. 7 replaces the intermediate circuit 68 among Fig. 5).In addition, similarly be Fig. 9 with Figure 12 in disclosed two kinds of different adjustment circuit 122 and 162 respectively, these two kinds to adjust circuit also interchangeable, for example is to adjust circuit 162 with the inverter among Figure 12 to replace adjustment circuit 122 among Fig. 9.And the clamped circuit among each embodiment can be realized with n-type metal oxide semiconductor transistor or thyristor or the like.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. electrostatic storage deflection (ESD) protection circuit, it is used for the preventing electro-static discharge incident; This electrostatic storage deflection (ESD) protection circuit includes:

One the one p type metal oxide semiconductor transistor has a drain electrode, a source electrode and that is connected in one first connection pad is connected in the grid of one second connection pad;

One first n-type metal oxide semiconductor transistor has the source electrode and that a grid, is connected in one the 3rd connection pad and is connected to a p type metal oxide semiconductor transistor drain;

One clamped circuit is connected between this first connection pad and one the 3rd connection pad; This clamped circuit is provided with a controlled end and is connected to a p type metal oxide semiconductor transistor drain;

One the 2nd p type metal oxide semiconductor transistor has the drain electrode that source electrode, that a grid, is connected to the transistorized grid of a p type metal oxide semiconductor connects the grid of this first n-type metal oxide semiconductor transistor; And

One adjusts circuit, is connected in this first connection pad and the transistorized grid of the 2nd p type metal oxide semiconductor, providing a reference level to the transistorized grid level of the 2nd p type metal oxide semiconductor,

Wherein the power level and the difference between the two that are higher than on this second connection pad of the power level on this first connection pad has surpassed the transistorized threshold voltage of a p type metal oxide semiconductor, a p type metal oxide semiconductor transistor turns then, produce a triggering signal with this clamped circuit of conducting

Wherein the power level on this second connection pad is higher than this reference level and difference has between the two surpassed the transistorized threshold voltage of the 2nd p type metal oxide semiconductor, then the 2nd p type metal oxide semiconductor transistor turns makes this first n-type metal oxide semiconductor transistor produce an anti-triggering signal to close this clamped circuit.

2. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this electrostatic storage deflection (ESD) protection circuit is located in the chip, and this second connection pad and the 3rd connection pad are used for making this chip can be biased between a positive voltage and the ground voltage respectively; And when this second connection pad was subjected to bias voltage, the power level on this second connection pad can be higher than the power level on this first connection pad, made the 2nd p type metal oxide semiconductor transistor turns.

3. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, it also includes:

One transmission circuit is connected between the transistorized grid of a p type metal oxide semiconductor and this second connection pad.

4. electrostatic storage deflection (ESD) protection circuit as claimed in claim 3, wherein this transmission circuit is a resistance.

5. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this adjustment circuit is a resistance.

6. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this adjustment circuit is a n-type metal oxide semiconductor transistor.

7. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, wherein, this adjustment circuit is an inverter.

8. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, it also includes:

One auxiliary circuit is connected between this controlled end and the 3rd connection pad; When the power level on this first connection pad is higher than power level on this second connection pad and difference between the two and has surpassed the transistorized threshold voltage of a p type metal oxide semiconductor, this auxiliary circuit can make the power level of this second connection pad reduce, and the power level difference of this second connection pad and this first connection pad is increased.

9. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, it also includes:

At least one diode is serially connected with between this clamped circuit and this first connection pad.

10. electrostatic storage deflection (ESD) protection circuit as claimed in claim 1, it also includes:

One intermediate circuit is connected between this first connection pad and this second connection pad, and in order to guaranteeing that the power level of this second connection pad can be lower than the power level of this first connection pad when this second connection pad is not accepted bias voltage, and difference between the two can surpass first definite value.