CN1713383A - Semiconductor device and ferroelectric memory, and method for manufacturing semiconductor device - Google Patents
Semiconductor device and ferroelectric memory, and method for manufacturing semiconductor device Download PDFInfo
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- CN1713383A CN1713383A CN200510073237.3A CN200510073237A CN1713383A CN 1713383 A CN1713383 A CN 1713383A CN 200510073237 A CN200510073237 A CN 200510073237A CN 1713383 A CN1713383 A CN 1713383A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
Provided is a semiconductor device which can allow a leak current even when it is a stack type and is reduced in size up to the necessary size. A capacitor 102 is formed of a lower electrode 111 provided over an SiO<SB>2</SB>layer 119 on an impurity layer 117 provided to a substrate 100, a ferrodielectric material 109 provided on the lower electrode 111, and an upper electrode 107 provided on the ferrodielectric material layer 109. Further, the capacitor 102 is provided with an SiO<SB>2</SB>layer 118 for electrically insulating the upper electrode 107 and wiring 105, a contact hole 103a to form a W-plug 113 for electrically connecting an impurity layer 117 and the lower electrode 111, and a contact hole 103b for electrically connecting the lower electrode 111 and wiring 105. The contact hole 103a and the contact hole 103b are opened mutually at the deviated locations in the plane of the capacitor 102.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device, ferroelectric memory and semiconductor device.
Background technology
Used ferroelectric memory (ferroelectric memory) to compare with the memory that has used insulating material etc. and had advantage low in energy consumption, this is that everybody knows.People are desirably in and further realize on the ferroelectric memory becoming more meticulous with highly integrated.But, the unit of ferroelectric memory also increases along with the reinforcement leakage current of the degree of becoming more meticulous generally speaking.Therefore, in the exploitation of ferroelectric memory, may diminish ferroelectric memory advantage low in energy consumption when becoming more meticulous when paying the utmost attention to.Thereby the size of unit need be considered scope that leakage current allows and to two aspects that require of the size of unit.
The cellular construction of ferroelectric memory has folded formula and plane.Fig. 5 is the schematic diagram of the memory cell structure of folded formula, and Fig. 5 (a) represents upper surface, and Fig. 5 (b) represents the cross section.Memory cell shown in Figure 5 has lower electrode 11, ferroelectric layer 9 and upper electrode 7.Formation plug 13 below lower electrode 11 does not electrically contact between illustrated ion implanted layer and the lower electrode 11 having.And, on upper electrode 7, SiO is arranged
2Deng dielectric film 15, on dielectric film 15, form wiring layer 5.Plug 13 forms by the metal of imbedding tungsten etc. in contact hole 3a.In addition, between wiring layer 5 and upper electrode 7, electrically contact by contact hole 3b.
In folded formula unit, directly over contact hole 3a, form contact hole 3b.Therefore, the upper surface of folded formula unit is the equal square in a limit and b limit among the figure.
Compare the advantage that the structure of shown folded formula unit exists the area occupied of unit to diminish with the plane that forms two contact holes in the position of separating.Therefore, consider, be preferably in and adopt folded formula unit in the product from the angle that becomes more meticulous of unit.But, the leakage current of folded formula unit is bigger than plane unit, if its by granular when wishing size, power consumption will reach the practical level that is unsuitable for.
Therefore, in the prior art, developed the technology of the plane unit downsizing that on power consumption, has advantage.As this prior art, enumerated the prior art of record in patent documentation 1.In patent documentation 1, adjust the contact hole position of plane unit, to dwindle the area occupied of unit, improve integrated level.In addition, in patent documentation 2, disclose the structure that varies in size of upper electrode and lower electrode, thereby further reduced the leakage current of plane unit.
Patent documentation 1: the spy opens flat 10-229168 communique
Patent documentation 2: the spy opens flat 10-65113 communique
Summary of the invention
But, above-mentioned prior art whichsoever all is to adopt the plane unit to realize technological improvement.Therefore, even also be difficult to realize the miniaturization of unit under the situation of the identical size of the cell size when having adopted folded formula unit.The present invention has overcome above-mentioned technological deficiency, its purpose is to be provided at and adopts when folding the formula unit, even also can make leakage current be positioned at the manufacture method of semiconductor device, ferroelectric memory and the semiconductor device of allowed band when reaching the size realization miniaturization that needs.
In order to solve above-mentioned technical problem, semiconductor device of the present invention comprises: stack capacitor portion comprises first electrode that is arranged on first insulating element, is arranged on the electric power storage parts on described first electrode and is arranged on second electrode on the described electric power storage parts; Second insulation division makes described second electrode and wiring part electric insulation; First contact hole in the described first insulating element upper shed, and is imbedded and is useful on the conductive layer that is electrically connected under described first insulating element and the conductive component of described first electrode; And second contact hole, in the described second insulating element upper shed, be used to be electrically connected second electrode and described wiring part, wherein, from the plane graph of described stack capacitor portion, the position upper shed that described first contact hole and described second contact hole are departing from mutually.
According to the invention of this structure, first electrode is set on insulating element, the electric power storage parts are set on first electrode, and on the electric power storage parts, second electrode are set, can form stack capacitor portion.In addition, on the insulating element under first electrode, make the first contact hole opening, fill to form plug, by filling in the conductive layer that can be electrically connected under first electrode and the insulating element with parts with conductivity.In addition, on the insulating element on second electrode, make the second contact hole opening, be electrically connected second electrode and wiring part.And, from the plane graph of stack capacitor portion, can be on the position of departing from mutually with first contact hole and the second contact hole opening.
The electric power storage parts are impaired because of forming plug.And, impaired when the contact hole that is connected with wiring forms.But, in the present invention, stagger mutually because of the strong impaired place of plug formation with because of contact hole forms strong impaired place.Therefore, the suffered overall damage of electric power storage parts relaxes, and can reduce the leakage current in the electric power storage parts of flowing through.Have the semiconductor device that the present invention of this structure can provide, realized that leakage current also is in the allowed band under the situation of miniaturization even when adopting folded formula, reached the size that needs.
In addition, semiconductor device of the present invention, from the plane graph of described stack capacitor portion, the bottom surface of described second contact hole not with the upper surface of described first contact hole opening overlappingly.
According to invention, stagger mutually because of the strong impaired place of plug formation with because of contact hole forms strong impaired place with this structure.Therefore, the suffered overall damage of electric power storage parts relaxes, and can reduce the leakage current in the electric power storage parts of flowing through.
In addition, in semiconductor device of the present invention, from the plane graph of described stack capacitor portion, the mode opening of described second contact hole to contact with the described first contact hole border.
According to invention with this structure, stagger mutually because of the strong impaired place of plug formation with because of contact hole forms strong impaired place, the while contact hole is close mutually as far as possible, thereby the area occupied realization of unit is minimized.
In addition, in semiconductor device of the present invention, from plane graph, described stack capacitor portion is roughly rectangle, described roughly rectangle is divided into two zones along its minor face, described first contact hole is formed on one of them zone, and described second contact hole is formed on another zone in the zone that forms with respect to first contact hole.
According to invention, can on the position of effectively avoiding the electric power storage components damage, form first contact hole and second contact hole with this structure.And, in the shared area of suppression capacitor portion, can reduce leakage current.
In addition, in semiconductor device of the present invention, described electric power storage parts are made of ferroelectric.
According to the invention with said structure, the present invention can be applied to and use in the semiconductor device of ferroelectric as the electric power storage parts.
In addition, ferroelectric memory of the present invention comprises above-mentioned each described semiconductor device.
According to above-mentioned invention, can provide the ferroelectric memory that comprises above-mentioned semiconductor device.
In addition, the manufacture method of semiconductor device provided by the invention comprises following operation: form first contact hole on first insulating element; Fill first contact hole with conductive component and form conductive plug; Formation first electrode layer on conductive plug, first electrode layer is electrically connected with local conductive layer under first insulating element by conductive plug; Upper surface at first electrode layer is provided with the electric power storage parts; Upper surface in the electric power storage component layer is provided with the second electrode lay; By a photoetching process (photolithography) operation first electrode layer, electric power storage parts, the second electrode lay are processed, formed stack capacitor portion; In stack capacitor portion, form second insulating element; And on described second insulating element and from the plane graph of described stack capacitor portion, see at position upper shed second contact hole that departs from described first contact hole.
According to above-mentioned invention, by first electrode is set, the electric power storage parts are set on first electrode on insulating element, and on the electric power storage parts, second electrode are set, thereby form stack capacitor portion.In addition,, fill to form plug, first electrode and local conductive layer are electrically connected by plug with parts with conductivity by on the insulating element under first electrode, making the first contact hole opening.In addition, insulating element upper shed second contact hole on second electrode is electrically connected second electrode and wiring part.And, from the plane graph of stack capacitor portion, can be on the position of departing from mutually with first contact hole and the second contact hole opening.
The electric power storage parts are impaired because of forming plug.And, impaired when the contact hole that is used for being connected with wiring forms.But, in the present invention, stagger mutually because of the strong impaired place of plug formation with because of contact hole forms strong impaired place.Therefore, the suffered overall damage of electric power storage parts relaxes, and can reduce the leakage current in the electric power storage parts of flowing through.The manufacture method of the semiconductor device that the present invention can provide has realized that leakage current also is in the allowed band under the situation of miniaturization even reaching the size that needs when adopting folded formula.
Description of drawings
Fig. 1 is the schematic diagram that the semiconductor device to one embodiment of the present of invention describes.
Fig. 2 is the process chart that the manufacture method to semiconductor device shown in Figure 1 describes.
Fig. 3 is another process chart that the manufacture method to semiconductor device shown in Figure 1 describes.
Fig. 4 is the schematic diagram that the technique effect to one embodiment of the present of invention describes.
Fig. 5 is the schematic diagram of the memory of existing folded formula unit.
Embodiment
Below, with reference to accompanying drawing, the embodiment of ferroelectric memory of the present invention is described.Fig. 1 is the schematic diagram that the ferroelectric memory to one embodiment of the present of invention describes, and Fig. 1 (a) is in the unit of ferroelectric memory, the upper surface figure of capacitor 102; Fig. 1 (b) is its sectional view.And in this manual, the upper surface figure shown in Fig. 1 (a) is corresponding to the plane graph of the capacitor department of the folded formula of the following stated.
Semiconductor device in the present embodiment is changed to ferroelectric memory.The impurity layer 117 of implanted dopant is arranged on the substrate as local conductive layer, at SiO as first insulating element on the impurity layer 117
2Form ferroelectric memory on the layer 119.And this ferroelectric memory comprises: as being arranged on SiO
2The lower electrode 111 of first electrode on the layer 119; As the ferroelectric layer 109 that is arranged on the electric power storage parts on the lower electrode 111; And as the upper electrode 107 that is arranged on second electrode on the ferroelectric layer 109.
And the semiconductor device of present embodiment has the wiring 105 that is arranged on the upper electrode 107.Wiring 105 comprises as the SiO at upper electrode 107 and second insulating element of electric insulation between 105 of connecting up
2Layer 118.At SiO
2Layer 119 upper shed contact hole 103a wherein imbed tungsten as conductive component, form W plug 113, are used for being electrically connected between impurity layer 117 and lower electrode 111.In addition, at SiO
2 Layer 118 upper shed contact hole 103b are used at upper electrode 107 and connect up being electrically connected between 105.
In the present embodiment, will be such as Ir/IrO
x/ Pt composite membrane will be such as Pt/IrO as lower electrode 111
x/ Ir composite membrane is as upper electrode 107.And, on ferroelectric layer 109, make PZT based material and PZTN based material.In addition, wiring 105 is made of aluminium, and impurity layer 117 is source electrode or the drain electrodes that are positioned at the transistor 120 on the substrate 100.And in the present embodiment, the structure representation that lower electrode 111, ferroelectric layer 109, upper electrode 107 are formed is a stack capacitor portion.In the present embodiment, capacitor department 102 is covered by the barrier film 115 that pellumina etc. constitutes.
In the present embodiment, contact hole 103a is first contact hole, and contact hole 103b is second contact hole.From the plane graph of capacitor department 102, the position upper shed that contact hole 103a and contact hole 103b are departing from mutually.
In the present embodiment, from plane graph, capacitor department 102 is roughly rectangle, with this roughly rectangle along (along) minor face is divided into two zones, contact hole 103a is formed on one of them regional 101a.In addition, contact hole 103b is formed on another regional 101b in the zone that forms with respect to contact hole 103.
In the present embodiment, by making contact hole 103a and contact hole 103b close, reduce the area occupied of unit 101.And from the plane graph of stack capacitor portion, contact hole 103a and contact hole 103b depart from mutually, thereby can make the influence that same area is not formed by contact hole or plug formation is brought of ferroelectric layer 109, and leakage current is reduced.According to this purpose, said position of departing from is preferred at least in the present embodiment, from the plane graph of capacitor department 102, the bottom surface 104b of contact hole 103b not with the upper surface 104a position overlapped of contact hole 103a.
And, in the present embodiment, from the condition of the area occupied of unit and leakage current as can be known, be that the mode of b limit twice forms unit 101 preferably with a limit in its upper surface.But, present embodiment is not limited to this structure, can be in the unit 101 area occupied when being minimized, the mode opening that contact hole 103b is contacted with contact hole 103a on the face of ferroelectric layer 109 with its border.
Fig. 2 (a)-(c) and Fig. 3 (a)-(c) are the process charts that the manufacture method to semiconductor device shown in Figure 1 describes.The semiconductor device of present embodiment is with method manufacturing described below.At first, in the present embodiment, with the SiO on the impurity layer 117
2The contact hole 103a opening of layer 119.Then, in contact hole 103a, imbed, to form W plug 113 such as tungsten.When formation W filled in 113, the upper surface 113a that will imbed tungsten was by CMP (Chemical Mechanical Polishing: chemico-mechanical polishing) abundant planarization such as method.
Then, at the SiO that has formed W plug 113
2Method by sputtering method etc. on the layer 119 forms Ir/IrO
x/ Pt composite membrane 111a.When forming Ir/IrO
xDuring/Pt composite membrane 111a,, form such as the TiAlN film in advance for preventing the tungsten oxidation.Then, coating is a ferroelectric material such as PZTN on Ir/IrOx/Pt composite membrane 111a, forms ferroelectric film 109a.And, on ferroelectric film 109a, form Pt/IrOx/Ir composite membrane 107a (Fig. 2 (b)) by sputtering method etc.
Then, at Pt/IrO
x/ Ir composite membrane 107a goes up the coating resist, forms the resist mask that meets cell configuration by photoetching process.By the etching that hops to it from this resist mask, thus time processing Ir/IrO
x/ Pt composite membrane 111a, ferroelectric film 109a, Pt/IrO
x/ Ir composite membrane 107a forms capacitor department 102 (Fig. 2 (c)).
And, in the present embodiment, as shown in Figure 3, with barrier film 115 covering capacitor portions 102 (Fig. 3 (a)), and, be provided with SiO
2Behind the layer 118, opening contact hole 103b (Fig. 3 (b)).As mentioned above, contact hole 103b in the scope on ferroelectric layer 109 tops and on the face of ferroelectric layer 109 not with the upper shed of contact hole 103a position overlapped.
And, utilize sputtering method on contact hole 103b, to produce the aluminium film, to 105 pattern-makings of connecting up, thereby form unit 101.
Fig. 4 is the schematic diagram that the effect to above-mentioned present embodiment describes, and wherein transverse axis is represented the value of leakage current, and the longitudinal axis is the distribution Z of unit ratio that represents to have each value of leakage current according to percentage.Leakage current is the value when having applied voltage 3V.In the ferroelectric memory of the data that obtained Fig. 4, as shown in Figure 1, be to be the data that a limit is obtained than the semiconductor device of the b length of side by cell configuration.In addition, in the present embodiment, the length on a limit is made as 2 μ m, the length on b limit is made as 1 μ m.
In Fig. 4, d2 represents that the data that obtained by the semiconductor device of present embodiment, d1 are the data for the semiconductor device of the equal in length on the length on a limit that relatively forms with d2 and b limit.The memory of the memory of acquisition data d1 and acquisition data d2 is with a collection of manufacturing.
According to Fig. 4,50% the leakage current of memory that can know present embodiment is smaller or equal to 2 μ A/cm
2In the scope of (representing) with I2 in scheming.And, can know with 50% leakage current of the memory of making in a collection of smaller or equal to 7 μ A/cm
2In the scope of (representing) with I1 in scheming.
According to the above embodiments, present embodiment can be provided at semiconductor device and the ferroelectric memory that adopts folded formula, but can reduce the leakage current of the memory of the folded formula unit of tradition, and the manufacture method of semiconductor device.According to present embodiment, semiconductor device and ferroelectric memory can be provided, wherein in the allowed band of leakage current, can realize the miniaturization of unit, and compare them with existing semiconductor devices and can either realize miniaturization, have the power consumption littler again than conventional semiconductor device, and the manufacture method of semiconductor device.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Description of reference numerals
100 substrates Unit 101
102 103a of capacitor section, 103b contact hole
104a upper surface 104b bottom surface
105 wirings, 107 upper electrodes
109 ferroelectric layers, 111 lower electrodes
113 W fill in 115 barrier films
117 impurity layers, 118,119 SiO
2Layer
120 transistors
Claims (7)
1. semiconductor device is characterized in that comprising:
Stack capacitor portion comprises first electrode that is arranged on first insulating element, is arranged on the electric power storage parts on described first electrode and is arranged on second electrode on the described electric power storage parts;
Second insulation division makes described second electrode and wiring part electric insulation;
First contact hole in the described first insulating element upper shed, and is imbedded the conductive layer that is used to be electrically connected under described first insulating element and the conductive component of described first electrode; And
Second contact hole in the described second insulating element upper shed, is used to be electrically connected described second electrode and described wiring part,
Wherein, from the plane graph of described stack capacitor portion, the position upper shed that described first contact hole and described second contact hole are departing from mutually.
2. semiconductor device according to claim 1 is characterized in that:
From the plane graph of described stack capacitor portion, described second contact hole is with not overlapping with the upper surface of described first contact hole mode opening in its bottom surface.
3. semiconductor device according to claim 1 and 2 is characterized in that:
From the plane graph of described stack capacitor portion, the mode opening of described second contact hole to contact with the described first contact hole border.
4. according to each described semiconductor device in the claim 1 to 3, it is characterized in that:
From plane graph, described stack capacitor portion is roughly rectangle, described roughly rectangle is divided into two zones along its minor face, described first contact hole is formed on one of them zone, and described second contact hole is formed on another zone with respect to the zone that forms described first contact hole.
5. according to each described semiconductor device in the claim 1 to 4, it is characterized in that:
Described electric power storage parts are made of ferroelectric.
6. ferroelectric memory is characterized in that:
Be equipped with according to each described semiconductor device in the claim 1 to 5.
7. the manufacture method of a semiconductor device is characterized in that comprising following operation:
On first insulating element, form first contact hole;
Fill described first contact hole with conductive component, form conductive plug;
Formation first electrode layer on described conductive plug, described first electrode layer is electrically connected with local conductive layer under described first insulating element by described conductive plug;
Upper surface at described first electrode layer is provided with the electric power storage parts;
Upper surface in described electric power storage component layer is provided with the second electrode lay;
By a photo-mask process described first electrode layer, described electric power storage parts, described the second electrode lay are processed, formed stack capacitor portion;
In described stack capacitor portion, form second insulating element; And
Form second contact hole on described second insulating element, from the plane graph of described stack capacitor portion, described second contact hole is in the position upper shed that departs from described first contact hole.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004188351 | 2004-06-25 | ||
| JP2004188351A JP4653426B2 (en) | 2004-06-25 | 2004-06-25 | Semiconductor device |
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|---|---|---|---|
| CN2008101278061A Division CN101312198B (en) | 2004-06-25 | 2005-06-01 | Semiconductor device |
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| CN1713383A true CN1713383A (en) | 2005-12-28 |
| CN100409445C CN100409445C (en) | 2008-08-06 |
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| CNB2005100732373A Active CN100409445C (en) | 2004-06-25 | 2005-06-01 | Semiconductor device and ferroelectric memory, and method for manufacturing semiconductor device |
| CN2008101278061A Active CN101312198B (en) | 2004-06-25 | 2005-06-01 | Semiconductor device |
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| US (1) | US7528490B2 (en) |
| JP (1) | JP4653426B2 (en) |
| CN (2) | CN100409445C (en) |
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|---|---|---|---|---|
| CN101055871B (en) * | 2006-04-13 | 2011-06-15 | 尔必达存储器股份有限公司 | Semiconductor storage device |
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| JP5426155B2 (en) * | 2008-12-19 | 2014-02-26 | ローム株式会社 | Semiconductor device |
| CN104659034B (en) * | 2015-02-10 | 2018-10-26 | 中国科学院物理研究所 | The preparation method of ferroelectric storage cell |
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| CN101055871B (en) * | 2006-04-13 | 2011-06-15 | 尔必达存储器股份有限公司 | Semiconductor storage device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100409445C (en) | 2008-08-06 |
| US7528490B2 (en) | 2009-05-05 |
| CN101312198B (en) | 2010-06-02 |
| US20050285276A1 (en) | 2005-12-29 |
| JP2006013138A (en) | 2006-01-12 |
| CN101312198A (en) | 2008-11-26 |
| JP4653426B2 (en) | 2011-03-16 |
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